Segmented redundancy calibration circuit, analog-to-digital converter and control method

Abstract

The invention discloses a segmented redundancy calibration circuit, an analog-to-digital converter and a control method, and is applied to the field of analog-to-digital conversion. Wherein the first end of the low-level-section capacitor array is connected with the first end of the high-level-section capacitor array and the first group of voltage input ends; the second end of the low-level section capacitor array is connected with the first end of the bridge capacitor and the first end of the calibration capacitor array; the second end of the high-bit-segment capacitor array is connected with the second end of the bridging capacitor, the second group of voltage input ends and the first input end of the comparator; the second end of the calibration capacitor array is grounded; the second input end of the comparator is connected with the second group of voltage input ends; wherein the specific value of the capacitors in the low-level-section capacitor array and the specific value of the capacitors in the high-level-section capacitor array independently follow the rule of underbinary. Therefore, the calibration function in the segmented redundancy calibration circuit is realized by controlling the number of capacitors, connected into the segmented redundancy calibration circuit, in the calibration capacitor array, so that the linearity of a final output signal is ensured.

Description

Technical Field

[0001] This application relates to the field of analog-to-digital conversion, and in particular to a segmented redundancy calibration circuit, an analog-to-digital converter, and a control method. Background Technology

[0002] In recent years, conventional successive approximation analog-to-digital converters (ADCs) have typically employed a pure capacitor matrix (CDAC) structure to reduce power consumption. However, the area of ​​a pure capacitor CDAC increases exponentially with increasing resolution N. Therefore, in high-precision (N≥12-bit) successive approximation ADCs, a segmented structure is usually used to reduce the size of the capacitor matrix. Segmented capacitor structures include... Figure 1 As shown, it consists of a low-order segment capacitor array, a high-order segment capacitor array, a comparator U, and a bridge capacitor C. B The low-level capacitor array includes L groups of capacitors, with capacitances starting from C. u If we consider this as a single unit, then the ratio of the capacitors in each group of the low-order segment capacitor array is: 1:2:4:......:2 L-1 The high-level capacitor array includes Q groups of capacitors, whose capacitance is C. u If we consider this as a single unit, then the ratio of the capacitors in each group of the high-order segment capacitor array is: 1:2:4:......:2 Q-1 In this configuration, the first terminal of each capacitor group is connected to the corresponding three-stage switch, and the second terminal of each capacitor group in the lower segment capacitor array is connected to the bridging capacitor C. B The first terminal is connected; the second terminal of each group of capacitors in the high-level capacitor array is connected to the bridging capacitor C. B The second terminal is connected to the non-inverting input of the comparator. The three-stage switch is connected to different voltage input terminals VIN, VREFP, and VREFN respectively; the inverting input of comparator U is grounded. Furthermore, there is a parasitic capacitance C in the low-order segment capacitor array. P2 Parasitic capacitance C exists in the high-order segment of the capacitor array. P1 Bridge capacitor C B Parasitic capacitance C exists P3 .

[0003] In this structure, the bridging capacitor C B Parasitic capacitance C between the upper and lower plates P3 Parasitic capacitance C in the low-level segment capacitor array P2 This will introduce weighting errors in the overall structure, resulting in nonlinearity in the final output signal of the ADC.

[0004] Given the above-mentioned technologies, finding a segmented redundancy calibration circuit is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a segmented redundancy calibration circuit, an analog-to-digital converter, and a control method. This can solve the problem of nonlinearity in the output signal caused by conventional pure capacitor CDAC structures in the prior art.

[0006] To address the aforementioned technical problems, this application provides a segmented redundancy calibration circuit, comprising: a low-order segment capacitor array, a high-order segment capacitor array, a comparator, a bridge capacitor, and a calibration capacitor array.

[0007] The first end of the low-side capacitor array is connected to the first end of the high-side capacitor array and to the first group of voltage input terminals; the second end of the low-side capacitor array is connected to the first end of the bridging capacitor and the first end of the calibration capacitor array.

[0008] The second terminal of the high-order segment capacitor array is connected to the second terminal of the bridge capacitor, the second group of voltage input terminals, and the first input terminal of the comparator.

[0009] The second terminal of the calibration capacitor array is grounded;

[0010] The second input terminal of the comparator is connected to the second set of voltage input terminals;

[0011] Among them, the ratio of capacitors in the low-order segment capacitor array and the ratio of capacitors in the high-order segment capacitor array both follow the under-binary rule individually.

[0012] Preferably, the calibration capacitor array includes N sets of calibration capacitor modules, where N is an integer greater than zero;

[0013] The first terminals of each group of calibration capacitor modules are connected together and together serve as the first terminal of the calibration capacitor array, which is connected to the second terminal of the low-level capacitor array and the first terminal of the bridging capacitor; the second terminals of each calibration capacitor module are connected together and together serve as the second terminal of the correction capacitor array, which is grounded.

[0014] Each calibration capacitor module group includes a first capacitor, a second capacitor, and a first switch, and the Mth calibration capacitor module group also includes a second switch; M is an integer greater than zero and less than N;

[0015] The first terminal of the first capacitor in each group of calibration capacitor modules serves as the first terminal of the calibration capacitor module, and the second terminal of the first capacitor is connected to the first terminal of the corresponding second capacitor and the first terminal of the first switch.

[0016] The first terminal of the second capacitor in the Mth calibration capacitor module is connected to the first terminal of the corresponding second switch, and the second terminal of the first switch is connected to the second terminal of the corresponding second switch, together serving as the second terminal of the Mth calibration capacitor module.

[0017] The second terminal of the second capacitor in the Nth group of calibration capacitor modules is connected to the second terminal of the corresponding first switch, and together they serve as the second terminal of the Nth group of calibration capacitor modules.

[0018] Preferably, both the low-side capacitor array and the high-side capacitor array include multiple capacitor modules with the same structure.

[0019] In this configuration, the first ends of each capacitor module in the low-side capacitor array are connected together and together serve as the first end of the low-side capacitor array, which is connected to the first group of voltage input terminals. The second ends of each capacitor module in the low-side capacitor array are all connected together and serve as the second end of the low-side capacitor array, which is connected to the first end of the bridging capacitor and the first end of the calibration capacitor array.

[0020] The first terminals of each capacitor module in the high-order segment capacitor array are connected together, and together they serve as the first terminal of the high-order segment capacitor array, which is connected to the first group of voltage input terminals. The second terminals of each capacitor module in the high-order segment capacitor array are connected together, and together they serve as the second terminal of the high-order segment capacitor array, which is connected to the second terminal of the bridge capacitor, the second group of voltage input terminals, and the first input terminal of the comparator.

[0021] Preferably, the capacitor module includes: a third capacitor and a three-position switch;

[0022] In this configuration, the first end of the three-segment switch serves as the first end of the capacitor module, and the second end of the three-segment switch is connected to the first end of the third capacitor.

[0023] The second terminal of the third capacitor serves as the second terminal of the capacitor module.

[0024] Preferably, it further includes: a grounding capacitor;

[0025] Among them, the first end of the grounding capacitor is connected to the second end of the low-level capacitor array and the first end of the calibration capacitor array.

[0026] The second terminal of the grounding capacitor is grounded.

[0027] Preferably, it further includes: a parasitic capacitance calibration logic unit and a temperature code conversion unit;

[0028] The input of the parasitic capacitance calibration logic unit is connected to the output of the comparator and is used to determine the corresponding correction signal based on the comparison signal output by the comparator.

[0029] The input of the temperature code conversion unit is connected to the output of the parasitic capacitance calibration logic unit, and is used to convert the calibration signal into the corresponding temperature code signal so as to control the calibration capacitor array according to the temperature code signal.

[0030] Preferably, it further includes: a successive approximation logic unit and an output conversion unit;

[0031] The input of the successive approximation logic unit is connected to the output of the comparator, and is used to determine the corresponding target signal based on the comparison signal output by the comparator.

[0032] The input terminal of the output conversion unit is connected to the output terminal of the successive approximation logic unit, and is used to convert the target signal into the corresponding output signal.

[0033] On the other hand, this application also provides an analog-to-digital converter including the segmented redundancy calibration circuit described above.

[0034] On the other hand, this application also provides a segmented redundancy calibration circuit control method, applied to the above-mentioned segmented redundancy calibration circuit, comprising:

[0035] Switch the voltage inputs from the low-order capacitor array and the high-order capacitor array to the first group of voltage input terminals;

[0036] Obtain the high-level correction voltage corresponding to the high-level capacitor array;

[0037] The correction signals corresponding to the high-level correction voltage and the threshold voltage are determined based on the comparator.

[0038] The number of capacitors in the calibration capacitor array that are connected to or de-connected to the segmented redundant calibration circuit is controlled according to the correction signal.

[0039] Preferably, it further includes:

[0040] Determine whether a calibration termination signal has been received;

[0041] If a signal indicating termination of calibration is received, it is determined that the calibration of the current segmented redundancy calibration circuit has ended.

[0042] If no correction termination signal is received, return to the step of determining the correction signal corresponding to the high-order correction voltage and the threshold voltage based on the comparator.

[0043] This application provides a segmented redundancy calibration circuit, comprising: a low-order segment capacitor array, a high-order segment capacitor array, a comparator, a bridge capacitor, and a calibration capacitor array. The first terminal of the low-order segment capacitor array is connected to the first terminal of the high-order segment capacitor array and to a first set of voltage input terminals. The second terminal of the low-order segment capacitor array is connected to the first terminal of the bridge capacitor and the first terminal of the calibration capacitor array. The second terminal of the high-order segment capacitor array is connected to the second terminal of the bridge capacitor, a second set of voltage input terminals, and the first input terminal of the comparator. The second terminal of the calibration capacitor array is grounded. The second input terminal of the comparator is connected to the second set of voltage input terminals. The ratios of the capacitors in the low-order segment capacitor array and the high-order segment capacitor array each individually follow a sub-binary rule. Therefore, the overall structure of this application employs a redundant structure, and thus the ratios of the capacitors in the low-order segment capacitor array and the high-order segment capacitor array each individually follow a sub-binary rule. Furthermore, in this application, the voltage value of the first group of voltage input terminals is switched to obtain the signal output from the comparator output terminal. This signal is used to control the calibration capacitor array, thereby controlling the number of capacitors connected to the segmented redundant calibration circuit in the calibration capacitor array, so as to realize the calibration function in the segmented redundant calibration circuit and ensure the linearity of the final output signal. Attached Figure Description

[0044] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 A circuit diagram of a segmented capacitor structure provided in the prior art;

[0046] Figure 2 A circuit diagram of the segmented redundancy calibration circuit provided in the embodiments of this application;

[0047] Figure 3 A circuit diagram of the calibration capacitor array provided in the embodiments of this application;

[0048] Figure 4 A complete circuit diagram of the segmented redundancy calibration circuit provided in the embodiments of this application;

[0049] Figure 5 A flowchart of a segmented redundancy calibration circuit control method provided in this application embodiment;

[0050] Figure 6 The control logic structure diagram of the segmented redundancy calibration circuit provided in the embodiments of this application;

[0051] Figure 7The signal waveform diagram of the segmented redundancy calibration circuit provided in the embodiment of this application. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0053] The core of this application is to provide a segmented redundancy calibration circuit, an analog-to-digital converter, and a control method.

[0054] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0055] To address the aforementioned technical problems, this application provides a segmented redundancy calibration circuit, such as... Figure 2 The diagram shows: a low-order segment capacitor array 1, a high-order segment capacitor array 2, a comparator U, and a bridge capacitor C. B In addition to calibration capacitor array 3, Figure 1 It also includes: a first group of voltage input terminals 4 and a second group of voltage input terminals 5. The circuit connection is as follows: the first terminal of the low-order segment capacitor array 1 is connected to the first terminal of the high-order segment capacitor array 2, and is also connected to the first group of voltage input terminals 4; the second terminal of the low-order segment capacitor array 1 is connected to the bridging capacitor C. B The first terminal is connected to the first terminal of the calibration capacitor array 3; the second terminal of the high-level capacitor array 2 is connected to the bridging capacitor C. B The second terminal of the second voltage input terminal 5 is connected to the first input terminal of the comparator U; the second terminal of the calibration capacitor array 3 is grounded; the second input terminal of the comparator U is connected to the second voltage input terminal 4; wherein, the ratio of the capacitors in the low-order segment capacitor array 1 and the ratio of the capacitors in the high-order segment capacitor array 2 both follow the sub-binary rule individually.

[0056] In specific embodiments, both the low-order segment capacitor array 1 and the high-order segment capacitor array 2 are conventional structures. However, the ratios of the capacitors in the low-order segment capacitor array 1 and the high-order segment capacitor array 2 in these conventional structures follow traditional binary rules. Taking the low-order segment capacitor array 1 as an example: when the low-order segment capacitor array 1 includes L groups of capacitors, its capacitance is expressed as C... u If we consider each capacitor as a unit, then the ratio of the capacitors in the lower segment capacitor array 1 is: 1:2:4:......:2 L-1However, in this application, to ensure the linearity of the subsequent output signal, redundancy is added. Therefore, the ratio of capacitors in the low-order segment capacitor array 1 and the ratio of capacitors in the high-order segment capacitor array 2 both individually follow the sub-radix-2 rule. In traditional binary, the radix factor is 2, and each bit has a weight of 2. N In binary, the ratio between adjacent bits is 2. However, in sub-radix-2, the radix factor is less than 2 and greater than or equal to 1; that is, the ratio between adjacent bits is no longer 2, but a ratio less than 2 and greater than or equal to 1. In this case, N represents the bit position. N This represents the weight of each bit. Taking a 4-bit system as an example, the weights of the 4 bits are 1, 2, 4, and 8, with a total weight of 15. If the base is equal to 1, it is equivalent to expanding the 4 bits into a 15-bit redundancy, with each bit having a weight of 1 and a total weight of 15. The value of N ranges from 0 to the total number of bits - 1. Taking a 4-bit system as an example, the value of N is 0 to 3. In this application, we take an 8-bit system with a 4:4 segmentation as an example, where the high-order segment capacitor array 2 is 4 bits and the low-order segment capacitor array 1 is 4 bits. With the addition of 3 bits of redundancy, the 8 bits are expanded into 11 bits. Therefore, the number of unit capacitors per bit is [6 4 2 2 1 1 6 4 2 2 1]. The scaling ratio at the segmentation is 15, and the weight corresponding to each bit is [90 60 30 30 15 15 6 4 2 2 1]. The specific data is shown in Table 1.

[0057] Table 1

[0058]

[0059] Taking a 12-bit 6:6 segmentation as an example, the high-order segment capacitor array 2 is 6 bits and the low-order segment capacitor array 1 is 6 bits. With the addition of 3 bits of redundancy, the 12 bits are expanded to 15 bits. The scaling ratio at the segmentation is 45. The specific data is shown in Table 2.

[0060] Table 2

[0061]

[0062] Taking a 12-bit 6:6 segmentation as an example, the high-order segment capacitor array 2 is 6 bits and the low-order segment capacitor array 1 is 6 bits. With the addition of 3 bits of redundancy, the 12 bits are expanded to 15 bits. The scaling ratio at the segmentation is 35. The specific data is shown in Table 3.

[0063] Table 3

[0064]

[0065] In this embodiment, considering the need for layout matching and correction, the bridging capacitor C... B You should choose an integer multiple of C. u For example: C B =2C u However, this application is not limited and users can set it themselves according to their needs.

[0066] The circuit principle of this application is as follows: when the first group of voltage input terminals 4 is switched as the power supply voltage for the low segment capacitor array 1 and the high segment capacitor array 2, the high segment correction voltage corresponding to the high segment capacitor array 2 will change; therefore, at this time, the comparator U compares the high segment correction voltage obtained from the first input terminal with the threshold voltage obtained from the second input terminal, and outputs the comparison result to control the number of capacitors connected to or not connected to the segmented redundant calibration circuit in the calibration capacitor array 3, so as to realize the calibration function in the segmented redundant calibration circuit and ensure the linearity of the final output signal.

[0067] Among them, the calibration capacitor array 3 is a preferred option, and can use 2 C u The structure can be cascaded, but this application is not limited to this; users can configure it according to their needs.

[0068] This application provides a segmented redundancy calibration circuit, comprising: a low-order segment capacitor array, a high-order segment capacitor array, a comparator, a bridge capacitor, and a calibration capacitor array. The first terminal of the low-order segment capacitor array is connected to the first terminal of the high-order segment capacitor array and to a first set of voltage input terminals. The second terminal of the low-order segment capacitor array is connected to the first terminal of the bridge capacitor and the first terminal of the calibration capacitor array. The second terminal of the high-order segment capacitor array is connected to the second terminal of the bridge capacitor, a second set of voltage input terminals, and the first input terminal of the comparator. The second terminal of the calibration capacitor array is grounded. The second input terminal of the comparator is connected to the second set of voltage input terminals. The ratios of the capacitors in the low-order segment capacitor array and the high-order segment capacitor array each individually follow a sub-binary rule. Therefore, the overall structure of this application employs a redundant structure, and thus the ratios of the capacitors in the low-order segment capacitor array and the high-order segment capacitor array each individually follow a sub-binary rule. Furthermore, in this application, the voltage value of the first group of voltage input terminals is switched to obtain the signal output from the comparator output terminal. This signal is used to control the calibration capacitor array, thereby controlling the number of capacitors connected to the segmented redundant calibration circuit in the calibration capacitor array, so as to realize the calibration function in the segmented redundant calibration circuit and ensure the linearity of the final output signal.

[0069] Based on the above embodiments, such as Figure 3As shown, the calibration capacitor array 3 includes N groups of calibration capacitor modules, where N is an integer greater than zero; wherein, the first terminals of each group of calibration capacitor modules are connected together, and together they serve as the first terminal of the calibration capacitor array, the second terminal of the lower segment capacitor array 1, and the bridging capacitor C. B The first terminal of each calibration capacitor module is connected; the second terminals of each calibration capacitor module are connected and together serve as the second terminal of the calibration capacitor array grounded. Each group of calibration capacitor modules includes a first capacitor C1, a second capacitor C2, and a first switch K1, and the Mth group of calibration capacitor modules also includes a second switch K2; M is an integer greater than zero and less than N. The first terminal of the first capacitor C1 in each group of calibration capacitor modules serves as the first terminal of the calibration capacitor module, and the second terminal of the first capacitor C1 is connected to the first terminal of the corresponding second capacitor C2 and the first terminal of the first switch K1. In the Mth group of calibration capacitor modules, the first terminal of the second capacitor C2 is connected to the first terminal of the corresponding second switch K2, and the second terminal of the first switch K1 is connected to the second terminal of the corresponding second switch K2, together serving as the second terminal of the Mth group of calibration capacitor modules. In the Nth group of calibration capacitor modules, the second terminal of the second capacitor C2 is connected to the second terminal of the corresponding first switch K1, together serving as the second terminal of the Nth group of calibration capacitor modules. Each capacitor is a capacitor unit C. u .

[0070] In a specific embodiment, all switches in the calibration capacitor array 3 are turned on first, at which point only the Nth group of calibration capacitor modules is connected, and the total connected capacitance is 0.5C. u In this structure, the capacitance increases by 0.5C for each closed switch. u When the switch receives a signal from the comparator U, it determines whether to turn it off, thereby adjusting the number of capacitors added to the segmented redundancy calibration circuit in real time.

[0071] Based on the above embodiments, as a preferred embodiment, such as Figure 4 As shown (where, Figure 4 In the circuit shown, the low-side capacitor array 1 includes five capacitor modules, and the high-side capacitor array 2 includes six capacitor modules. Both the low-side capacitor array 1 and the high-side capacitor array 2 include multiple capacitor modules with the same structure. The first terminals of each capacitor module in the low-side capacitor array 1 are connected and together serve as the first terminal of the low-side capacitor array 1, connected to the first group of voltage input terminals 4. The second terminals of each capacitor module in the low-side capacitor array 1 are all connected and serve as the second terminal of the low-side capacitor array 1, connected to the bridging capacitor C. BThe first terminal is connected to the first terminal of the calibration capacitor array 3; the first terminals of each capacitor module in the high-level capacitor array 2 are connected together, and together they serve as the first terminal of the high-level capacitor array 2, which is connected to the first group of voltage input terminals 4; the second terminals of each capacitor module in the high-level capacitor array 2 are connected together, and together they serve as the second terminal of the high-level capacitor array 2, which is connected to the bridging capacitor C. B The second terminal, the second group of voltage input terminals 5, and the first input terminal of comparator U are connected. The capacitor module specifically includes: a third capacitor C3 and a three-position switch K3; wherein, the first terminal of the three-position switch K3 serves as the first terminal of the capacitor module, and the second terminal of the three-position switch K3 is connected to the first terminal of the third capacitor C3; the second terminal of the third capacitor C3 serves as the second terminal of the capacitor module.

[0072] The first group of voltage input terminals 4 includes a VIN voltage input terminal, a VRP voltage input terminal, and a ground terminal; the second group of voltage input terminals 5 is a VCM voltage input terminal.

[0073] Since the above circuit structure is a conventional pure capacitor matrix (CDAC) structure, its circuit principle will not be described in detail here.

[0074] In the circuit structure, due to the presence of bridging capacitors C that are integer multiples of the original capacitor units... B Therefore, a grounding capacitor C needs to be added at the connection point of the low-level capacitor array 1. G This is used to balance the total weight in the low-level capacitor array 1 and the weight of the last element in the high-level capacitor array 2. The grounding capacitor C... G Specifically, how many times the unit capacitance C? u Users can customize the settings according to their needs.

[0075] besides, Figure 4 The system also includes: a parasitic capacitance calibration logic unit 6, a temperature code conversion unit 7, a successive approximation logic unit 8, and an output conversion unit 9. The input of the parasitic capacitance calibration logic unit 7 is connected to the output of comparator U, and it determines the corresponding correction signal based on the comparison signal output by comparator U. The correction signal is a binary signal. The input of the temperature code conversion unit 7 is connected to the output of the parasitic capacitance calibration logic unit 6, and it converts the correction signal into a corresponding temperature code signal to control the calibration capacitor array 3. The temperature code signal is a 15-bit signal. The input of the successive approximation logic unit 8 is connected to the output of comparator U, and it determines the corresponding target signal based on the comparison signal output by comparator U. The input of the output conversion unit 9 is connected to the output of the successive approximation logic unit 8, and it converts the target signal into a corresponding output signal to control external circuits. Both the target signal and the output signal are binary signals.

[0076] It should be noted that the calibration process mentioned in this application is a repetitive process. That is, when the comparator U outputs the first comparison signal, the parasitic capacitance calibration logic unit 6 outputs the corresponding first calibration signal, the temperature code conversion unit 7 outputs the corresponding first temperature code signal, and controls the calibration capacitor array 3 to achieve the first calibration. After the first calibration, the comparator U outputs the second comparison signal, the parasitic capacitance calibration logic unit 6 outputs the corresponding second calibration signal, the temperature code conversion unit 7 outputs the corresponding second temperature code signal, and controls the calibration capacitor array 3 to achieve the second calibration. This process is repeated until the final output signal meets the requirements.

[0077] It should be noted that the embodiments provided in this application are only one possible implementation method, but are not limited to this only implementation method. Users can set their own implementation methods according to their needs.

[0078] This application provides a segmented redundancy calibration circuit, comprising: a low-order segment capacitor array, a high-order segment capacitor array, a comparator, a bridge capacitor, and a calibration capacitor array. The first terminal of the low-order segment capacitor array is connected to the first terminal of the high-order segment capacitor array and to a first set of voltage input terminals. The second terminal of the low-order segment capacitor array is connected to the first terminal of the bridge capacitor and the first terminal of the calibration capacitor array. The second terminal of the high-order segment capacitor array is connected to the second terminal of the bridge capacitor, a second set of voltage input terminals, and the first input terminal of the comparator. The second terminal of the calibration capacitor array is grounded. The second input terminal of the comparator is connected to the second set of voltage input terminals. The ratios of the capacitors in the low-order segment capacitor array and the high-order segment capacitor array each individually follow a sub-binary rule. Therefore, the overall structure of this application employs a redundant structure, and thus the ratios of the capacitors in the low-order segment capacitor array and the high-order segment capacitor array each individually follow a sub-binary rule. Furthermore, in this application, the voltage value of the first group of voltage input terminals is switched to obtain the signal output from the comparator output terminal. This signal is used to control the calibration capacitor array, thereby controlling the number of capacitors connected to the segmented redundant calibration circuit in the calibration capacitor array, so as to realize the calibration function in the segmented redundant calibration circuit and ensure the linearity of the final output signal.

[0079] On the other hand, this application also provides an analog-to-digital converter including the above-described segmented redundancy calibration circuit, and having the same beneficial effects. The specific embodiments of the analog-to-digital converter are the same as those of the above-described segmented redundancy calibration circuit, and therefore will not be described in detail here.

[0080] On the other hand, this application also provides a segmented redundancy calibration circuit control method, applied to the aforementioned segmented redundancy calibration circuit, such as... Figure 5 As shown, the process includes the following:

[0081] S10: Switch the input voltage of the low-order capacitor array and the high-order capacitor array to the first group of voltage input terminals.

[0082] S11: Obtain the high-segment correction voltage corresponding to the high-segment capacitor array.

[0083] S12: Determine the correction signal corresponding to the high-level correction voltage and the threshold voltage based on the comparator.

[0084] S13: Control the number of capacitors in the calibration capacitor array that are connected to or de-connected to the segmented redundant calibration circuit according to the calibration signal.

[0085] This also includes:

[0086] Determine whether a calibration termination signal has been received;

[0087] If a signal indicating termination of calibration is received, it is determined that the calibration of the current segmented redundancy calibration circuit has ended.

[0088] If no correction termination signal is received, return to the step of determining the correction signal corresponding to the high-order correction voltage and the threshold voltage based on the comparator.

[0089] In a specific embodiment, Figure 4 Based on Table 1, such as Figure 6 and Figure 7 As shown, the upper plate is connected to a common-mode voltage, V MSB =VCM; At this time, the last lower plate in the high-side capacitor array 2, i.e., point ①, is connected to the reference voltage VRP, the remaining lower plates in the high-side capacitor array 2 are grounded, and all lower plates in the low-side capacitor array 1, i.e., point ②, are grounded. When the lower plate at point ① switches to the ground terminal (ground potential), and the lower plate at point ② switches to the reference voltage VRP, due to the corresponding parasitic capacitances in the high-side capacitor array 2 and the low-side capacitor array 1, the two voltage switching will inevitably lead to a change in the upper plate voltage V during the correction phase. MSB The change, i.e., V MSB ≠VCM, at this time, comparator U compares V... MSB The difference between the value of VCM and the value of VCM generates a judgment result and the first correction signal CAL_B. <3> Then it is converted into the first temperature code signal CAL_T<14:0>, which controls the calibration capacitor array 3 to connect or not connect the corresponding number of capacitors.

[0090] In this application, the correction logic adopts a preset 1 control form, such as... Figure 7 As shown, when the sampling signal CK_SAM is high, the first correction signal CAL_B <3> The capacitor is pre-set to 1, other control signals are 0, and half of the capacitors in calibration capacitor array 3 are pre-connected. When the comparator clock CK_CMP is high, V... MSBCompared with VCM, when CK_CMP falls, CAL_B <3> Based on the output of comparator U, choose to either set the value to 1 or 0; repeat the above correction process to generate the second correction signal CAL_B. <2> And so on, until the last correction signal CAL_B. <0> This completes the correction of parasitic capacitance.

[0091] Among them, the switching of point ① affects the voltage V of the upper plate. MSB The change is:

[0092] dV MSB1 =VRP×(C a +C Lt ) / [16(2C u +C Lt )+2C Lt ];

[0093] Among them, C a =2C u +C P3 C Lt =15C u +12C u +C cal +C P2 ;

[0094] ② The switching of point voltage affects the voltage V of the upper plate. MSB The change is:

[0095] dV MSB2 =VRP×(15×C a ) / [16(2C u +C Lt )+2C Lt ];

[0096] If the weights are equal, then dV MSB1= dV MSB2 C a +C Lt =15×C a Therefore, the required capacitance value in calibration capacitor array 3 is: C cal =C u +14C P3 -C P2 In the ideal case where land parasitism is not considered, then C cal =C u .

[0097] Among them, C P2 C is the parasitic capacitance in the low-order segment capacitor array 1; P3 For bridging capacitor C B Parasitic capacitance; C calTo calibrate the total capacitance in capacitor array 3.

[0098] Therefore, this application provides a segmented redundancy calibration circuit control method, applied to the aforementioned segmented redundancy calibration circuit, which includes switching the voltages in the low-order segment capacitor array and the high-order segment capacitor array at the first group of voltage input terminals; obtaining the high-order correction voltage corresponding to the high-order segment capacitor array; determining the correction signal corresponding to the high-order correction voltage and the threshold voltage based on a comparator; and controlling the number of capacitors in the calibration capacitor array that are connected to / not connected to the segmented redundancy calibration circuit according to the correction signal. The segmented redundancy calibration circuit includes: a low-order segment capacitor array, a high-order segment capacitor array, a comparator, a bridge capacitor, and a calibration capacitor array. The first terminal of the low-order segment capacitor array is connected to the first terminal of the high-order segment capacitor array and to the first group of voltage input terminals. The second terminal of the low-order segment capacitor array is connected to the first terminal of the bridge capacitor and the first terminal of the calibration capacitor array. The second terminal of the high-order segment capacitor array is connected to the second terminal of the bridge capacitor, the second group of voltage input terminals, and the first input terminal of the comparator. The second terminal of the grounding capacitor and the second terminal of the calibration capacitor array are both grounded. The second input terminal of the comparator is connected to the second group of voltage input terminals. The ratios of the capacitors in the low-order segment capacitor array and the high-order segment capacitor array each individually follow a sub-binary rule. Therefore, the redundant structure adopted in this application ensures that the ratios of the capacitors in the low-order segment capacitor array and the high-order segment capacitor array each individually follow a sub-binary rule. Simultaneously, this application obtains the signal output from the comparator output by switching the voltage value of the first group of voltage input terminals. This signal controls the calibration capacitor array, thereby controlling the number of capacitors connected to the segmented redundant calibration circuit in the calibration capacitor array, to realize the calibration function in the segmented redundant calibration circuit and ensure the linearity of the final output signal. When the segmented redundant calibration circuit also includes a grounding capacitor, the grounding capacitor is used to balance the total weight of the lower segment capacitor array and the weight of the last element of the higher segment capacitor array. In other words, this application, through a special segmented scaling ratio and redundant structure, makes the total weight of the lower segment capacitor array equal to the weight of the last element of the higher segment capacitor array. Therefore, it is not necessary to insert an additional reference capacitor in the higher segment capacitor array to make it equal to the total weight of the lower segment capacitor array. In the calibration stage, the same effect as inserting an external reference capacitor can be achieved simply by switching the voltage of the lower plate of the last capacitor in the existing higher segment capacitor array.

[0099] The foregoing has provided a detailed description of the segmented redundancy calibration circuit, analog-to-digital converter, and control method provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0100] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A segmented redundant calibration circuit, comprising: The application relates to a low-bit segment capacitor array, a high-bit segment capacitor array, a comparator, a bridging capacitor and a calibration capacitor array. The first end of the low-bit segment capacitor array is connected with the first end of the high-bit segment capacitor array and a first group of voltage input ends; the second end of the low-bit segment capacitor array is connected with the first end of the bridging capacitor and the first end of the calibration capacitor array; The second end of the high-bit segment capacitor array is connected with the second end of the bridging capacitor, a second group of voltage input ends and the first input end of the comparator; The second end of the calibration capacitor array is grounded; The second input end of the comparator is connected with the second group of voltage input ends; The ratio of the capacitors in the low-bit segment capacitor array and the high-bit segment capacitor array separately follows the rule of under-binary. The calibration capacitor array comprises N groups of calibration capacitor modules, and N is an integer greater than zero; 2. The segmented redundant calibration circuit of claim 1, wherein, The first end of each group of calibration capacitor modules is connected, and is connected with the second end of the low-bit segment capacitor array and the first end of the bridging capacitor as the first end of the calibration capacitor array; the second end of each calibration capacitor module is connected, and is grounded as the second end of the calibration capacitor array; Each group of calibration capacitor modules comprises a first capacitor, a second capacitor and a first switch, and the Mth group of calibration capacitor modules further comprises a second switch; M is an integer greater than zero and smaller than N; The first end of the first capacitor in each group of calibration capacitor modules is the first end of the calibration capacitor module, and the second end of the first capacitor is connected with the first end of the corresponding second capacitor and the first end of the first switch; The first end of the second capacitor in the Mth group of calibration capacitor modules is connected with the first end of the corresponding second switch, the second end of the first switch is connected with the second end of the corresponding second switch, and they are connected as the second end of the Mth group of calibration capacitor modules; The second end of the second capacitor in the Nth group of calibration capacitor modules is connected with the second end of the corresponding first switch, and they are connected as the second end of the Nth group of calibration capacitor modules. The low-bit segment capacitor array and the high-bit segment capacitor array each comprise a plurality of capacitor modules with the same structure; 3. The segmented redundant calibration circuit of claim 1, wherein, The first end of each capacitor module in the low-bit segment capacitor array is connected, and is connected with the first group of voltage input ends as the first end of the low-bit segment capacitor array; the second end of each capacitor module in the low-bit segment capacitor array is connected, and is connected with the first end of the bridging capacitor and the first end of the calibration capacitor array as the second end of the low-bit segment capacitor array; The first end of each capacitor module in the high-bit segment capacitor array is connected, and is connected with the first group of voltage input ends as the first end of the high-bit segment capacitor array; the second end of each capacitor module in the high-bit segment capacitor array is connected, and is connected with the second end of the bridging capacitor, the second group of voltage input ends and the first input end of the comparator as the second end of the high-bit segment capacitor array. The capacitor module comprises a third capacitor and a three-segment switch.

4. The segmented redundant calibration circuit of claim 3, wherein, ​ The first end of the three-section switch is the first end of the capacitor module, and the second end of the three-section switch is connected with the first end of the third capacitor. The second end of the third capacitor is the second end of the capacitor module.

5. The segmented redundant calibration circuit of claim 1, wherein, Further comprising: a ground capacitor; The first end of the ground capacitor is connected with the second end of the low-bit capacitor array and the first end of the calibration capacitor array. The second end of the ground capacitor is grounded.

6. The segmented redundant calibration circuit of claim 1, wherein, Further comprising: a parasitic capacitor calibration logic unit and a temperature code conversion unit; The input end of the parasitic capacitor calibration logic unit is connected with the output end of the comparator, and is configured to determine a corresponding correction signal according to a comparison signal output by the comparator; 7. The segmented redundant calibration circuit of claim 1, wherein, The input end of the temperature code conversion unit is connected with the output end of the parasitic capacitor calibration logic unit, and is configured to convert the correction signal into a corresponding temperature code signal, so as to control the calibration capacitor array according to the temperature code signal. Further comprising: a successive approximation logic unit and an output conversion unit; The input end of the successive approximation logic unit is connected with the output end of the comparator, and is configured to determine a corresponding target signal according to a comparison signal output by the comparator; 8. An analog-to-digital converter, characterized by The input end of the output conversion unit is connected with the output end of the successive approximation logic unit, and is configured to convert the target signal into a corresponding output signal.

9. A segmented redundancy calibration circuit control method, characterized in that, The segmented redundancy calibration circuit comprises the segmented redundancy calibration circuit according to any one of claims 1-7. The segmented redundancy calibration circuit according to claim 1 comprises: switching the first group of voltage input ends to input voltages in the low-bit capacitor array and the high-bit capacitor array; obtaining a high-bit correction voltage corresponding to the high-bit capacitor array; determining a correction signal corresponding to the high-bit correction voltage and a threshold voltage based on a comparator; 10. The method of claim 9, wherein, controlling the number of capacitors in the calibration capacitor array to access / abandon to access the segmented redundancy calibration circuit according to the correction signal. Further comprising: determining whether a correction termination signal is received; if the correction termination signal is received, determining that the current segmented redundancy calibration circuit correction is completed; if the correction termination signal is not received, returning to the step of determining the correction signal corresponding to the high-bit correction voltage and the threshold voltage based on the comparator.

Images