Preparation method of inner side wall and preparation method of semiconductor device

Abstract

The embodiment of the invention provides a preparation method of an inner side wall, which comprises the following steps: before forming a first dielectric layer, firstly removing false side walls at two sides of a false gate structure and forming cavities at two sides of a sacrificial layer, and then forming a first part covering the side wall of the false gate structure and a second part filling the cavities and covering the side wall of a stack structure, the first part exposes at least part of the surface, facing the dummy gate structure, of the target channel layer, so that a step structure of which the second part protrudes towards two sides is formed on one side, facing the dummy gate structure, of the first channel layer; and finally, when the inner side wall is formed, anisotropic etching can be performed on the first dielectric layer and the stacked structure by taking the first part as a self-alignment structure so as to form the inner side wall and the outer side wall, and the first part is taken as the self-alignment structure, so that transverse undercutting of the inner side wall is avoided, and the over-etching problem of the inner side wall is improved.

Description

Technical Field

[0001] This specification relates to the field of semiconductor technology, specifically to gate-around field-effect transistor technology in the field of semiconductor technology, and more specifically, to a method for fabricating an inner sidewall and a method for fabricating a semiconductor device. Background Technology

[0002] With advancements in integrated circuit technology, transistor sizes are continuously shrinking to meet the demands for higher density, lower power consumption, and higher performance. However, traditional planar transistor structures (such as planar MOSFETs) have encountered physical limits and technical challenges after their size has shrunk to a certain extent, including short-channel effects and leakage current. While the emergence of FinFET (Fin Field-Effect Transistor) has largely solved these problems, as transistor sizes shrink further to 3 nanometers and below, FinFET also faces issues such as mobility degradation, decreased gate control capability, and increased leakage current and power consumption. GAAFET (Gate-All-Around Field Effect Transistor), due to its excellent gate control capability and good compatibility with FinFET integration schemes, has been considered by academia and industry as a replacement for FinFET at 3nm and below technology nodes.

[0003] With the continuous advancement of technology nodes, many problems have been encountered in the fabrication of advanced semiconductor devices such as GAAFETs. Ensuring the performance of the fabricated semiconductor devices has become one of the key research and development directions for relevant technical personnel. Summary of the Invention

[0004] This specification provides a method for fabricating an inner sidewall and a method for fabricating a semiconductor device, in order to improve the performance of the fabricated semiconductor device.

[0005] To achieve the above technical objectives, the embodiments of this specification provide the following technical solutions:

[0006] One embodiment of this specification provides a method for preparing an inner sidewall, comprising:

[0007] A substrate is provided, the surface of which has a stacked structure and a dummy gate structure and dummy sidewalls located on the side of the stacked structure opposite to the substrate, the dummy sidewalls being located on both sides of the dummy gate structure, the stacked structure comprising alternately stacked sacrificial layers and channel layers;

[0008] The sacrificial layer is etched to form a cavity, and the false sidewalls are removed.

[0009] A first dielectric layer is formed, the first dielectric layer including a first portion and a second portion, the first portion covering the sidewall of the dummy gate structure, the second portion filling the cavity and covering the sidewall of the stacked structure, the first portion exposing at least a portion of the surface of the first channel layer facing the dummy gate structure, the first channel layer being a channel layer close to the dummy gate structure;

[0010] Using the first part as a self-aligned structure, anisotropic etching is performed on the first dielectric layer and the stacked structure. The remaining first part after etching serves as the outer wall, and the remaining second part after etching serves as the inner wall.

[0011] Secondly, one embodiment of this specification also provides a computing device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method for fabricating the inner wall or the method for fabricating a semiconductor device as described above.

[0012] Thirdly, one embodiment of this specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method for preparing the inner wall or the method for preparing the semiconductor device as described above.

[0013] Fourthly, embodiments of this specification provide a computer program product or a computer program, the computer program product including a computer program stored in a computer-readable storage medium; the processor of the computer device reads the computer program from the computer-readable storage medium, and when the processor executes the computer program, it implements the steps of the above-described method for preparing the inner wall or the method for preparing the semiconductor device.

[0014] As can be seen from the above technical solution, the method for preparing the inner sidewall provided in this specification, before forming the first dielectric layer, firstly removes the false sidewalls on both sides of the false gate structure and forms cavities on both sides of the sacrificial layer, then forms a first part including a first part covering the sidewalls of the false gate structure and a second part filling the cavities and covering the sidewalls of the stacked structure. The first part exposes at least a portion of the surface of the target channel layer facing the false gate structure. Thus, on the side of the first channel layer (i.e., the channel layer near the false gate structure) facing the false gate structure, a stepped structure protruding to both sides of the second part is formed. Finally, when forming the inner sidewall, the first part can be used as the first part. A portion of the first part, acting as a self-aligned structure, performs anisotropic etching on the first dielectric layer and the stacked structure to form inner and outer sidewalls. Because the first part serves as a self-aligned structure, lateral drilling of the inner sidewalls is avoided, mitigating the over-etching problem. Simultaneously, the first part exposes at least the surface of the target channel layer. Anisotropic etching using the first part as a self-aligned structure avoids the under-etching problem where the channel layer in the stacked structure cannot be exposed during the etching process. This improves the morphology of the inner sidewalls and related structures formed during etching, thereby improving the performance of the formed semiconductor device. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this specification. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the fabrication process of GAAFET in related technologies;

[0017] Figure 2 This is a schematic diagram illustrating the over-etching of the inner sidewall during the fabrication process of GAAFET in related technologies.

[0018] Figure 3 This diagram illustrates the relationship between the material proportion distribution in the transition layer and the etching rate.

[0019] Figure 4 For H in FinFET and NSFET rcs A schematic diagram showing the relationship between leakage current;

[0020] Figure 5 A schematic flowchart illustrating a preparation method provided for embodiments of this specification;

[0021] Figures 6-9 A schematic flowchart illustrating a preparation method provided for embodiments of this specification;

[0022] Figure 10 A schematic diagram illustrating the preparation process of a protective layer provided for embodiments of this specification;

[0023] Figure 11 A schematic diagram illustrating the process of removing a false sidewall provided for embodiments of this specification;

[0024] Figure 12 A schematic diagram of a feasible fabrication process for a semiconductor device provided for embodiments of this specification;

[0025] Figure 13 This is a schematic diagram of the structure of a computing device provided for the implementation of this specification. Detailed Implementation

[0026] Unless otherwise defined, the technical or scientific terms used in the embodiments of this specification shall have the ordinary meaning understood by one of ordinary skill in the art to which this specification pertains. The terms "first," "second," and similar terms used in the embodiments of this specification do not indicate any order, quantity, or importance, but are merely used to avoid confusion of constituent elements.

[0027] Unless the context otherwise requires, throughout this specification, "a plurality of" means "at least two," and "including" is interpreted as open-ended or encompassing, that is, "including, but not limited to." In the description of this specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this specification. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example.

[0028] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0029] Overview

[0030] In the fabrication of semiconductor devices, obtaining a structure that meets expectations and has a good morphology is a necessary condition for ensuring the normal performance and function of the device. Taking GAAFET as an example, since the process node of GAAFET can be below 3nm, this places higher demands on the fabrication process. Figure 1 , Figure 1 This diagram illustrates the fabrication process of GAAFET in related technologies:

[0031] Figure 1 In step 1), a channel / sacrificial layer stacked thin film is deposited on the surface of a substrate (which may be a silicon (Si) substrate) to form a stacked structure. In some embodiments, the channel layer may be a silicon (Si) layer and the sacrificial layer may be a silicon-germanium (SiGe) layer. In other embodiments, the channel layer may be a silicon-germanium layer and the sacrificial layer may be a silicon layer. A Pad Ox layer may be formed on top of the stacked structure to protect and isolate the stacked structure.

[0032] Figure 1 In step 2), deep trench isolation is formed by patterning, and dielectric filling and etch-back are performed to form a dielectric isolation layer. The filling dielectric can be a low-temperature insulating dielectric deposition film such as silicon oxide.

[0033] Figure 1 In step 3), the dummy gate and hard mask layers are deposited to prepare the dummy gate and hard mask layers. The dummy gate can be a polysilicon structure, and the hard mask layer can be a silicon nitride layer. Figure 1 The above figure in step 3) is a cross-sectional view of the BB direction in the corresponding top view;

[0034] Figure 1 In step 4), the dummy gate layer is etched using a patterning method to ensure that the dummy gate layer meets the design width requirements. The width of the dummy gate layer can be determined according to different technology nodes and circuit design rules. Figure 1 The figure above (step 4) is a cross-sectional view along the AA direction in the top view.

[0035] Figure 1 In step 5), the outer wall dielectric layer is deposited, forming a high-retention form (or high-retention property) outer wall (second dielectric layer) through atomic layer deposition or other methods. The materials forming the outer wall include, but are not limited to, one or more of silicon nitride, silicon oxide, silicon carbon nitride, silicon carbon oxynitride, silicon carbon oxide, and silicon oxynitride stacked together. The purpose of the outer wall in GAAFET is to protect the dummy gate and the gate structure that will replace the dummy gate later.

[0036] Figure 1 In step 6), the outer wall and silicon fins are etched. Figure 1 The figure above in step 6) is a cross-sectional view along the AA direction corresponding to the top view; in this step, the outer wall and silicon fins can be formed by dry etching, while consuming part or all of the hard mask layer.

[0037] Figure 1 In step 7), cavity etching is performed by dry etching to form cavities on both sides of the sacrificial layer. These cavities are used to accommodate the inner sidewalls that are formed subsequently. Figure 1The diagram above (step 7) is a cross-sectional view along the AA direction corresponding to the top view;

[0038] Figure 1 In step 8), the inner wall dielectric layer is filled by forming a high-conformity inner wall film (third dielectric layer) through atomic layer deposition or other methods. The material forming the inner wall in this step can be the same as the material forming the outer wall. Figure 1 The diagram above (step 8) is a cross-sectional view along the AA direction of the top view.

[0039] Figure 1 In step 9), the inner wall dielectric layer is etched back: using etching processes such as dry etching, the inner wall dielectric layer is etched back to preserve the inner wall located in the cavity, while exposing both ends of the channel layer for subsequent source and drain epitaxy. Figure 1 The diagram above (step 9) is a cross-sectional view along the AA direction of the top view.

[0040] Figure 1 In step 10), source / drain region epitaxy: source / drain epitaxy is performed on both sides of the exposed channel layer to form source / drain electrodes. Figure 1 The figure above (step 10) is a cross-sectional view along the AA direction corresponding to the top view.

[0041] After the source and drain are formed, processes such as removing the dummy gate and filling the high-dielectric-constant metal gate are performed to complete the fabrication of the entire semiconductor device.

[0042] In the above-mentioned fabrication process, due to the small size of the cavity, when the inner sidewall dielectric layer is etched back in step 9), the problem of insufficient etching or over-etching is likely to occur. When the inner sidewall dielectric layer is not etched enough, the two ends of the channel layer cannot be exposed, which causes the source and drain formed later to be unable to make normal contact with the channel layer, resulting in abnormal function of the entire device. When the inner sidewall dielectric layer is over-etched, leakage current is easily generated due to the reduction of the inner sidewall thickness, which has an adverse effect on the device performance.

[0043] For example, in related technologies, reference Figure 2 , Figure 2 In step 1), after filling the inner wall dielectric layer, anisotropic etching is used to remove the top and bottom inner wall dielectric layers (third dielectric layer), such as... Figure 2 As shown in step 2), the third dielectric layer on the side is then etched using isotropic etching, as shown in step 2). Figure 2As shown in step 3), when the etching progress approaches the channel layer, two interfaces are formed: silicon and the third dielectric layer. Simultaneously, the etching gas exhibits a high selectivity for both the third dielectric layer and silicon to ensure the channel layer is not etched. However, due to the presence of an intermediate transition layer at the contact point between silicon and the third dielectric layer, the etching rate significantly decreases as the etching progress approaches silicon, while the etching rate at the inner wall position remains unchanged (see reference). Figure 3 , Figure 3 This diagram illustrates the relationship between the material proportion distribution in the transition layer and the etching rate. The horizontal axis represents the elemental content of silicon and the third dielectric layer. Figure 3 The above figure shows that from left to right, the element content of the third dielectric layer gradually decreases from 100% to 0%, and from right to left, the silicon element content gradually increases from 0% to 100%. Figure 3 The diagram below shows that as the silicon content increases, the etching rate gradually decreases, eventually leading to larger over-etching of the inner wall, resulting in... Figure 2 In the middle, step 4) and Figure 2 In step 5), the bowl-shaped structure is prone to leakage due to the reduced thickness of the inner wall, which affects the performance of the device.

[0044] To address the issue of over-etching of the inner sidewalls, a selective growth method for the inner sidewalls has been proposed. This method involves selectively growing a dielectric material based on a sacrificial layer after the cavity is formed to create the inner sidewalls, thus filling the cavity and completing the sidewall fabrication. This eliminates the need for an etching process, avoiding potential over-etching or under-etching issues that can occur during the inner sidewall etching process. However, research has shown that the selective growth method for inner sidewalls makes it difficult to control the film thickness of the grown inner sidewalls. Furthermore, due to the height difference in the sacrificial layer, inconsistent thicknesses of the inner sidewalls across different layers can easily occur, negatively impacting device performance. In addition, lateral selective growth of thin films places high demands on equipment performance, resulting in higher production costs.

[0045] To address the issues of over-etching or under-etching that easily occur during the etching of inner walls in related technologies at a low cost, the inventors have proposed a method for fabricating semiconductor structures based on a self-aligned structure. This method involves forming the first dielectric layer (distinct from...). Figures 1-3In accordance with relevant technologies, before the first dielectric layer mentioned in the embodiments of this specification is used to form the final outer and inner sidewalls, the false sidewalls on both sides of the false gate structure are first removed and cavities are formed on both sides of the sacrificial layer. Then, a first portion covering the sidewalls of the false gate structure and a second portion filling the cavities and covering the sidewalls of the stacked structure are formed. The first portion exposes at least a portion of the surface of the target channel layer facing the false gate structure. Thus, on the side of the first channel layer (i.e., the channel layer near the false gate structure) facing the false gate structure, a stepped structure protruding to both sides of the second portion is formed. Finally, when forming the inner sidewall, the first dielectric layer can be used as the first dielectric layer. A portion of the first part, acting as a self-aligned structure, performs anisotropic etching on the first dielectric layer and the stacked structure to form inner and outer sidewalls. Because the first part serves as a self-aligned structure, lateral drilling of the inner sidewalls is avoided, mitigating the over-etching problem. Simultaneously, the first part exposes at least the surface of the target channel layer. Anisotropic etching using the first part as a self-aligned structure avoids the under-etching problem where the channel layer in the stacked structure cannot be exposed during the etching process. This improves the morphology of the inner sidewalls and related structures formed during etching, thereby improving the performance of the formed semiconductor device.

[0046] Furthermore, further research revealed that etching the first dielectric layer may damage the substrate, and the greater the substrate damage, the greater the leakage current of the device. (See relevant documentation for details.) Figure 4 , Figure 4 This illustrates the H in FinFET and NSFET (Nanowire Semiconductor Field-Effect Transistor, a type of GAAFET). rcs A schematic diagram showing the relationship between H and leakage current, where H rcs Characterizes the depth of damage to the substrate caused during the etching process. Figure 4 (a) and (b) show H under the condition that Vds = 0.7V (drain-source voltage = 0.7V), respectively. rcs A schematic diagram of the Id-Vg (drain current-gate voltage) curves in FinFET and NSFET as the wavelength varies from 0nm to 18nm. Figure 4 (c) and (d) are respectively in H rcs Contour plot of leakage current density distribution at 18nm and schematic diagram of leakage current density variation along fin height. From Figure 4 It can be observed that the greater the damage to the substrate during the etching process, the greater the leakage current of the device, and the greater the loss to the device performance.

[0047] To avoid this problem, the preparation method provided in this specification forms a protective layer covering a target area of ​​the substrate after forming the first dielectric layer and before etching the first dielectric layer; the target area includes the area on the substrate not covered by the stacked structure. Thus, when etching the first dielectric layer and the stacked structure, the protective layer can protect the substrate from etching damage and avoid leakage current problems caused by etching damage.

[0048] Based on the above concept, this specification provides a preparation method, which will be described exemplarily below with reference to the accompanying drawings.

[0049] Exemplary methods

[0050] This specification provides a method for preparing an inner sidewall, such as... Figure 5 As shown, it includes:

[0051] S501: A substrate 10 is provided, the surface of which has a stacked structure 20 and a dummy gate structure 31 and a dummy sidewall 32 located on the side of the stacked structure 20 away from the substrate 10, the dummy sidewall 32 being located on both sides of the dummy gate structure 31, the stacked structure 20 including alternately stacked sacrificial layers 22 and channel layers 21.

[0052] refer to Figure 6 , Figure 6 The substrate 10 and its surface structure are shown. Unlike fabrication methods in related technologies, the false sidewalls 32 formed in this step need to be etched away in subsequent fabrication processes to prepare for the formation of a self-aligned structure. In some embodiments, to ensure that the first portion 41 of the first dielectric layer 40 formed in subsequent steps is a self-aligned structure, the two ends of the channel layer 21 are sufficiently exposed during etching of the first dielectric layer 40 and the stacked structure 20. The width L1 of the false sidewalls 32 is greater than the width of the subsequently formed outer sidewalls 411, as detailed in subsequent embodiments.

[0053] It is understood that there is also an oxide layer (Pad Ox) between the dummy gate structure 31 and the stacked structure 20. The purpose of this oxide layer can be found in the relevant introduction above, and will not be repeated here.

[0054] S502: Etch the sacrificial layer 22 to form a cavity 23 and remove the false sidewall 32;

[0055] Figure 7The feasible process of step S502 is shown. The sacrificial layer 22 can be etched first to form cavities 23 on both sides of the sacrificial layer 22. The cavities 23 are used to accommodate the inner sidewalls 412 that are subsequently formed. Then the false sidewalls 32 are removed to reserve space for the formation of the first dielectric layer 40.

[0056] S503: Form a first dielectric layer 40, the first dielectric layer 40 including a first portion 41 and a second portion 42, the first portion 41 covering the sidewall of the dummy gate structure 31, the second portion 42 filling the cavity 23 and covering the sidewall of the stacked structure 20, the first portion 41 exposing at least a portion of the surface of the first channel layer 21 facing the dummy gate structure 31, the first channel layer 21 being the channel layer 21 close to the dummy gate structure 31;

[0057] refer to Figure 8 , Figure 8 The diagram shows a cross-sectional structure after step S503. In this embodiment, the purpose of exposing at least a portion of the surface of the first channel layer 21 facing the dummy gate structure 31 in the first part 41 is to ensure that both ends of the channel layer 21 are exposed when etching is performed with the first part 41 as a self-aligned structure, thus avoiding the problem of insufficient etching.

[0058] S504: Using the first portion 41 as a self-aligned structure, anisotropic etching is performed on the first dielectric layer 40 and the stacked structure 20. The remaining first portion 41 after etching serves as the outer sidewall 411, and the remaining second portion 42 after etching serves as the inner sidewall 412.

[0059] refer to Figure 9 , Figure 9 The diagram shows a cross-sectional structure after step S504. During anisotropic etching, the etching rate in one direction (e.g., the vertical direction) can be much greater than the etching rate in another direction (e.g., the horizontal direction). Using the first part 41 as a self-aligned structure, precise etching can be performed on the second part 42 and the portions of the stacked structure 20 exposed outside the first part 41, effectively avoiding over-etching of the inner wall 412 filled in the cavity 23 (e.g., ...). Figure 9 As shown in the enlarged schematic diagram within the dashed box, the self-alignment effect of the outer sidewall of the first part 41 reduces the risk of over-etching the inner sidewall 412. Furthermore, since the first part 41 exposes at least a portion of the surface of the first channel layer 21 facing the dummy gate structure 31, i.e., the two ends of the channel layer 21 in the stacked structure 20 protrude from the first part 41, it is beneficial to ensure that the two ends of the channel layer 21 can be fully exposed after the etching process. Moreover, since the first part 41 can serve as a self-aligned structure, no additional mask is required, which simplifies the etching steps.

[0060] In summary, the preparation method provided in this specification, before forming the first dielectric layer 40, firstly removes the dummy sidewalls 32 on both sides of the dummy gate structure 31 and forms cavities 23 on both sides of the sacrificial layer 22. Then, it forms a first portion 41 covering the sidewalls of the dummy gate structure 31 and a second portion 42 filling the cavities 23 and covering the sidewalls of the stacked structure 20. The first portion 41 exposes at least a portion of the surface of the target channel layer 21 facing the dummy gate structure 31. Thus, on the side of the first channel layer 21 (i.e., the channel layer 21 near the dummy gate structure 31) facing the dummy gate structure 31, a stepped structure protruding to both sides of the second portion 42 is formed. Finally, when forming the inner sidewall 412, the first portion 42 can be used as a step structure. The first portion 41 is used as a self-aligned structure to perform anisotropic etching on the first dielectric layer 40 and the stacked structure 20 to form inner sidewalls 412 and outer sidewalls 411. Since the first portion 41 serves as a self-aligned structure, lateral drilling of the inner sidewall 412 is avoided, thus improving the over-etching problem of the inner sidewall 412. At the same time, the first portion 41 exposes at least the surface of the target channel layer 21. Anisotropic etching with the first portion 41 as a self-aligned structure can avoid the under-etching problem where the channel layer 21 in the stacked structure 20 cannot be exposed during the etching process. This is beneficial to improving the morphology of the inner sidewalls 412 and related structures formed during the etching process, thereby improving the performance of the formed semiconductor device.

[0061] Further research revealed that if directly targeting Figure 7 Anisotropic etching of the structure shown may damage the substrate 10, leading to increased leakage current in the final device. For details, please refer to the preceding description. To address this issue, in one embodiment of this specification, after the formation of the first dielectric layer 40 and before performing anisotropic etching on the first dielectric layer 40 and the stacked structure 20 using the first portion 41 as a self-aligned structure, the method further includes:

[0062] A protective layer 51 is formed to cover a target area of ​​the substrate 10; the target area includes the area on the substrate not covered by the stacked structure 20.

[0063] After anisotropic etching of the first dielectric layer 40 and the stacked structure 20 using the first portion 41 as a self-aligned structure, the method further includes:

[0064] Remove the protective layer 51.

[0065] refer to Figure 10Between steps S503 and S504, a step of forming a protective layer 51 is added. The protective layer 51 formed may be made of a different material than the first dielectric layer 40. In step S504, during the anisotropic etching process, the etching rate of the first dielectric layer 40 may be higher and the etching rate of the protective layer 51 may be lower by selecting etching gas or other methods, so that the protective layer 51 can better protect the substrate 10.

[0066] In an optional implementation, a method for forming a protective layer 51 is provided, specifically, forming the protective layer 51 covering a target area of ​​the substrate 10 includes:

[0067] A second dielectric layer 50 is formed covering the substrate 10, the first dielectric layer 40 and the dummy gate structure 31, wherein the second dielectric layer 50 and the first dielectric layer 40 are dielectric layers of different materials;

[0068] The second dielectric layer 50 is etched to form the protective layer 51 covering the target area of ​​the substrate 10.

[0069] The second dielectric layer 50 can be formed using processes such as spin coating, and then cured by baking. Since spin coating materials are typically liquid and have good fluidity, they can effectively cover the entire device. The main component of the second dielectric layer 50 can include carbon-based materials, and the top surface of the second dielectric layer 50 only needs to be 100 nm to 500 nm above the top surface of the dummy gate structure 31.

[0070] To avoid adverse effects on the stacked structure 20 when removing the false sidewall 32, in one embodiment of this specification, removing the false sidewall 32 includes:

[0071] A third dielectric layer 60 is formed covering the substrate 10, the dummy sidewalls 32, the dummy gate structure 31, and the sidewalls of the stacked structure 20;

[0072] The third dielectric layer 60 is etched to form a stacked protective structure 61 and expose the false sidewall 32; the stacked protective structure 61 covers the sidewall of the stacked structure 20;

[0073] The false sidewall 32 was removed by etching;

[0074] The stacked protective structure 61 is removed by etching.

[0075] In this embodiment, the process of removing the false sidewall 32 can be referred to Figure 11The resulting stacked protection structure 61 can protect the stacked structure 20 during the etching process of removing the false sidewalls 32, avoiding adverse effects on the sidewalls of the stacked structure 20 during the etching process of removing the false sidewalls 32, and ensuring the performance of the final device.

[0076] In order to enable the stacked protection structure 61 to provide good protection for the stacked structure 20, in one embodiment of this specification, the first distance is 0 nm to 50 nm larger than the second distance. The first distance includes the distance between the stacked protection structure 61 and the substrate 10, and the second distance includes the distance between the first channel layer 21 and the substrate 10. The first channel layer 21 is the channel layer 21 close to the dummy gate structure 31.

[0077] In this embodiment, the stacked protective structure 61 extends above the first channel layer 21 by a distance of 0 nm to 50 nm, thereby preventing the stacked structure 20 from being exposed during the removal of the false sidewalls 32 and effectively protecting the stacked structure 20.

[0078] As mentioned above, in order to ensure that there is no problem of insufficient etching during the etching process of the inner sidewall 412, in one embodiment, the width of the false sidewall 32 in the first direction is greater than the width of the outer sidewall 411 in the first direction.

[0079] The first direction is parallel to the surface of the substrate 10.

[0080] Reference Figure 6 and Figure 9 L1 > L2, where L2 is the required width of the outer wall 32 and the required width of the dummy grid structure 31 is also fixed. At the same time, the edges of the channel layer 21 and the outer wall 32 are required to be flush. Therefore, in order to reserve space and avoid the space left after etching the stacked structure from not being able to form an outer wall 32 with a width of L2, L1 is required to be greater than L2.

[0081] More specifically, in one embodiment, the width of the outer wall 411 in the first direction ranges from 10 nm to 50 nm.

[0082] The width of the false sidewall 32 in the first direction is 2nm to 5nm larger than the width of the outer sidewall 411 in the first direction.

[0083] In this embodiment, 10nm≤L2≤50nm, 2nm≤L1-L2≤5nm. Through experiments, it was found that when the values ​​of L1 and L2 are within the above range, the first dielectric layer 40 with a stepped structure can be formed well, which meets the self-alignment requirements of the subsequent inner wall 412 etching.

[0084] When etching the stacked structure 20, the etching stop position can be controlled to avoid adverse effects on the substrate 10. Specifically, the anisotropic etching of the first dielectric layer 40 and the stacked structure 20 using the first portion 41 as a self-aligned structure includes:

[0085] Using the first part 41 as a self-aligned structure, anisotropic etching is performed on the first dielectric layer 40 and the stacked structure 20. The distance between the etching stop position and the substrate 10 ranges from 0.3h to 1h, where h is the thickness of the sacrificial layer 22.

[0086] Typically, when etching the first dielectric layer 40, a portion of the first dielectric layer 40 can be retained at the bottom of the substrate 10. This serves two purposes: firstly, the retained portion of the first dielectric layer 40 protects the substrate 10 from damage; secondly, it effectively increases the spacing between the source and drain regions on the substrate, effectively reducing bottom subfin channel leakage and improving overall device performance. Since the minimum thickness of the sacrificial layer 22 is less than 10 nm (0.3h ≤ 3 nm), if the etching stop position is less than 0.3h, the etching process is difficult to control and can easily damage the substrate 10. Conversely, if the thickness of the retained first dielectric layer 40 (i.e., until etching stops) is greater than 1h, it will affect the current conduction of the channel layer 21 adjacent to the bottommost sacrificial layer 22, adversely affecting the electrical performance of the device. Therefore, setting the distance between the etching stop position and the substrate 10 to a range of 0.3h to 1h effectively increases the spacing between the source and drain regions on the substrate 10, effectively reducing bottom subfin channel leakage and improving overall device performance.

[0087] To ensure that the formed first dielectric layer 40 has a good morphology, and to avoid the oxide layer from adversely affecting device performance, in one embodiment of this specification, before forming the first dielectric layer 40, the following steps are also included:

[0088] The substrate 10, stacked structure 20, dummy gate structure 31 and dummy sidewall 32 are subjected to reduction treatment to remove the oxide layer.

[0089] In one specific embodiment of this specification, a feasible method for fabricating a semiconductor device is provided, such as... Figure 12 As shown, Figure 12 A schematic diagram of a feasible fabrication process for a semiconductor device is shown, where A to M represent cross-sectional structural diagrams of the device after different etching steps; the fabrication method specifically includes:

[0090] A. A stacked structure 20, a dummy sidewall 32, and a dummy gate structure 31 are formed on the surface of the substrate 10. The thickness of the dummy sidewall 32 is 2nm to 5nm thicker than the thickness of the subsequently formed outer sidewall 411, which is used to reserve thickness for the two ends of the channel layer 21 to be exposed during subsequent anisotropic etching. The material used for the dummy sidewall 32 may include SiN. X (Silicon nitride), SiOCH (silicon, oxygen, carbon, hydrogen) and SiO N (Silicon oxide) or a combination of one or more materials.

[0091] B. Etching to form cavity 23: This step can use anisotropic etching in dry etching to remove part of the material at both ends of the sacrificial layer 22 to form the cavity 23 structure. This cavity 23 structure is used to deposit the inner sidewall 412 material. The formed inner sidewall 412 serves two purposes: protection and support, and isolation between the subsequent metal material replacing the sacrificial layer 22 and the source / drain electrodes 72, preventing short circuits between the metal material and the source / drain electrodes 72. The etching gases used in the cavity 23 etching step include, but are not limited to, fluorocarbons, fluoronitrogen compounds, and hydrogen fluoride. Typically, one or more of these gases are combined with argon (ignition gas) or hydrogen (catalytic gas) to complete the cavity 23 etching step. The etching depth of cavity 23 is not much different from the width L1 of the false sidewall 32, and the depth of cavity 23 is generally L1 ± 2 nm.

[0092] C. Spin-coating the third dielectric layer 60 to cover the entire device. This process can be completed using a spin coater. After spin coating, the third dielectric layer 60 fills the entire device, and then it is baked and cured. The main component of the third dielectric layer 60 is carbon-based material. The thickness of the third dielectric layer 60 should exceed the upper surface of the device (the upper surface of the dummy gate structure 31) by 100nm to 500nm.

[0093] D. The third dielectric layer 60 is etched back. The etching time is strictly controlled by dry etching. The etch is performed until it is flush with the first trench layer 21 to obtain the stacked protection structure 61. The purpose of the stacked protection structure 61 is to protect the stacked structure 20 and the substrate 10 from being affected when removing the false sidewalls 32, and to prepare for ensuring that the outer sidewalls 411 and inner sidewalls 412 have the same thickness. The etching gas used in this process can include a combination of oxygen-containing gases, such as argon + oxygen, for example: O2 at 100-500 sccm (standard cubic centimeters per minute), Ar at 10-50 sccm, pressure at 10-100 mtorr (millitorr), power at 200-800 W, and time at 3-15 s, etc.

[0094] E. Isotropic etching is used to remove false sidewalls 32. Carbon-fluorine or nitrogen-fluorine ...

[0095] F. Removal of stacked protective structure 61. The etching gas used in this process is mainly a combination of oxygen-containing gases, such as argon + oxygen, for example: O2 at 100-500 sccm, Ar at 10-50 sccm, pressure at 10-100 mtorr, power at 200-800 W, time at 3-50 s, etc.

[0096] G. Filling the first dielectric layer 40: Before filling, the oxide layer on the device surface can be reduced in a pretreatment chamber. The treatment gas can include a hydrogen-helium mixture + argon, and typically a 5% H2 / He mixture can be used to align the surface for reduction. Then, plasma-enhanced atomic layer deposition (PEALD) is used to prepare the inner sidewall 412 dielectric layer. Its thickness needs to be greater than 1 / 2 the thickness of the sacrificial layer 22, for example, 2-50 nm, to ensure that the side cavity 23 can be completely filled. It also needs to meet the thickness requirements of the outer sidewall 411, for example, 10 nm-50 nm, which is the actual required sidewall thickness for this semiconductor device. Due to the different structures of the dummy gate layer and the channel layer 21, a natural step structure is formed at the location of the first channel layer 21 when the first dielectric layer 40 is deposited. That is, the width of the dummy gate structure 31 is smaller than the width of the channel layer 21, or the width L1 of the first dielectric layer 40 covering the sidewall of the dummy gate structure 31 is smaller than the width L2 of the first dielectric layer 40 covering the first channel layer 21, thus forming a step shape, which prepares for subsequent self-aligned etching. This step can employ atomic layer deposition (ALD) to deposit the first dielectric layer 40. Deposition conditions can include a pressure of 10-30 torr, a temperature of 300-500℃, a power of 200-800W, an Ar flow rate of 300-3000 sccm, and an NH3 (or N2+H2 combination, etc.) flow rate of 500-5000 sccm. The silicon reaction source is introduced into the chamber via Ar transport at a flow rate of 100-2000 sccm. A typical deposition cycle consists of: 1) introducing NH3 (or N2+H2 combination, etc.) for 1-5 seconds; 2) purging the nitrogen-containing reaction source for 0.5-2 seconds; 3) introducing the silicon reaction source for 0.3-2 seconds; and 4) purging the silicon-containing reaction source for 1-5 seconds. The number of cycles required to deposit a specific thickness is calculated based on the deposition rate. In this embodiment, the number of cycles is between 200-500.

[0097] H. The top and bottom of the first dielectric layer 40 are removed by anisotropic etching so that the substrate 10 material at the bottom of the device is exposed, providing an interface for the subsequent epitaxial source and drain 72, while forming the first part 41 and the second part 42 of the first dielectric layer 40.

[0098] 1. Spin-coat the second dielectric layer 50. The second dielectric layer 50 can be made of the same material as the third dielectric layer 60. The process of spin-coating the second dielectric layer 50 can be referred to the formation process of the third dielectric layer 60 in the previous text.

[0099] J. Etching back of the second dielectric layer 50: The etching time is strictly controlled by dry etching. The etch back height can be flush with the height of the bottom sacrificial layer 22. After etching back, a protective layer 51 is formed. The purpose of the protective layer 51 is to protect the substrate 10 in subsequent etching steps. The etching gases used in this process are mainly oxygen-containing gas combinations, such as argon + oxygen, for example: O2 at 100-500 sccm, Ar at 10-50 sccm, and pressure at 10-100 mtorr, etc.

[0100] K. The final outer sidewall 411, inner sidewall 412, and stacked structure 20 are formed by anisotropic etching. This step mainly adopts a dry vertical-down fabrication method, requiring an etching morphology angle between 88° and 90° to ensure that the thickness of the inner sidewall 412 is roughly consistent between each stack, while fully exposing both ends of the channel layer 21. Simultaneously, the etching time needs to be strictly controlled to retain a portion of the first dielectric layer 40 at the bottom of the device, generally with a thickness between 0.3 and 1 times the thickness of the sacrificial layer 22. Typically, the minimum thickness of the sacrificial layer 22 is below 10 nm; 0.3 times is ≤3 nm. If the thickness is further reduced, the etching process becomes difficult to control; if it is >1 times, it will affect the current conduction of the adjacent channel layer 21 of the sacrificial layer 22, affecting the device's electrical performance. Therefore, retaining a thickness between 0.3 and 1 times the thickness of the sacrificial layer 22 can effectively increase the spacing between the source and drain regions on the substrate 10, effectively reducing leakage current in the bottom subfin channel and improving the overall performance of the device. In addition, using the steps formed in step H as a self-aligned structure, the material is etched downwards in the vertical direction to remove the protruding portion of the trench layer 21 / sacrificial layer 22, thus forming the final inner wall 412 structure, achieving a width that is consistent with the outer wall 411. Figure 12 The K-figure in the figure shows the final etching morphology of the inner sidewall 412. This method completely avoids problems such as over-etching or under-etching of the inner sidewall 412 dielectric layer.

[0101] L. Removing the protective layer 51. The etching gases used in this process are mainly oxygen-containing gas combinations, such as argon + oxygen, for example: O2 at 100-500 sccm, Ar at 10-50 sccm, and pressure at 10-100 mtorr. By protecting the substrate 10 with the protective layer 51 and controlling the etching time, damage to the substrate 10 during the etching process can be avoided, and leakage current in the subfin channel can be reduced.

[0102] M. Epitaxy of source 71 and drain 72 is performed on the sidewalls of the exposed stacked structure 20. Before epitaxy, the device surface can be pretreated in a pretreatment chamber. The main gas is a mixture of ammonia, nitrogen trifluoride, and argon. The purpose is to remove the oxide layer formed on the exposed semiconductor device due to contact with air or oxygen source, so as to better perform epitaxy of source 71 / drain 72.

[0103] After forming the source 71 and drain 72, processes such as removing the dummy gate structure 31 and filling the high dielectric constant metal gate can be performed to ultimately form a semiconductor device such as a GAAFET.

[0104] Accordingly, this specification also provides a method for fabricating a semiconductor device, comprising:

[0105] An inner sidewall is formed on a substrate according to the method for preparing the inner sidewall according to any of the above embodiments;

[0106] A target electrode is formed on the substrate to form the semiconductor device, the target electrode including a gate, a source, and a drain.

[0107] For a description of the methods for fabricating semiconductor devices, please refer to the relevant descriptions above. This manual will not repeat them here.

[0108] Accordingly, embodiments of this specification also provide a semiconductor device, including:

[0109] Substrate;

[0110] An inner sidewall and a target electrode are located on one side of the substrate. The target electrode includes a gate, a source, and a drain. The inner sidewall is prepared according to the preparation method of the inner sidewall described in any of the above embodiments.

[0111] For other feasible structures of semiconductor devices, such as outer walls and channel layers, please refer to the relevant descriptions above. This specification will not elaborate further here.

[0112] In one alternative implementation, refer to Figure 12 The width of the first inner wall is greater than the width of the other inner walls, and the first inner wall is the inner wall closest to the substrate.

[0113] Exemplary device

[0114] This application also provides a semiconductor process apparatus, including: a process chamber, a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the method for fabricating the inner sidewall or the method for fabricating a semiconductor device as described in any of the above embodiments.

[0115] Another embodiment of this application also proposes a computing device, see [link to relevant documentation] Figure 13 As shown, an exemplary embodiment of this specification also provides a computing device, including: a memory and a processor, the memory storing a computer program, the processor executing the computer program to perform the steps in the methods for preparing an inner wall or a semiconductor device according to various embodiments of this specification described above.

[0116] The internal structure of the computing device can be as follows: Figure 13 As shown, the computing device includes a processor, memory, network interface, and input device connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it follows the steps of the methods for fabricating the inner wall or semiconductor device according to the various embodiments of this specification described above.

[0117] The processor may include the main processor, as well as baseband chips, modems, etc.

[0118] The memory stores a program that executes the technical solution of this invention, and may also store an operating system and other critical business functions. Specifically, the program may include program code, which includes computer operation instructions. More specifically, the memory may include read-only memory (ROM), other types of static storage devices capable of storing static information and instructions, random access memory (RAM), other types of dynamic storage devices capable of storing information and instructions, disk storage, flash memory, etc.

[0119] The processor can be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the program of the present invention. It can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0120] Input devices may include devices that receive data and information input by the user, such as keyboards, mice, cameras, scanners, light pens, voice input devices, touch screens, pedometers, or gravity sensors.

[0121] Output devices may include devices that allow information to be output to the user, such as displays, printers, speakers, etc.

[0122] The communication interface may include any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Network (WLAN), etc.

[0123] The processor executes the program stored in the memory and calls other devices, which can be used to implement any of the steps of the method for preparing an inner wall or a semiconductor device provided in the above embodiments of this application.

[0124] The computing device may also include a display component and a voice component. The display component may be a liquid crystal display screen or an e-ink display screen. The input device of the computing device may be a touch layer covering the display component, or a button, trackball or touchpad set on the casing of the computing device, or an external keyboard, touchpad or mouse, etc.

[0125] Those skilled in the art will understand that Figure 13 The structures shown are merely block diagrams of some structures related to the solutions in this specification and do not constitute a limitation on the computing devices on which the solutions in this specification are applied. Specific computing devices may include more or fewer components than those shown in the figures, or combine certain components, or have different component arrangements.

[0126] Exemplary computer program products and storage media

[0127] In addition to the methods and apparatus described above, the methods for fabricating inner walls or semiconductor devices provided in the embodiments of this specification can also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods for fabricating inner walls or semiconductor devices according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0128] The computer program product described herein can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments described herein. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0129] Furthermore, embodiments of this specification also provide a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor of the steps in the methods for preparing an inner wall or a semiconductor device according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0130] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0131] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The embodiments described above are merely illustrative of several implementation methods outlined in this specification. While the descriptions are specific and detailed, they should not be construed as limiting the scope of the solutions provided in this specification. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the scope of protection of this specification. Therefore, the scope of protection for this patent should be determined by the appended claims.

Claims

1. A method for preparing an inner sidewall, characterized in that, include: A substrate is provided, the surface of which has a stacked structure and a dummy gate structure and dummy sidewalls located on the side of the stacked structure opposite to the substrate, the dummy sidewalls being located on both sides of the dummy gate structure, the stacked structure comprising alternately stacked sacrificial layers and channel layers; The sacrificial layer is etched to form a cavity, and the false sidewalls are removed; A first dielectric layer is formed, the first dielectric layer including a first portion and a second portion, the first portion covering the sidewall of the dummy gate structure, the second portion filling the cavity and covering the sidewall of the stacked structure, the first portion exposing at least a portion of the surface of the first channel layer facing the dummy gate structure, the first channel layer being a channel layer close to the dummy gate structure; Using the first part as a self-aligned structure, anisotropic etching is performed on the first dielectric layer and the stacked structure. The remaining first part after etching serves as the outer wall, and the remaining second part after etching serves as the inner wall.

2. The method according to claim 1, characterized in that, After the formation of the first dielectric layer and before the anisotropic etching of the first dielectric layer and the stacked structure using the first portion as a self-aligned structure, the method further includes: A protective layer is formed to cover a target area of ​​the substrate; the target area includes regions on the substrate not covered by the stacked structure. After anisotropic etching of the first dielectric layer and the stacked structure using the first portion as a self-aligned structure, the method further includes: Remove the protective layer.

3. The method according to claim 2, characterized in that, The protective layer forming the target region covering the substrate includes: A second dielectric layer is formed covering the substrate, the first dielectric layer, and the dummy gate structure, wherein the second dielectric layer and the first dielectric layer are dielectric layers of different materials; The second dielectric layer is etched to form the protective layer covering the target area of ​​the substrate.

4. The method according to claim 2, characterized in that, The thickness of the protective layer ranges from 0.3h to 1h, where h is the thickness of the sacrificial layer.

5. The method according to claim 1, characterized in that, The removal of the false sidewall includes: A third dielectric layer is formed covering the substrate, the dummy sidewalls, the dummy gate structure, and the sidewalls of the stacked structure; The third dielectric layer is etched to form a stacked protective structure and expose the false sidewalls; the stacked protective structure covers the sidewalls of the stacked structure. Etching removes the false sidewalls; The stacked protective structure is removed by etching.

6. The method according to claim 5, characterized in that, The first distance is 0 nm to 50 nm greater than the second distance. The first distance includes the distance between the stacked protective structure and the substrate, and the second distance includes the distance between the first channel layer and the substrate.

7. The method according to any one of claims 1 to 6, characterized in that, The width of the false sidewall in the first direction is greater than the width of the outer sidewall in the first direction; The first direction is parallel to the substrate surface.

8. The method according to claim 7, characterized in that, The width of the outer wall in the first direction ranges from 10nm to 50nm. The width of the false sidewall in the first direction is 2nm to 5nm greater than the width of the outer sidewall in the first direction.

9. The method according to any one of claims 1 to 6, characterized in that, The anisotropic etching of the first dielectric layer and the stacked structure, using the first portion as a self-aligned structure, includes: Using the first part as a self-aligned structure, anisotropic etching is performed on the first dielectric layer and the stacked structure. The distance between the etching stop position and the substrate ranges from 0.3h to 1h, where h is the thickness of the sacrificial layer.

10. The method according to any one of claims 1 to 6, characterized in that, Before forming the first dielectric layer, the method further includes: The substrate, stacked structure, dummy gate structure, and dummy sidewalls are subjected to reduction treatment to remove the oxide layer.

11. A method for fabricating a semiconductor device, characterized in that, include: The method for preparing the inner sidewall according to any one of claims 1 to 10 involves forming an inner sidewall on a substrate; A target electrode is formed on the substrate to form the semiconductor device, the target electrode including a gate, a source, and a drain.

12. A semiconductor device, characterized in that, include: Substrate; An inner sidewall and a target electrode are located on one side of the substrate. The target electrode includes a gate, a source, and a drain. The inner sidewall is prepared by the method of preparing the inner sidewall according to any one of claims 1 to 10.

13. The device according to claim 12, characterized in that, The width of the first inner wall is greater than the width of the other inner walls, and the first inner wall is the inner wall closest to the substrate.

14. A semiconductor process apparatus, characterized in that, include: The process chamber, memory, processor, and computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method for fabricating the inner wall as described in any one of claims 1 to 10 or the method for fabricating the semiconductor device as described in claim 11.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method for preparing the inner wall as described in any one of claims 1 to 10 or the method for preparing the semiconductor device as described in claim 11.

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