Preparation method of grid electrode of pHEMT device and pHEMT device

Abstract

The invention provides a preparation method of a grid electrode of a pHEMT device and the pHEMT device. The method comprises the following steps: providing an epitaxial wafer; coating the surface of the wafer with positive photoresist, and performing soft baking on the wafer coated with the photoresist by using a hot plate; based on a bifocal plane exposure technology, adjusting the focusing depth and the exposure quantity through a focal length energy matrix to carry out secondary exposure; and baking and developing the wafer after the secondary exposure so as to prepare a target gate on the wafer, the line width of the target gate being less than 100 nm. By applying the DFE technology to pHEMT grid photoetching, compared with a traditional single exposure process, the method has a larger process window and can realize better grid morphology; an electron beam photoetching device of a KRF line or an ArF line is used for exposing an irradiation pattern, the grid line width smaller than the limit resolution of a photoetching machine is obtained, and the photoetching technology with the size smaller than 100 nm is achieved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating the gate of a pHEMT device and the pHEMT device itself. Background Technology

[0002] Gallium arsenide pHEMTs (pseudo-hybrid high electron mobility transistors) are widely used in millimeter-wave and microwave communication systems due to their excellent high-frequency characteristics. As operating frequencies continue to increase, the requirements for gate linewidth precision in pHEMT devices also become more stringent.

[0003] Electron beam lithography equipment can achieve higher resolution, but it is inefficient and costly. Mature and lower-cost I-line stepper lithography machines cannot achieve gate lithography processes that meet application requirements. Lithography equipment using KRF or ArF lines with wavelengths of 248nm or 193nm is limited by process technology and cannot achieve linewidths smaller than the process limits. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a method and system for fabricating the gate of a pHEMT device, which aims to solve the technical problem of high fabrication cost of high-resolution gates in the prior art.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a method for fabricating the gate of a pHEMT device, comprising the following steps: S1 provides an epitaxial wafer; S2, apply positive photoresist to the wafer surface and use a hot plate to soft bake the photoresist-coated wafer; S3, the sample after soft baking is exposed once using a KRF line or ArF line photolithography device with a wavelength of 248nm or 193nm; S4, with the wafer stationary, a second exposure is performed based on dual-focal-plane exposure technology by adjusting the focus depth and exposure amount through the focal length energy matrix. The focal position of the first exposure is different from that of the second exposure. S5, the wafer after the second exposure is baked and developed to prepare a target gate on the wafer, the linewidth of the target gate being less than 100 nm.

[0006] According to one aspect of the above technical solution, in step S2, the thickness of the photoresist is 5500Å ~ 6000Å, and the thickness uniformity is ±100Å.

[0007] According to one aspect of the above technical solution, in step S2, the control parameters for soft baking are: baking temperature of 90℃-120℃ and baking time of 60 seconds-90 seconds.

[0008] According to one aspect of the above technical solution, the epitaxial wafer is a gallium arsenide wafer or a gallium nitride wafer.

[0009] According to one aspect of the above technical solution, after the second exposure step, the method further includes: With the wafer stationary, three exposures are performed by adjusting the focus depth and exposure amount using a focal length energy matrix.

[0010] On the other hand, the present invention also provides a pHEMT device, including a gate prepared by the above-described technical solution.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: by applying DFE (Double Focal plane Exposure) technology to pHEMT gate lithography, a larger process window is achieved compared with the traditional single exposure process, and better gate morphology can be achieved; by using KRF line or ArF line electron beam lithography equipment to expose and irradiate the pattern, a gate linewidth smaller than the lithography machine's limit resolution is obtained, realizing a lithography process with a size of less than 100nm. Attached Figure Description

[0012] Figure 1 This is a flowchart of the gate fabrication method of the pHEMT device in the first embodiment of the present invention; The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0013] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0014] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0015] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0016] Example 1 Please see Figure 1 The figure shows a method for fabricating the gate of a pHEMT device according to the first embodiment of the present invention. As shown in the figure, the method includes the following steps: S1, An epitaxial wafer is provided. The wafer is either a gallium arsenide (GaAs) wafer or a gallium nitride (GaN) wafer; in this embodiment, a 6-inch diameter GaAs wafer is used. The wafer material is GaAs, which has excellent high-frequency characteristics and high carrier mobility. The wafer structure is an AlGaAs / InGaAs stacked structure, with InGaAs serving as the quantum well layer and acting as the carrier channel for electron transport. The wafer surface has good flatness and cleanliness. The wafer is fabricated using molecular beam epitaxy (MBE) technology, which allows for precise control of the thickness and doping concentration of each layer.

[0017] S2 involves coating the wafer surface with positive photoresist and then using a hot plate to soft-bake the photoresist-coated wafer. Specifically, an automated spin coater is used to coat the wafer surface with positive photoresist, controlling the photoresist layer thickness to be 5500~6000 Å and the thickness uniformity to ±100 Å. The spin coater employs high-speed rotation technology, which can achieve uniform photoresist coating on the wafer surface. The photoresist material possesses excellent uniformity and adhesion properties.

[0018] A soft bake is performed on the photoresist-coated wafer using a hot plate at 90-120°C for 60-90 seconds. Soft baking evaporates the solvent in the photoresist layer, improving its mechanical strength. It also improves the uniformity of the photoresist layer and increases the adhesion between the photoresist and the wafer. Soft baking is a crucial step to ensure the smooth progress of subsequent photolithography processes.

[0019] S3, using an electron beam lithography device with a wavelength of 248nm or 193nm (KRF or ArF lines) to expose the sample after soft baking once.

[0020] S4. With the wafer stationary, a second exposure is performed using dual-focal-plane exposure technology, adjusting the focus depth and exposure amount via a focal length energy matrix. The focal position of the first exposure differs from that of the second. The second exposure is then performed inside the lithography machine with a different focus position than the first, while the wafer remains stationary. The optimal exposure amount and focus depth for the photoresist are determined based on the results obtained from the FEM (Focus Energy Matrix). The spatial interference effect of the two defocused exposures reconstructs the light intensity distribution gradient, overcoming the optical diffraction limit.

[0021] Preferably, in this embodiment, the number of exposures can be more than two, and the exposure conditions for the two or more exposures can be the same or different.

[0022] S5, the wafer after the second exposure is baked and developed to prepare a target gate with a linewidth of less than 100 nm on the wafer. After exposure, PEB and development are performed according to the normal photolithography process. The target morphology is formed according to the combination of the two exposure conditions (Focus, DOSE).

[0023] In summary, the gate fabrication method for the pHEMT device in the above embodiments of the present invention, by applying DFE (Double Focal Plane Exposure) technology to pHEMT gate photolithography, has a larger process window and can achieve better gate morphology compared to the traditional single exposure process; by using electron beam lithography equipment with KRF lines or ArF lines to expose and irradiate the pattern, a gate linewidth smaller than the limit resolution of the photolithography machine is obtained, realizing a photolithography process with a size of less than 100nm.

[0024] Example 2 A second embodiment of this application also provides a pHEMT device, including the gate obtained in the above embodiments.

[0025] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0026] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method of fabricating a gate for a pHEMT device, characterized by, The method comprises the following steps: S1, providing an epitaxial wafer; S2, coating a positive photoresist on the wafer surface, and soft baking the wafer with the photoresist by using a hot plate; S3, performing first exposure on the soft-baked sample by using an electron beam lithography device with KRF line or ArF line with wavelength of 248nm or 193nm; S4, performing second exposure by adjusting the focusing depth and exposure amount based on a bifocal plane exposure technology through a focal energy matrix without moving the wafer, wherein the focal point position of the first exposure is different from that of the second exposure; S5, baking and developing the wafer after the second exposure to prepare a target gate on the wafer, wherein the line width of the target gate is less than 100nm.

2. The method of claim 1, wherein the pHEMT device is a GaAs device. In step S2, the thickness of the photoresist is 5500Å-6000Å, and the thickness uniformity is ±100Å.

3. The method of claim 1, wherein the pHEMT device is a GaAs device. In step S2, the control parameters of the soft baking are as follows: the baking temperature is 90-120℃, and the baking time is 60-90 seconds.

4. The method of claim 1, wherein the pHEMT device is a GaAs device. The epitaxial wafer is a gallium arsenide wafer or a gallium nitride wafer.

5. The method of claim 1, wherein the pHEMT device is a GaAs device. After the step of performing the second exposure, the method further comprises: performing third exposure by adjusting the focusing depth and exposure amount through a focal energy matrix without moving the wafer.

6. A pHEMT device, characterized by, The gate prepared by the gate preparation method of the pHEMT device according to any one of claims 1-5.

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