Semiconductor device, manufacturing method thereof, power amplifier and electronic equipment

Abstract

The invention provides a semiconductor device, a manufacturing method thereof, a power amplifier and electronic equipment. The semiconductor device comprises a substrate, a plurality of first electrodes arranged along a first direction, a plurality of second electrodes, a plurality of control electrodes, a dielectric layer and a heat dissipation bump, and the heat conductivity of the heat dissipation bump is greater than that of the substrate. The dielectric layer comprises a plurality of dielectric through holes, and the heat dissipation protruding blocks are electrically connected with the first electrode through conductive connecting pieces in the dielectric through holes. In the thickness direction of the substrate, the projection of the dielectric through hole is located in the range of the projection of the first electrode. The plurality of medium through holes in the medium layer comprise a first medium through hole and a second medium through hole, and the cross-sectional area of the first medium through hole is larger than that of the second medium through hole. Wherein the cross-sectional area is the cross-sectional area of the medium through hole in the direction perpendicular to the thickness direction of the substrate. The heat dissipation uniformity of the semiconductor device can be improved, and then the output power and reliability of the semiconductor device are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device, a method for manufacturing the same, a power amplifier, and an electronic device. Background Technology

[0002] Third-generation semiconductor materials (such as GaN) have excellent application prospects in high-temperature, high-frequency, and high-power applications due to their advantages such as large bandwidth, high breakdown field strength, high thermal conductivity, and high electron saturation velocity. GaN-based high electron mobility transistors (HEMTs) are characterized by high breakdown field strength, high saturation drift velocity, low leakage current, and high areal density.

[0003] However, due to the uneven temperature distribution during operation, HEMT devices generate a large amount of heat, leading to phase imbalance between different gates in the HEMT device. This affects the output power of the HEMT device and may also cause reliability issues. Summary of the Invention

[0004] This application provides a semiconductor device, its manufacturing method, a power amplifier, and an electronic device to improve the heat dissipation uniformity of the semiconductor device, thereby enhancing the output power and reliability of the semiconductor device.

[0005] In a first aspect, embodiments of this application provide a semiconductor device, which may include: a substrate, a plurality of first electrodes, a plurality of second electrodes, a plurality of control electrodes, a dielectric layer, and heat dissipation bumps. The thermal conductivity of the heat dissipation bumps is greater than that of the substrate. Each first electrode, each second electrode, and each control electrode is located between the substrate and the dielectric layer, and the heat dissipation bumps are located on the side of the dielectric layer facing away from the substrate. The dielectric layer includes a plurality of dielectric vias, each of which has a conductive connector disposed therein. The heat dissipation bumps are electrically connected to the first electrodes through the conductive connectors; and the heat dissipation bumps are insulated from the second electrodes and control electrodes through the dielectric layer. In the thickness direction of the substrate, the projection of the dielectric vias lies within the projection range of the first electrodes. The plurality of dielectric vias in the dielectric layer may include first dielectric vias and second dielectric vias. The cross-sectional area of ​​the first dielectric vias is greater than the cross-sectional area of ​​the second dielectric vias. The cross-sectional area is the cross-sectional area of ​​the dielectric vias along the direction perpendicular to the thickness of the substrate.

[0006] In the semiconductor device provided in this application embodiment, a heat dissipation bump is provided on the side of the dielectric layer facing away from the substrate, and a dielectric via is provided in the dielectric layer. The heat dissipation bump can be electrically connected to the first electrode through a conductive connector in the dielectric via. Furthermore, the thermal conductivity of the heat dissipation bump is greater than that of the substrate, i.e., the heat dissipation bump has a higher thermal conductivity. Thus, the heat generated by the semiconductor device during operation can be dissipated through the first electrode, the conductive connector in the dielectric via, and the heat dissipation bump. Moreover, the multiple dielectric vias in the dielectric layer can include first dielectric vias and second dielectric vias, with the cross-sectional area of ​​the first dielectric via being larger than that of the second dielectric via. The heat generated by the semiconductor device during operation is dissipated through the first electrode, the conductive connector in the dielectric via, and the heat dissipation bump. The heat dissipation capacity of the semiconductor device is related to the contact area between the first electrode and the conductive connector, i.e., the heat dissipation capacity of the semiconductor device is related to the cross-sectional area of ​​the dielectric via; the larger the cross-sectional area of ​​the dielectric via, the better the heat dissipation effect at that location. The first dielectric via can be placed at a location where heat dissipation of the semiconductor device is relatively concentrated, thereby improving the heat dissipation uniformity of the semiconductor device, and thus improving the output power and reliability of the semiconductor device. Furthermore, the structure of the semiconductor devices in this embodiment has low requirements for processing equipment, is less difficult to manufacture, and has high mass production capability.

[0007] The technical solution of this application embodiment can effectively improve the problem of uneven temperature distribution by changing the cross-sectional area of ​​the medium through-hole at different locations. It is understood that in this application embodiment, the difference between the cross-sectional areas of the first medium through-hole and the second medium through-hole is greater than the error range of the manufacturing process. For example, the difference between the cross-sectional areas of the first medium through-hole and the second medium through-hole can be greater than 5%.

[0008] In one possible implementation, the projection range of the first electrode in the direction perpendicular to the substrate may have projections of one or more dielectric vias, which can be set according to actual conditions. The cross-sectional shape of the dielectric via in the direction parallel to the substrate can be various shapes such as rectangle, circle, ellipse, polygon (≥4 sides, such as octagon), which can be set according to actual needs.

[0009] In one possible implementation, the semiconductor device in this application embodiment may further include an epitaxial layer located between the film layer containing the first electrode and the substrate. Exemplarily, the epitaxial layer may specifically include a channel layer, a barrier layer, or other film layers. The specific structure of the epitaxial layer can be configured according to the type of semiconductor device. Furthermore, the semiconductor device in this application embodiment may also include an insulating layer located between the dielectric layer and the epitaxial layer. The first electrode, the second electrode, and the control electrode can be mutually insulated through the insulating layer. In specific configurations, the positions of each first electrode, each second electrode, and each control electrode can be reasonably set according to actual needs. For example, each first electrode and each second electrode can be arranged alternately along a first direction, and each control electrode can be located between adjacent first and second electrodes. Exemplarily, the semiconductor device in this application embodiment can be a high electron mobility transistor device, where the first electrode can be the source, the second electrode can be the drain, and the control electrode can be the gate. When the semiconductor device in this application embodiment is another type of transistor, the first electrode, the second electrode, and the control electrode can be configured accordingly, which will not be listed here.

[0010] In one possible implementation, the ratio of the thermal conductivity of the heat dissipation bump to the thermal conductivity of the substrate can be greater than 1.05, meaning the heat dissipation bump has high thermal conductivity and good heat dissipation effect. For example, the thermal conductivity of the heat dissipation bump can be greater than 50 W / (m·K). Furthermore, the heat dissipation bump also has good electrical conductivity. It can be electrically connected to the first electrode through a dielectric via, allowing the first electrode to be directly led out, thereby shortening the interconnection distance between the first electrode and other components. In a specific configuration, the heat dissipation bump can include thermally and electrically conductive materials, such as copper, tin, or gold. Additionally, the conductive connector in the dielectric via also has good electrical and thermal conductivity; for example, the conductive connector can include copper, tin, or gold. The conductive connector and the heat dissipation bump can be made of the same material, or they can be made of different materials. In specific configurations, the substrate may include semiconductor materials such as gallium nitride (GaN), silicon (Si), and silicon carbide (SiC), and the thermal conductivity of the substrate may be approximately 130–150 W / (m*k).

[0011] In one possible implementation, the semiconductor device in this application embodiment may include one or more heat dissipation bumps, and the number and position of the heat dissipation bumps may be reasonably set according to the actual connection relationship.

[0012] In some embodiments of this application, the semiconductor device may include active and passive regions. During the operation of the semiconductor device, a two-dimensional electron gas is generated at the interface between the barrier layer and the channel layer of the epitaxial layer. The region where the two-dimensional electron gas exists at this interface is the active region, and the region where the two-dimensional electron gas does not exist (or the two-dimensional electron gas is destroyed) is the passive region. In a specific configuration, the projections of each first electrode and the projections of the active region overlap in the thickness direction of the substrate. In some cases, each first electrode may be completely located within the active region; or, there may be partial patterns of one or more first electrodes that are not in the active region, which can be reasonably configured according to actual needs. In a specific implementation, the semiconductor device may include one or more cells, and each cell may contain multiple first electrodes, multiple second electrodes, and multiple control electrodes, and each cell may contain an active region.

[0013] In some embodiments of this application, the projection of the heat dissipation bump can overlap with the projection of the active region in the thickness direction of the substrate. When the semiconductor device is working, the heat source is mainly concentrated in the region between the first electrode and the second electrode. By placing the heat dissipation bump in the active region, the heat generated by the semiconductor device can be directly dissipated through the first electrode, the conductive connector in the dielectric via, and the heat dissipation bump, thereby improving the heat dissipation efficiency of the semiconductor device.

[0014] In a specific configuration, the projections of each second electrode and the active region can overlap in the thickness direction of the substrate. The projections of each control electrode can also overlap in the active region.

[0015] In practical implementation, the semiconductor device provided in this application embodiment is applied in a power amplifier. The semiconductor device can be electrically connected to the circuit board via heat dissipation bumps. That is, the semiconductor device in this application embodiment can be flip-chip mounted on the circuit board. In a specific configuration, a molding compound can be wrapped around the side of the semiconductor device facing away from the circuit board. Since the molding compound is generally quite thick and has very low thermal conductivity (<1W / (m*K)), its thermal conductivity is very poor. In this application embodiment, by flip-chip mounting the semiconductor device onto the circuit board, the circuit board dissipates heat more easily than the molding compound, providing a better heat dissipation path for the semiconductor device. The heat generated by the semiconductor device can be quickly dissipated through the heat dissipation bumps and the circuit board, further improving the heat dissipation efficiency of the semiconductor device.

[0016] In one possible implementation, the semiconductor device in this application embodiment may further include: a buffer layer located on the side of the dielectric layer facing away from the substrate, the buffer layer having an opening at a position corresponding to the heat dissipation bump. In the thickness direction of the substrate, the projection of the dielectric via lies within the range of the projection of the opening, and the projection of the heat dissipation bump covers the projection of the opening. A portion of the heat dissipation bump is embedded in the opening, and the edge of the heat dissipation bump overlaps the surface of the buffer layer facing away from the substrate. Thus, the heat dissipation bump can be engaged at the edge of the opening. In this way, the buffer layer can support and reinforce the heat dissipation bump, preventing it from detaching from the dielectric via under high temperature, high stress, etc., thereby improving the structural stability of the heat dissipation bump. Exemplarily, the buffer layer may include organic materials such as polyimide (PI), and the thickness of the buffer layer may be set to be greater than 5 micrometers.

[0017] In some embodiments of this application, the first electrodes in the semiconductor device can be arranged along a first direction, which is perpendicular to the thickness direction of the substrate. The distance between the first dielectric via and the center of each first electrode in the semiconductor device in the first direction can be smaller than the distance between the second dielectric via and the center of each first electrode in the semiconductor device in the first direction. That is, the first dielectric via is closer to the center of each first electrode in the semiconductor device in the first direction than the second dielectric via. Among the first electrodes arranged along the first direction, the distance between the first first electrode and the center is equal to the distance between the last first electrode and the center. During the operation of the semiconductor device, heat is more concentrated at the center of each first electrode in the semiconductor device. Therefore, setting a larger cross-sectional area of ​​the dielectric via near the center of each first electrode in the first direction can improve the heat dissipation uniformity of the semiconductor device, thereby improving the output power and reliability of the semiconductor device.

[0018] Of course, in some cases, the distance between the first dielectric via and the center of each first electrode in the semiconductor device in the first direction can also be equal to the distance between the second dielectric via and the center of each first electrode in the semiconductor device in the first direction. In specific configurations, the positions of the first and second dielectric vias can be rationally set according to the heat dissipation requirements of the semiconductor device.

[0019] In one possible implementation, the first electrodes, second electrodes, and control electrodes in the semiconductor device can be arranged along a first direction. In this embodiment, the first width of the first dielectric via can be greater than the first width of the second dielectric via, so that the cross-sectional area of ​​the first dielectric via is greater than the cross-sectional area of ​​the second dielectric via. The first width is the width of the dielectric via along a second direction, which is perpendicular to the thickness direction of the substrate, and the first direction and the second direction are mutually perpendicular. In a specific configuration, the second widths of the first and second dielectric vias can be the same, or they can be different, as long as the cross-sectional area of ​​the first dielectric via is greater than the cross-sectional area of ​​the second dielectric via. The second width is the width of the dielectric via along the first direction. In a specific configuration, the first electrodes and second electrodes can be arranged alternately. Each control electrode can be located between adjacent first and second electrodes.

[0020] In each via in a semiconductor device, the difference between the maximum and minimum first width of the via is greater than or equal to (n-1)*d micrometers, where n is the number of control electrodes in the semiconductor device and d is a coefficient greater than or equal to 0.5. This setting allows for significant differences in heat dissipation at different vias, effectively improving the heat dissipation uniformity of the semiconductor device. Specifically, the first width of the via is less than the width of the corresponding first electrode along the second direction, and the second width of the via is less than the width of the corresponding first electrode along the first direction. This ensures that the via does not exceed the range of the corresponding first electrode. Furthermore, the minimum distance between the edge of the via and the edge of the corresponding first electrode can be the aforementioned coefficient d, i.e., the distance between the edge of the via and the edge of the corresponding first electrode is greater than or equal to 0.5 micrometers, thus ensuring that the dimensions of the via meet processing limits.

[0021] In another possible implementation, the first electrodes, second electrodes, and control electrodes in the semiconductor device are arranged along a first direction. In this embodiment, the second width of the first dielectric via can be greater than the second width of the second dielectric via, where the second width is the width of the dielectric via along the first direction, so that the cross-sectional area of ​​the first dielectric via is greater than the cross-sectional area of ​​the second dielectric via. In specific configurations, the first widths of the first and second dielectric vias can be the same, or they can be different, as long as the cross-sectional area of ​​the first dielectric via is greater than the cross-sectional area of ​​the second dielectric via. The first width is the width of the dielectric via along a second direction, which is perpendicular to the thickness direction of the substrate, and the first and second directions are mutually perpendicular. In specific configurations, the first electrodes and second electrodes can be arranged alternately. Each control electrode can be located between adjacent first and second electrodes.

[0022] In each via in a semiconductor device, the difference between the maximum and minimum second width of the via is greater than or equal to (n-1)*d micrometers, where n is the number of control electrodes in the semiconductor device and d is a coefficient greater than or equal to 0.5. This setting allows for significant differences in heat dissipation at different vias, effectively improving the heat dissipation uniformity of the semiconductor device. Specifically, the first width of the via is less than the width of the corresponding connected first electrode along the second direction, and the second width of the via is less than the width of the corresponding connected first electrode along the first direction. This ensures that the via does not exceed the range of the corresponding connected first electrode. Furthermore, the minimum distance between the edge of the via and the edge of the corresponding connected first electrode can be the aforementioned coefficient d, thus ensuring that the dimensions of the via meet processing limits.

[0023] In this embodiment, by providing a heat dissipation bump on the side of the dielectric layer away from the substrate and by providing a dielectric via in the dielectric layer, with a conductive connector in the dielectric via, the heat generated by the semiconductor device can be dissipated through the first electrode, the conductive connector in the dielectric via, and the heat dissipation bump. Furthermore, by changing the cross-sectional area of ​​the dielectric via at different locations, the heat dissipation uniformity of the semiconductor device can be effectively improved. The following provides a detailed description of various implementation methods of the dielectric via in this embodiment.

[0024] In some embodiments of this application, the first electrodes, second electrodes, and control electrodes in the semiconductor device can be arranged along a first direction, which is perpendicular to the thickness direction of the substrate. Dielectric vias in the dielectric layer are distributed along the first direction, and the cross-sectional area of ​​the dielectric vias gradually decreases along the direction from the center to the edge of each first electrode in the first direction. During the operation of the semiconductor device, heat is mainly concentrated at the center of each first electrode. Setting the cross-sectional area of ​​each dielectric via to gradually decrease along the direction from the center to the edge of each first electrode in the first direction improves the heat dissipation efficiency at locations with concentrated heat sources and enhances the uniformity of heat dissipation. In one possible implementation, the ratio of the cross-sectional area of ​​the dielectric via to the area of ​​the corresponding connected first electrode gradually decreases along the direction from the center to the edge of each first electrode in the first direction. In specific configurations, the areas of each first electrode in the semiconductor device can be substantially equal, or the areas of different first electrodes in the semiconductor device can be different, depending on actual needs. In specific configurations, the first electrodes and second electrodes can be arranged alternately. Each control electrode can be located between adjacent first and second electrodes;

[0025] In one possible implementation, the semiconductor device may include a cell containing multiple first electrodes, multiple second electrodes, and multiple control electrodes. Furthermore, the cell may include a first connection portion and a second connection portion, with each control electrode interconnected via the first connection portion and each second electrode interconnected via the second connection portion. Thus, each second electrode and each control electrode in the cell can form an interdigital structure. The difference between the maximum and minimum values ​​of the first (or second) width of the dielectric via is greater than or equal to (n-1)*d micrometers, where n is the number of control electrodes in the semiconductor device, and d is a coefficient greater than or equal to 0.5. Furthermore, the first width of the dielectric via is less than the width of the corresponding connected first electrode along a second direction, and the second width of the dielectric via is less than the width of the corresponding connected first electrode along a first direction. The first width is the width of the dielectric via along the second direction, and the second width is the width of the dielectric via along the first direction. The cross-sectional area of ​​the dielectric via can gradually decrease along the direction from the center to the edge of the cell in the first direction. When a semiconductor device includes a single cell, the heat source is mainly concentrated at the center of the cell. The cross-sectional area of ​​the dielectric via gradually decreases along the direction from the center to the edge of the cell in the first direction, which can improve the heat dissipation uniformity of the semiconductor device.

[0026] In another possible implementation, the semiconductor device may include a plurality of cells arranged along a first direction. Each cell contains a plurality of first electrodes, a plurality of second electrodes, a plurality of control electrodes, a first connection portion, and a second connection portion. The control electrodes in the cells are interconnected via the first connection portions, and the second electrodes in the cells are interconnected via the second connection portions. In each cell, the difference between the maximum and minimum values ​​of the first width (or second width) of the dielectric via is greater than or equal to (n-1)*d micrometers, where n is the number of control electrodes in the semiconductor device, and d is a coefficient greater than or equal to 0.5. Furthermore, the first width of the dielectric via is smaller than the width of the corresponding connected first electrode along the second direction, and the second width of the dielectric via is smaller than the width of the corresponding connected first electrode along the first direction. The first width is the width of the dielectric via along the second direction, and the second width is the width of the dielectric via along the first direction. The cross-sectional area of ​​the dielectric via can gradually decrease along the direction from the center to the edge of each cell in the first direction. In some cases, the control electrodes in the cell are evenly spaced, and the distance between adjacent cells is small. For example, the distance between adjacent cells can be comparable to the distance between adjacent control electrodes in the cell. The heat source is mainly concentrated at the center of each cell in the semiconductor device. The cross-sectional area of ​​the dielectric via gradually decreases along the direction from the center to the edge of each cell in the first direction, which can improve the heat dissipation uniformity of the semiconductor device. Furthermore, at least two adjacent dielectric vias in the dielectric layer may have equal cross-sectional areas along the first direction. In specific configurations, two, three, or more adjacent dielectric vias may have equal cross-sectional areas, which can be configured according to actual conditions; examples are not provided here. It is understood that in the embodiments of this application, equal cross-sectional areas mean that the cross-sectional areas of two dielectric vias are equal within a certain error range. For example, this error range can be less than or equal to 5%, that is, the difference in cross-sectional areas of two dielectric vias is less than or equal to 5%.

[0027] In some embodiments of this application, the semiconductor device may include a plurality of cells arranged along a first direction. Each cell is provided with a plurality of first electrodes, a plurality of second electrodes, a plurality of control electrodes, a first connection portion, and a second connection portion. The control electrodes in the cells are interconnected through the first connection portions, and the plurality of second electrodes in the cells are interconnected through the second connection portions. In each cell of the semiconductor device, the difference between the maximum and minimum values ​​of the first width (or second width) of the dielectric via is greater than or equal to (n-1)*d micrometers, where n is the number of control electrodes in the semiconductor device, and d is a coefficient greater than or equal to 0.5. Furthermore, the first width of the dielectric via is less than the width of the corresponding connected first electrode along the second direction, and the second width of the dielectric via is less than the width of the corresponding connected first electrode along the first direction. The first width is the width of the dielectric via along the second direction, and the second width is the width of the dielectric via along the first direction. The cross-sectional area of ​​each dielectric via in each cell is equal, and along the direction from the center to the edge of each cell in the first direction, the cross-sectional area of ​​the dielectric via in each cell gradually decreases. In some cases, the distance between adjacent cells can be greater than the distance between adjacent control electrodes within a cell, or it can be comparable to the distance between adjacent control electrodes within a cell. Along the direction from the center to the edge of each cell in the semiconductor device, the cross-sectional area of ​​the dielectric vias in each cell gradually decreases, which can improve the heat dissipation efficiency at the center of each cell in the semiconductor device, thereby improving the overall heat dissipation uniformity of the semiconductor device. It is understood that in the embodiments of this application, equal cross-sectional areas mean that the cross-sectional areas of two dielectric vias are equal within a certain error range. For example, this error range can be less than or equal to 5%, that is, the difference in cross-sectional areas of two dielectric vias is less than or equal to 5%.

[0028] In some embodiments of this application, the semiconductor device may include a plurality of cells arranged along a first direction, each cell having a plurality of first electrodes, a plurality of second electrodes, and a plurality of control electrodes arranged along the first direction; wherein the first direction is perpendicular to the thickness direction of the substrate. Each cell may further include a first connection portion and a second connection portion, wherein the control electrodes in the cell can be interconnected through the first connection portion, and the second electrodes in the cell can be interconnected through the second connection portion. In each cell, the difference between the maximum and minimum values ​​of the first width (or second width) of the dielectric via is greater than or equal to (n-1)*d micrometers, where n is the number of control electrodes in the semiconductor device, and d is a coefficient greater than or equal to 0.5. Furthermore, the first width of the dielectric via is less than the width of the corresponding connected first electrode along the second direction, and the second width of the dielectric via is less than the width of the corresponding connected first electrode along the first direction. The first width is the width of the dielectric via along the second direction, and the second width is the width of the dielectric via along the first direction. In each cell, the dielectric vias are distributed along a first direction, and the cross-sectional area of ​​the dielectric vias gradually decreases along the direction from the center to the edge of the cell in the first direction. In some cases, the distance between adjacent cells is large, and the heat source is mainly concentrated at the center of the cell. Therefore, setting the cross-sectional area of ​​the dielectric via at the center of each cell to be larger can improve the heat dissipation uniformity of the semiconductor device.

[0029] In one possible implementation, along the direction from the center to the edge of each cell in the semiconductor device, the cross-sectional area of ​​the dielectric via at the center of each cell gradually decreases. In some cases, the distance between adjacent cells is large, and the heat source is mainly concentrated at the center of each cell, as well as at the center of the semiconductor device as a whole. Setting the cross-sectional area of ​​the dielectric via at the center of each cell to be large, and setting the cross-sectional area of ​​the dielectric via in the cells located at the center of each cell in the semiconductor device to be large, can further improve the heat dissipation uniformity of the semiconductor device. In a specific setting, the cross-sectional area of ​​a dielectric via in a cell near the center of the semiconductor device can be larger than the cross-sectional area of ​​the dielectric via at the corresponding position in a cell near the edge of the semiconductor device.

[0030] The above describes various implementation methods of the dielectric via in the embodiments of this application. In specific settings, the cross-sectional area of ​​the dielectric via can be reasonably set according to the specific structure of the semiconductor device and the location of the heat source. Examples will not be given here.

[0031] Secondly, embodiments of this application also provide a method for fabricating a semiconductor device, which may include:

[0032] Step 1: Form a plurality of first electrodes, a plurality of second electrodes, and a plurality of control electrodes on a substrate. In a specific implementation, insulating material may be deposited in the gaps between each first electrode, each second electrode, and each control electrode to form an insulating layer for insulating the first electrodes, second electrodes, and control electrodes from each other. Furthermore, prior to Step 1, an epitaxial layer may be formed on the substrate. Exemplarily, the epitaxial layer may specifically include a channel layer, a barrier layer, or other film layers, and the specific structure of the epitaxial layer may be configured according to the type of semiconductor device.

[0033] Step 2: A dielectric layer is formed on each of the first electrodes, each of the second electrodes, and each of the control electrodes, and multiple dielectric vias are formed in the dielectric layer. The projection of the dielectric vias along the thickness direction of the substrate lies within the projection range of the first electrodes. The multiple dielectric vias in the dielectric layer may include first dielectric vias and second dielectric vias, with the cross-sectional area of ​​the first dielectric via being larger than the cross-sectional area of ​​the second dielectric via. This cross-sectional area refers to the cross-sectional area of ​​the dielectric via along the direction perpendicular to the substrate thickness.

[0034] In step two above, forming multiple dielectric vias in the dielectric layer can specifically include:

[0035] A buffer layer is formed on top of the dielectric layer and patterned to create openings within it. For example, an organic material such as polyimide (PI) can be used to fabricate the buffer layer, and its thickness can be greater than 5 micrometers. Next, holes are drilled in the dielectric layer within the opening areas, and conductive materials are filled into the holes. For instance, metals such as copper, tin, or gold can be filled into the holes to form dielectric vias and conductive connectors disposed within them. This ensures that the projection of each dielectric via onto the substrate falls within the projection range of the opening onto the substrate, allowing subsequently formed heat dissipation bumps to connect to the conductive connectors in the dielectric vias through the openings. Furthermore, the projection of the opening onto the substrate is smaller than the area of ​​the heat dissipation bump to be formed, so that a portion of the subsequently formed heat dissipation bump is embedded within the opening, and the heat dissipation bump engages with the edge of the opening.

[0036] Step 3: Form heat dissipation bumps on the dielectric layer. Each dielectric via is provided with a conductive connector. The heat dissipation bumps can be electrically connected to the first electrode through the conductive connectors, and are insulated from the second electrode and the control electrode through the dielectric layer. The thermal conductivity of the heat dissipation bumps is greater than that of the substrate. In one possible implementation, the ratio of the thermal conductivity of the heat dissipation bumps to that of the substrate can be greater than 1.05, meaning the heat dissipation bumps have high thermal conductivity and good heat dissipation effect. For example, the thermal conductivity of the heat dissipation bumps can be greater than 50 W / (m·K). Thermally and electrically conductive materials can be used to fabricate the heat dissipation bumps; for example, metals such as copper, tin, and gold can be used.

[0037] In addition, the bottom of the heat dissipation bump is embedded in the opening of the buffer layer, and the edge of the heat dissipation bump overlaps the surface of the buffer layer away from the substrate. In this way, the buffer layer can support and reinforce the heat dissipation bump, preventing the heat dissipation bump from detaching from the dielectric via under high temperature, high stress and other conditions, thereby improving the structural stability of the heat dissipation bump.

[0038] In one possible implementation, the semiconductor device includes an active region, and the projections of each first electrode and the active region overlap in the thickness direction of the substrate. In step three above, forming heat dissipation bumps on the dielectric layer can specifically include forming heat dissipation bumps at positions corresponding to the active region, such that the projections of the heat dissipation bumps in the thickness direction of the substrate overlap with the active region. When the semiconductor device is operating, the heat source is mainly concentrated in the region between the first and second electrodes. By placing heat dissipation bumps in the active region, the heat generated by the semiconductor device can be directly dissipated through the first electrodes, the conductive connectors in the dielectric vias, and the heat dissipation bumps, thereby improving the heat dissipation efficiency of the semiconductor device.

[0039] In the semiconductor device fabrication method provided in this application embodiment, a dielectric via is formed in a dielectric layer, and a heat dissipation bump is formed on top of the dielectric layer. The heat dissipation bump can be electrically connected to a first electrode through a conductive connector in the dielectric via. Furthermore, the thermal conductivity of the heat dissipation bump is greater than that of the substrate, meaning the heat dissipation bump has a higher thermal conductivity. Thus, the heat generated by the semiconductor device during operation can be dissipated through the first electrode, the conductive connector in the dielectric via, and the heat dissipation bump. Moreover, the multiple dielectric vias in the dielectric layer can include first dielectric vias and second dielectric vias, with the cross-sectional area of ​​the first dielectric via being larger than that of the second dielectric via. The heat generated by the semiconductor device during operation is dissipated through the first electrode, the conductive connector in the dielectric via, and the heat dissipation bump. The heat dissipation capacity of the semiconductor device is related to the contact area between the first electrode and the conductive connector, meaning the heat dissipation capacity of the semiconductor device is related to the cross-sectional area of ​​the dielectric via; the larger the cross-sectional area of ​​the dielectric via, the better the heat dissipation effect at that location. The first dielectric via can be placed at a location where heat dissipation of the semiconductor device is relatively concentrated, thereby improving the heat dissipation uniformity of the semiconductor device, and consequently improving the output power and reliability of the semiconductor device. Furthermore, the structure of the semiconductor devices in this embodiment has low requirements for processing equipment, is less difficult to manufacture, and has high mass production capability.

[0040] The technical solution of this application embodiment can effectively improve the problem of uneven temperature distribution by changing the cross-sectional area of ​​the medium through-hole at different locations. It is understood that in this application embodiment, the difference between the cross-sectional areas of the first medium through-hole and the second medium through-hole is greater than the error range of the manufacturing process. For example, the difference between the cross-sectional areas of the first medium through-hole and the second medium through-hole can be greater than 5%.

[0041] In some embodiments of this application, the first electrodes in the semiconductor device can be arranged along a first direction, which is perpendicular to the thickness direction of the substrate. In step two above, the distance between the first dielectric via and the center of each first electrode in the semiconductor device in the first direction can be smaller than the distance between the second dielectric via and the center of each first electrode in the semiconductor device in the first direction. That is, the first dielectric via is closer to the center of each first electrode in the semiconductor device in the first direction than the second dielectric via. Among the first electrodes arranged along the first direction, the distance between the first first electrode and the center is equal to the distance between the last first electrode and the center. During the operation of the semiconductor device, heat is more concentrated at the center of each first electrode in the semiconductor device. Therefore, setting a larger cross-sectional area of ​​the dielectric via near the center of each first electrode in the first direction can improve the heat dissipation uniformity of the semiconductor device, thereby improving the output power and reliability of the semiconductor device.

[0042] Of course, in some cases, the distance between the first dielectric via and the center of each first electrode in the semiconductor device in the first direction can also be equal to the distance between the second dielectric via and the center of each first electrode in the semiconductor device in the first direction. In specific configurations, the positions of the first and second dielectric vias can be rationally set according to the heat dissipation requirements of the semiconductor device.

[0043] Thirdly, this application embodiment also provides a power amplifier. The power amplifier provided in this application embodiment may include any of the semiconductor devices mentioned in the first aspect above and a circuit board. The semiconductor device can be electrically connected to the circuit board through heat dissipation bumps, that is, the semiconductor device can be flip-chip mounted on the circuit board. In a specific configuration, a plastic encapsulation layer may also be wrapped around the side of the semiconductor device away from the circuit board. Since the plastic encapsulation layer is generally quite thick and has a very low thermal conductivity (<1W / (m*K)), its thermal conductivity is very poor. In this application embodiment, by flip-chip mounting the semiconductor device on the circuit board, the circuit board dissipates heat more easily than the plastic encapsulation layer, providing a better heat dissipation path for the semiconductor device. The heat generated by the semiconductor device can be quickly dissipated through the heat dissipation bumps and the circuit board, further improving the heat dissipation efficiency of the semiconductor device. Since the semiconductor devices in the first aspect of this application embodiment have high output power and reliability, the power amplifier including any of the above semiconductor devices also has good performance and reliability.

[0044] Fourthly, embodiments of this application also provide an electronic device, which may include the power amplifier described in the third aspect above and a housing, wherein the power amplifier may be located within the housing. Because the power amplifier described in the third aspect has good performance and reliability, the electronic device including the power amplifier also has good performance and reliability. Attached Figure Description

[0045] Figure 1 This is a schematic diagram illustrating an application scenario of an embodiment of this application;

[0046] Figure 2 This is a schematic diagram of the application system architecture according to an embodiment of this application;

[0047] Figure 3a This is a schematic diagram of the power amplifier provided in an embodiment of this application;

[0048] Figure 3b for Figure 3a A schematic diagram of the cross-section at the dashed line NN';

[0049] Figure 4 A top view of the semiconductor device provided in the embodiments of this application;

[0050] Figure 5for Figure 4 A schematic diagram of the cross-section at the dashed line CC'.

[0051] Figure 6 This is a schematic diagram of the power amplifier structure in an embodiment of this application;

[0052] Figure 7 This is another top view schematic diagram of the semiconductor device provided in the embodiments of this application;

[0053] Figure 8 This is another top view schematic diagram of the semiconductor device provided in the embodiments of this application;

[0054] Figure 9 The above diagram illustrates the simulation results of the embodiments and comparative examples of this application.

[0055] Figure 10 This is another top view schematic diagram of the semiconductor device provided in the embodiments of this application;

[0056] Figure 11 This is another top view schematic diagram of the semiconductor device provided in the embodiments of this application;

[0057] Figure 12 This is another top view schematic diagram of the semiconductor device provided in the embodiments of this application;

[0058] Figure 13 This is another top view schematic diagram of the semiconductor device provided in the embodiments of this application;

[0059] Figure 14 This is another top view schematic diagram of the semiconductor device provided in the embodiments of this application;

[0060] Figure 15 This is another top view schematic diagram of the semiconductor device provided in the embodiments of this application;

[0061] Figure 16 This is another top view schematic diagram of the semiconductor device provided in the embodiments of this application;

[0062] Figure 17 A flowchart illustrating a method for fabricating a semiconductor device as provided in an embodiment of this application;

[0063] Figures 18 to 21 The diagram shows the structure of each step in the manufacturing method provided in the embodiments of this application.

[0064] Figure label:

[0065] 101-Baseband chip; 102-Power amplifier; 103-Antenna; 104-Filter; 105-Low noise amplifier; S-Source; D-Drain; G-Gate; A-Active region; B-Non-active region; 10-Substrate; 11-First electrode; 12-Second electrode; 13-Control electrode; 14-Dielectric layer; 15-Heat sink bump; 16-Epipolar layer; 17-Insulating layer; 18-Buffer layer; 191-First connection; 192-Second connection; 100-Semiconductor device; 100m-Cell; 200-Circuit board; T-Dielectric via; U-Opening; F1-First direction; F2-Second direction. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0067] It should be noted that the accompanying drawings in this application are for illustrative purposes only and do not represent actual scale. The same reference numerals in the accompanying drawings denote the same or similar structures, and therefore, repeated descriptions of them will be omitted.

[0068] The terms describing position and direction used in this application, such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," are merely illustrative examples based on the orientation or positional relationships shown in the accompanying drawings. They are intended solely for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Changes may be made as needed, and all such changes are included within the scope of protection of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0069] To facilitate understanding of the technical solution of this application, the application scenarios of this application will be introduced first, in conjunction with the accompanying drawings.

[0070] This application provides a semiconductor device, a method for manufacturing the same, a power amplifier, and an electronic device. The semiconductor device provided in this application can be a high electron mobility transistor (HMT) device; exemplarily, the semiconductor device in this application can be a GaN-based HMT device. Of course, in some cases, the semiconductor device in this application can also be other types of transistor devices, and this application does not limit the scope of the application. Figure 1 This is a schematic diagram illustrating an application scenario of an embodiment of this application, such as... Figure 1As shown, the semiconductor devices provided in this application embodiment can be applied to various types of electronic devices. For example, the semiconductor devices in this application embodiment can be applied to: (1) tablet computers; (2) mobile phones, such as mobile phones, satellite phones, etc.; (3) watches; (4) glasses, such as virtual reality (VR) glasses, augmented reality (AR) glasses, glasses with communication functions, etc.; (5) headphones; (6) routers and other terminal devices. Of course, the semiconductor devices provided in this application embodiment can also be applied to other electronic devices, which will not be listed here.

[0071] Figure 2 This is a schematic diagram of the application system architecture of an embodiment of this application, such as... Figure 2 As shown, the electronic device provided in this application embodiment may include: a baseband chip 101, a power amplifier 102, an antenna 103, a filter 104, and a low-noise amplifier 105. During the operation of the electronic device, the radio frequency (RF) signal generated by the baseband chip 101 is input to the power amplifier 102. The power amplifier 102 amplifies the RF signal and transmits the amplified RF signal to the antenna 103 to complete the RF signal transmission in the transmission path. In specific implementations, a filter 104 (or a switch) can be set in the transmission path according to the supported frequency band of the power amplifier 102 to support the amplification requirements of different frequency band RF signals. The RF signal received by the antenna 103 passes through the filter 104, the low-noise amplifier 105, and other devices before being input to the baseband chip 101 to complete the RF signal transmission in the receiving path. The semiconductor device in this application embodiment can be applied to the power amplifier 102. Furthermore, the power amplifier 102 may also include circuits and power supply chips that match the semiconductor device. Of course, in practical applications, the semiconductor device provided in this application embodiment can also be applied to other components of the electronic device, which is not limited here.

[0072] Figure 3a This is a schematic diagram of the power amplifier provided in an embodiment of this application. Figure 3b for Figure 3a A schematic diagram of the cross-section at the dashed line NN', as shown below. Figure 3a and Figure 3bAs shown, the HEMT device may include multiple source electrodes S, multiple drain electrodes D, and multiple gate electrodes G located in the active region A. When connecting the HEMT device to the circuit board 200, the HEMT device is mounted upright on the circuit board 200. To avoid damaging the structure in the epitaxial layer 16 below the active region A, the source electrodes S need to be led out to the non-active region B and connected to the circuit board 200 below through the conductive vias V in the substrate 10. To improve the heat dissipation uniformity of the HEMT device, the spacing between the gate electrodes G in the active region A is adjusted so that the spacing between the gate electrodes G in the center of the HEMT device is larger, and the spacing between the gate electrodes G at the edge of the HEMT device is smaller, for example... Figure 3a The spacing between the gates G in the HEMT device is g1 > g2 > g3, which makes it easier for heat to dissipate from the center of the HEMT device and improves the heat dissipation uniformity. However, in order to keep the overall size of the HEMT device basically unchanged, the spacing between the gates G at the edge of the HEMT device is actually adjusted by reducing the spacing between the gates G. Therefore, the heat dissipation effect at the center of the HEMT device is still poor, and it cannot improve the heat dissipation uniformity of the HEMT device. Furthermore, the spacing between the gates G at the edge of the HEMT device is very small, reaching the limit of the fabrication process, making the fabrication difficult.

[0073] Based on this, in order to improve the heat dissipation uniformity of semiconductor devices and thus enhance their output power and reliability, the technical solutions of this application have improved the structure of semiconductor devices. The technical solutions provided by the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0074] Figure 4 This is a top view schematic diagram of the semiconductor device provided in the embodiments of this application. Figure 5 for Figure 4 A schematic diagram of the cross-section at the dashed line CC', as shown below. Figure 4 and Figure 5As shown, the semiconductor device provided in this application embodiment may include: a substrate 10, a plurality of first electrodes 11, a plurality of second electrodes 12, a plurality of control electrodes 13, a dielectric layer 14, and heat dissipation bumps 15. The thermal conductivity of the heat dissipation bumps 15 is greater than that of the substrate 10. Each first electrode 11, each second electrode 12, and each control electrode 13 is located between the substrate 10 and the dielectric layer 14, and the heat dissipation bumps 15 are located on the side of the dielectric layer 14 facing away from the substrate 10. The dielectric layer 14 includes a plurality of dielectric vias T, each dielectric via T having a conductive connector disposed therein. The heat dissipation bumps 15 are electrically connected to the first electrodes 11 through the conductive connectors; and through the dielectric layer 14, the heat dissipation bumps 15 are insulated from the second electrodes 12 and the control electrodes 13. In the thickness direction of the substrate 10, the projection of the dielectric vias T is located within the projection range of the first electrodes 11. The plurality of dielectric vias T in the dielectric layer 14 may include first dielectric vias T1 and second dielectric vias T2. The cross-sectional area of ​​the first dielectric via T1 is greater than the cross-sectional area of ​​the second dielectric via T2. The cross-sectional area here refers to the cross-sectional area of ​​the dielectric via T along the direction perpendicular to the thickness of the substrate 10. It is understood that this is done to clearly illustrate the structure of each component. Figure 4 The dielectric layer is omitted, and the location of the dielectric via is indicated by a dashed box.

[0075] In the semiconductor device provided in this embodiment, a heat dissipation bump 15 is provided on the side of the dielectric layer 14 facing away from the substrate 10, and a dielectric via T is provided in the dielectric layer 14. The heat dissipation bump 15 can be electrically connected to the first electrode 11 through a conductive connector in the dielectric via T. Furthermore, the thermal conductivity of the heat dissipation bump 15 is greater than that of the substrate 10, i.e., the thermal conductivity of the heat dissipation bump 15 is relatively high. Thus, the heat generated by the semiconductor device during operation can be dissipated through the first electrode 11, the conductive connector in the dielectric via T, and the heat dissipation bump 15. Moreover, the plurality of dielectric vias T in the dielectric layer 14 may include a first dielectric via T1 and a second dielectric via T2, wherein the cross-sectional area of ​​the first dielectric via T1 is greater than the cross-sectional area of ​​the second dielectric via T2. The heat generated by the semiconductor device during operation is dissipated through the first electrode 11, the conductive connector in the dielectric via T, and the heat dissipation bump 15. The heat dissipation capacity of the semiconductor device is related to the contact area between the first electrode 11 and the conductive connector, that is, the heat dissipation capacity of the semiconductor device is related to the cross-sectional area of ​​the dielectric via T. The larger the cross-sectional area of ​​the dielectric via T, the better the heat dissipation effect at that location. The first dielectric via T1 can be placed at a location where heat dissipation of the semiconductor device is relatively concentrated, thereby improving the heat dissipation uniformity of the semiconductor device, and thus improving the output power and reliability of the semiconductor device. In addition, the structure of the semiconductor device in this embodiment has low requirements for processing equipment, is less difficult to manufacture, and has high mass production capability.

[0076] The technical solution of this application embodiment can effectively improve the problem of uneven temperature distribution by changing the cross-sectional area of ​​the medium through hole T at different locations. It is understood that in this application embodiment, the difference between the cross-sectional areas of the first medium through hole T1 and the second medium through hole T2 is greater than the error range of the manufacturing process. For example, the difference between the cross-sectional areas of the first medium through hole T1 and the second medium through hole T2 can be greater than 5%.

[0077] In one possible implementation, the projection range of the first electrode 11 in the direction perpendicular to the substrate 10 may have projections of one or more dielectric vias T, which can be set according to actual conditions. The cross-sectional shape of the dielectric via T in the direction parallel to the substrate 10 can be various shapes such as rectangle, circle, ellipse, polygon (≥4 sides, such as octagon), which can be set according to actual needs.

[0078] In one possible implementation, the semiconductor device in this embodiment may further include an epitaxial layer 16 located between the film layer containing the first electrode 11 and the substrate 10. Exemplarily, the epitaxial layer 16 may specifically include a channel layer, a barrier layer, or other film layers. The specific structure of the epitaxial layer 16 can be configured according to the type of semiconductor device. Furthermore, the semiconductor device in this embodiment may also include an insulating layer 17 located between the dielectric layer 14 and the epitaxial layer 16. The first electrode 11, the second electrode 12, and the control electrode 13 can be mutually insulated through the insulating layer 17. In specific configurations, the positions of each first electrode 11, each second electrode 12, and each control electrode 13 can be reasonably set according to actual needs. For example, each first electrode 11 and each second electrode 12 can be arranged alternately along a first direction F1, and each control electrode 13 can be located between adjacent first electrodes 11 and second electrodes 12. Exemplarily, the semiconductor device in this embodiment may be a high electron mobility transistor device, where the first electrode 11 can be the source, the second electrode 12 can be the drain, and the control electrode 13 can be the gate. When the semiconductor device in the embodiments of this application is another type of transistor, the first electrode 11, the second electrode 12 and the control electrode 13 can be configured accordingly, and examples will not be given here.

[0079] In one possible implementation, the ratio of the thermal conductivity of the heat dissipation bump 15 to the thermal conductivity of the substrate 10 can be greater than 1.05, meaning the heat dissipation bump 15 has high thermal conductivity and good heat dissipation effect. For example, the thermal conductivity of the heat dissipation bump 15 can be greater than 50 W / (m·K). Furthermore, the heat dissipation bump 15 also has good electrical conductivity. The heat dissipation bump 15 can be electrically connected to the first electrode 11 through the dielectric via T. Therefore, the first electrode 11 can be directly led out through the heat dissipation bump 15, thereby shortening the interconnection distance between the first electrode 11 and other components. In a specific configuration, the heat dissipation bump 15 can include thermally and electrically conductive materials, such as copper, tin, or gold. In addition, the conductive connector in the dielectric via T also has good electrical and thermal conductivity; for example, the conductive connector can include copper, tin, or gold. The conductive connector and the heat dissipation bump 15 can be made of the same material, or they can be made of different materials. In a specific configuration, the substrate 10 may include semiconductor materials such as gallium nitride (GaN), silicon (Si), and silicon carbide (SiC), and the thermal conductivity of the substrate 10 may be approximately 130–150 W / (m*k).

[0080] In one possible implementation, the semiconductor device in this application embodiment may include one or more heat dissipation bumps 15, and the number and position of the heat dissipation bumps 15 may be reasonably set according to the actual connection relationship.

[0081] Continue to refer to Figure 4 and Figure 5 In some embodiments of this application, the semiconductor device may include an active region A and a passive region (not shown in the figure). During the operation of the semiconductor device, a two-dimensional electron gas is generated at the interface between the barrier layer and the channel layer of the epitaxial layer 16. The region where the two-dimensional electron gas exists at this interface is the active region A, and the region where the two-dimensional electron gas does not exist (or the two-dimensional electron gas is destroyed) is the passive region. In a specific configuration, the projections of each first electrode 11 and the projections of the active region A overlap in the thickness direction of the substrate 10. In some cases, each first electrode 11 may be completely located within the active region A; or, there may be a partial pattern of one or more first electrodes 11 that is not in the active region A, which can be reasonably configured according to actual needs. In a specific implementation, the semiconductor device may include one or more cells, and each cell may contain multiple first electrodes 11, multiple second electrodes 12, and multiple control electrodes 13, for example, Figure 4 The following is an illustration using a single cell in a semiconductor device as an example. Each cell can have an active region A.

[0082] In some embodiments of this application, the projection of the heat dissipation bump 15 may overlap with the projection of the active region A in the thickness direction of the substrate 10. When the semiconductor device is working, the heat source is mainly concentrated in the region between the first electrode 11 and the second electrode 12. By placing the heat dissipation bump 15 in the active region A, the heat generated by the semiconductor device can be directly dissipated through the first electrode 11, the conductive connector in the dielectric via T, and the heat dissipation bump 15, thereby improving the heat dissipation efficiency of the semiconductor device.

[0083] In a specific configuration, in the thickness direction of the substrate 10, the projection of each second electrode 12 may overlap with the active region A, and the projection of each control electrode 13 may overlap with the active region A.

[0084] Figure 6 This is a schematic diagram of the power amplifier structure in the embodiments of this application, combined with... Figures 4 to 6 The semiconductor devices provided in the embodiments of this application are applied in power amplifiers. Figure 6 The example shown is a semiconductor device 100 with a single cell. In actual implementation, the number of cells in the semiconductor device 100 can be adjusted according to specific needs. The semiconductor device 100 can be electrically connected to the circuit board 200 via heat dissipation bumps 15. That is, the semiconductor device 100 in this embodiment can be flip-chip mounted on the circuit board 200. In a specific implementation, a molding compound (not shown) can be wrapped around the side of the semiconductor device 100 facing away from the circuit board 200. Since the molding compound is generally thick and has very low thermal conductivity (<1W / (m*K)), its thermal conductivity is very poor. In this embodiment, by flip-chip mounting the semiconductor device 100 on the circuit board 200, the circuit board 200 dissipates heat more easily than the molding compound, providing a better heat dissipation path for the semiconductor device 100. This allows the heat generated by the semiconductor device 100 to be quickly dissipated through the heat dissipation bumps 15 and the circuit board 200, further improving the heat dissipation efficiency of the semiconductor device 100.

[0085] like Figure 4 and Figure 5As shown, in one possible implementation, the semiconductor device in this embodiment may further include a buffer layer 18 located on the side of the dielectric layer 14 facing away from the substrate 10. The buffer layer 18 has an opening U at a position corresponding to the heat dissipation bump 15. In the thickness direction of the substrate 10, the projection of the dielectric via T is within the range of the projection of the opening U, and the projection of the heat dissipation bump 15 covers the projection of the opening U. A portion of the heat dissipation bump 15 is embedded in the opening U, and the edge of the heat dissipation bump 15 overlaps the surface of the buffer layer 18 facing away from the substrate 10. In this way, the heat dissipation bump 15 can be engaged at the edge of the opening U. Thus, the buffer layer 18 can support and reinforce the heat dissipation bump 15, preventing the heat dissipation bump 15 from detaching from the dielectric via T under high temperature, high stress, etc., thereby improving the structural stability of the heat dissipation bump 15. Exemplarily, the buffer layer 18 may include organic materials such as polyimide (PI), and the thickness of the buffer layer 18 may be set to be greater than 5 micrometers.

[0086] Continue to refer to Figure 4 and Figure 5 In some embodiments of this application, the first electrodes 11 in the semiconductor device can be arranged along a first direction F1, which is perpendicular to the thickness direction of the substrate 10. The distance between the first dielectric via T1 and the center of each first electrode 11 in the semiconductor device along the first direction F1 can be smaller than the distance between the second dielectric via T2 and the center of each first electrode 11 in the semiconductor device along the first direction F1. That is, the first dielectric via T1 is closer to the center of each first electrode 11 in the semiconductor device along the first direction F1 than the second dielectric via T2. Among the first electrodes 11 arranged along the first direction F1, the distance between the first first electrode 11 and the center is equal to the distance between the last first electrode 11 and the center. During the operation of the semiconductor device, heat is more concentrated at the center of each first electrode 11 in the semiconductor device. Therefore, setting a larger cross-sectional area of ​​the dielectric via T near the center of each first electrode 11 along the first direction F1 can improve the heat dissipation uniformity of the semiconductor device, thereby improving the output power and reliability of the semiconductor device.

[0087] Of course, in some cases, the distance between the first dielectric via T1 and the center of each first electrode 11 in the semiconductor device along the first direction F1 can also be equal to the distance between the second dielectric via T2 and the center of each first electrode 11 in the semiconductor device along the first direction F1. In specific configurations, the positions of the first dielectric via T1 and the second dielectric via T2 can be reasonably set according to the heat dissipation requirements of the semiconductor device.

[0088] Figure 7This is another top view schematic diagram of the semiconductor device provided in the embodiments of this application. In order to clearly illustrate the structure of each component, Figure 7 The dielectric layer and heat dissipation bumps are omitted, and the dielectric vias are indicated by dashed boxes. For example... Figure 7 As shown, in one possible implementation, the first electrodes 11, second electrodes 12, and control electrodes 13 in the semiconductor device can be arranged along a first direction F1. In this embodiment, the first width L1 of the first dielectric via T1 can be greater than the first width L1 of the second dielectric via T2, so that the cross-sectional area of ​​the first dielectric via T1 is greater than the cross-sectional area of ​​the second dielectric via T2. The first width L1 is the width of the dielectric via T along the second direction F2, which is perpendicular to the thickness direction of the substrate 10, and the first direction F1 and the second direction F2 are perpendicular to each other. In a specific configuration, the second width L2 of the first dielectric via T1 and the second dielectric via T2 can be the same, or they can be different, as long as the cross-sectional area of ​​the first dielectric via T1 is greater than the cross-sectional area of ​​the second dielectric via T2. The second width L2 is the width of the dielectric via T along the first direction F1. In a specific configuration, the first electrodes 11 and the second electrodes 12 can be arranged alternately. Each control electrode 13 can be located between adjacent first electrode 11 and second electrode 12.

[0089] Continue to refer to Figure 7 In each via T in the semiconductor device, the difference between the maximum and minimum values ​​of the first width L1 of the via T is greater than or equal to (n-1)*d micrometers, where n is the number of control electrodes 13 in the semiconductor device, and d is a coefficient greater than or equal to 0.5. This setting allows for significant differences in heat dissipation effects at different via T locations, thereby effectively improving the heat dissipation uniformity of the semiconductor device. Specifically, the first width L1 of the via T is less than the width W of the corresponding connected first electrode 11 along the second direction F2, and the second width L2 of the via T is less than the width Q of the corresponding connected first electrode 11 along the first direction F1. This ensures that the via T does not exceed the range of the corresponding connected first electrode 11. Furthermore, the minimum distance between the edge of the via T and the edge of the corresponding connected first electrode 11 can be the aforementioned coefficient d, i.e., the distance between the edge of the via T and the edge of the corresponding connected first electrode 11 is greater than or equal to 0.5 micrometers, thus ensuring that the dimensions of the via T meet the processing limits.

[0090] Figure 8 This is another top view schematic diagram of the semiconductor device provided in the embodiments of this application, as shown below. Figure 8As shown, in another possible implementation, the first electrodes 11, second electrodes 12, and control electrodes 13 in the semiconductor device are arranged along a first direction F1. In this embodiment, the second width L2 of the first dielectric via T1 can be greater than the second width L2 of the second dielectric via T2. The second width L2 is the width of the dielectric via T along the first direction F1, so that the cross-sectional area of ​​the first dielectric via T1 is greater than the cross-sectional area of ​​the second dielectric via T2. In a specific configuration, the first width L1 of the first dielectric via T1 and the second dielectric via T2 can be the same, or the first width L1 of the first dielectric via T1 and the second dielectric via T2 can be different, as long as the cross-sectional area of ​​the first dielectric via T1 is greater than the cross-sectional area of ​​the second dielectric via T2. The first width L1 is the width of the dielectric via T along the second direction F2, which is perpendicular to the thickness direction of the substrate 10, and the first direction F1 and the second direction F2 are perpendicular to each other. In a specific configuration, the first electrodes 11 and the second electrodes 12 can be arranged alternately. Each control electrode 13 can be located between adjacent first electrode 11 and second electrode 12.

[0091] Continue to refer to Figure 8 In each via T in the semiconductor device, the difference between the maximum and minimum values ​​of the second width L2 of the via T is greater than or equal to (n-1)*d micrometers, where n is the number of control electrodes 13 in the semiconductor device, and d is a coefficient greater than or equal to 0.5. This setting allows for significant differences in heat dissipation effects at different via T locations, thereby effectively improving the heat dissipation uniformity of the semiconductor device. Specifically, the first width L1 of the via T is less than the width W of the corresponding connected first electrode 11 along the second direction F2, and the second width L2 of the via T is less than the width Q of the corresponding connected first electrode 11 along the first direction F1. This ensures that the via T does not exceed the range of the corresponding connected first electrode 11. Furthermore, the minimum distance between the edge of the via T and the edge of the corresponding connected first electrode 11 can be the aforementioned coefficient d, thereby ensuring that the dimensions of the via T meet the processing limits.

[0092] Figure 9 This is a schematic diagram of simulation results for the embodiments and comparative examples of this application, as shown below. Figure 9 As shown, curve M1 is the temperature distribution curve at different locations in the comparative example, and curve M2 is the temperature distribution curve at different locations in the embodiment of this application. Figure 9The horizontal axis represents different positions along the first direction, and the vertical axis represents the temperature value at each position. The difference between this embodiment and the comparative example is that in this embodiment, the first dielectric via is closer to the center of each first electrode in the semiconductor device along the first direction than the second dielectric via, and the cross-sectional area of ​​the first dielectric via is larger than that of the second dielectric via. In the comparative example, the cross-sectional areas of the dielectric vias at different positions are equal. Apart from this, the other structures of this embodiment and the comparative example are the same. For curve M1, the temperature at the middle position is significantly higher than the temperature at the edge position, indicating a significant problem of uneven temperature distribution in the comparative example, with a temperature deviation of approximately 3.7℃. For curve M2, the temperature difference between the middle and edge positions is smaller, with a temperature deviation of approximately 1.2℃. Comparing curves M1 and M2, it is clear that the technical solution of this embodiment can effectively improve the problem of uneven temperature distribution by changing the cross-sectional area of ​​the dielectric vias at different positions.

[0093] In this embodiment, by providing heat dissipation bumps on the side of the dielectric layer away from the substrate and by providing dielectric vias in the dielectric layer, with conductive connectors within the dielectric vias, heat generated by the semiconductor device can be dissipated through the first electrode, the conductive connectors in the dielectric vias, and the heat dissipation bumps. Furthermore, by changing the cross-sectional area of ​​the dielectric vias at different locations, the heat dissipation uniformity of the semiconductor device can be effectively improved. The following, in conjunction with the accompanying drawings, provides a detailed description of various implementation methods of the dielectric vias in this embodiment.

[0094] In some embodiments of this application, such as Figure 10 As shown, Figure 10This is another top view schematic diagram of the semiconductor device provided in an embodiment of this application. The first electrodes 11, second electrodes 12, and control electrodes 13 in the semiconductor device can be arranged along a first direction F1. The first direction F1 is perpendicular to the thickness direction of the substrate 10. The dielectric vias T in the dielectric layer are distributed along the first direction F1, and the cross-sectional area of ​​the dielectric vias T gradually decreases along the direction from the center to the edge of each first electrode 11 in the first direction F1. During the operation of the semiconductor device, heat is mainly concentrated at the center of each first electrode 11. Setting the cross-sectional area of ​​each dielectric via T to gradually decrease along the direction from the center to the edge of each first electrode 11 in the first direction F1 ensures higher heat dissipation efficiency at locations with concentrated heat sources, resulting in better heat dissipation uniformity of the semiconductor device. In one possible implementation, the ratio of the cross-sectional area of ​​the dielectric via T to the area of ​​the corresponding connected first electrode 11 gradually decreases along the direction from the center to the edge of each first electrode 11 in the first direction F1. In a specific configuration, the areas of each first electrode 11 in the semiconductor device can be substantially equal, or the areas of different first electrodes 11 in the semiconductor device can be different, depending on actual needs. In a specific configuration, each first electrode 11 and each second electrode 12 can be arranged alternately. Each control electrode 13 can be located between adjacent first and second electrodes.

[0095] In one possible implementation, refer to Figure 10The semiconductor device may include a cell 100m, in which a plurality of first electrodes 11, a plurality of second electrodes 12, and a plurality of control electrodes 13 are disposed. Furthermore, the cell 100m may also include a first connecting portion 191 and a second connecting portion 192, wherein each control electrode 13 is interconnected through the first connecting portion 191, and each second electrode 12 is interconnected through the second connecting portion 192. Thus, each second electrode 12 and each control electrode 13 in the cell 100m can form an interdigital structure. The difference between the maximum and minimum values ​​of the first width (or second width) of the dielectric via T is greater than or equal to (n-1)*d micrometers, where n is the number of control electrodes 13 in the semiconductor device, and d is a coefficient greater than or equal to 0.5. Moreover, the first width of the dielectric via T is less than the width of the corresponding connected first electrode 11 along the second direction F2, and the second width of the dielectric via T is less than the width of the corresponding connected first electrode 11 along the first direction F1. Wherein, the first width is the width of the dielectric via T along the second direction F2, and the second width is the width of the dielectric via T along the first direction F1. Along the direction from the center to the edge of the cell 100m in the first direction F1, the cross-sectional area of ​​the dielectric via T can gradually decrease. When a semiconductor device includes a single cell 100m, the heat source is mainly concentrated at the center of the cell 100m. Setting the cross-sectional area of ​​the dielectric via T to gradually decrease along the direction from the center to the edge of the cell 100m in the first direction F1 can improve the heat dissipation uniformity of the semiconductor device.

[0096] In another possible implementation, such as Figure 11 As shown, Figure 11This is another top view schematic diagram of a semiconductor device provided in an embodiment of this application. The semiconductor device may include a plurality of cells 100m arranged along a first direction F1. Each cell 100m is provided with a plurality of first electrodes 11, a plurality of second electrodes 12, a plurality of control electrodes 13, a first connection portion 191, and a second connection portion 192. The control electrodes 13 in the cells 100m can be interconnected through the first connection portion 191, and the second electrodes 12 in the cells 100m can be interconnected through the second connection portion 192. In each cell 100m, the difference between the maximum and minimum values ​​of the first width (or second width) of the dielectric via T is greater than or equal to (n-1)*d micrometers, where n is the number of control electrodes 13 in the semiconductor device, and d is a coefficient greater than or equal to 0.5. Furthermore, the first width of the dielectric via T is less than the width of the corresponding connected first electrode 11 along the second direction F2, and the second width of the dielectric via T is less than the width of the corresponding connected first electrode 11 along the first direction F1. Wherein, the first width is the width of the dielectric via T along the second direction F2, and the second width is the width of the dielectric via T along the first direction F1. The cross-sectional area of ​​the dielectric via T can gradually decrease along the direction from the center to the edge of each cell 100m in the semiconductor device along the first direction F1. In some cases, the control electrodes 13 in the cell 100m are evenly spaced, and the distance between adjacent cells 100m is small. For example, the distance between adjacent cells 100m can be comparable to the distance between adjacent control electrodes 13 in the cell 100m. The heat source is mainly concentrated at the center of each cell 100m in the semiconductor device. The cross-sectional area of ​​the dielectric via T gradually decreases along the direction from the center to the edge of each cell 100m in the first direction, which can improve the heat dissipation uniformity of the semiconductor device.

[0097] In another possible implementation, such as Figure 12 and Figure 13 As shown, Figure 12 and Figure 13 These are another top view structural schematic diagrams of the semiconductor device provided in the embodiments of this application. Figure 11 Based on the structure shown, at least two adjacent dielectric vias T with equal cross-sectional areas exist in the dielectric layer along the first direction F1. Figure 12 and Figure 13 In the diagram, the values ​​within the dashed boxes represent the size relationship of the cross-sectional areas; larger values ​​indicate larger cross-sectional areas, while equal values ​​indicate that the cross-sectional areas are approximately the same. For example, in... Figure 12 In the case of two adjacent medium through-holes T, the cross-sectional areas are approximately equal. For example, in... Figure 13In this embodiment, there exist two adjacent medium through-holes T with substantially equal cross-sectional areas, and three adjacent medium through-holes T with substantially equal cross-sectional areas. Of course, in some cases, there may also be four or more adjacent medium through-holes T with substantially equal cross-sectional areas, which can be set according to the actual situation; examples will not be provided here. It is understood that in this embodiment, "conforming cross-sectional areas" means that the cross-sectional areas of two medium through-holes are equal within a certain error range. For example, this error range can be less than or equal to 5%, meaning the difference in cross-sectional areas between the two medium through-holes is less than or equal to 5%.

[0098] In other embodiments of this application, such as Figure 14 As shown, Figure 14This is another top view schematic diagram of a semiconductor device provided in an embodiment of this application. The semiconductor device may include a plurality of cells 100m arranged along a first direction F1. Each cell 100m is provided with a plurality of first electrodes 11, a plurality of second electrodes 12, a plurality of control electrodes 13, a first connection portion 191, and a second connection portion 192. The control electrodes 13 in the cells 100m are interconnected through the first connection portion 191, and the plurality of second electrodes 12 in the cells 100m are interconnected through the second connection portion 192. In each cell 100m of the semiconductor device, the difference between the maximum and minimum values ​​of the first width (or second width) of the dielectric via T is greater than or equal to (n-1)*d micrometers, where n is the number of control electrodes 13 in the semiconductor device, and d is a coefficient greater than or equal to 0.5. Furthermore, the first width of the dielectric via T is less than the width of the corresponding connected first electrode 11 along the second direction F2, and the second width of the dielectric via T is less than the width of the corresponding connected first electrode 11 along the first direction F1. Wherein, the first width is the width of the dielectric via T along the second direction F2, and the second width is the width of the dielectric via T along the first direction F1. The cross-sectional area of ​​each dielectric via T in each cell 100m is equal. Along the direction from the center to the edge of each cell 100m in the first direction F1, the cross-sectional area of ​​the dielectric via T in each cell 100m gradually decreases. In some cases, the distance between adjacent cells 100m can be greater than the distance between adjacent control electrodes 13 in the cell 100m, or it can be comparable to the distance between adjacent control electrodes 13 in the cell 100m. The gradual decrease in the cross-sectional area of ​​the dielectric via T in each cell 100m along the direction from the center to the edge of the first direction F1 in the semiconductor device can result in higher heat dissipation efficiency at the center of each cell 100m in the semiconductor device, thereby improving the overall heat dissipation uniformity of the semiconductor device. It is understood that, in the embodiments of this application, equal cross-sectional areas means that the cross-sectional areas of the two medium through holes are equal within a certain error range. For example, the error range can be less than or equal to 5%, that is, the difference in cross-sectional areas of the two medium through holes is less than or equal to 5%.

[0099] In other embodiments of this application, such as Figure 15 As shown, Figure 15This is another top view schematic diagram of a semiconductor device provided in an embodiment of this application. The semiconductor device may include a plurality of cells 100m arranged along a first direction F1. Each cell 100m is provided with a plurality of first electrodes 11, a plurality of second electrodes 12, and a plurality of control electrodes 13 arranged along the first direction F1; wherein, the first direction F1 is perpendicular to the thickness direction of the substrate 10. Each cell 100m may further include: a first connection portion 191 and a second connection portion 192. Each control electrode 13 in the cell 100m can be interconnected through the first connection portion 191, and each second electrode 12 in the cell 100m can be interconnected through the second connection portion 192. In each cell 100m, the difference between the maximum and minimum values ​​of the first width (or second width) of the dielectric via T is greater than or equal to (n-1)*d micrometers, where n is the number of control electrodes 13 in the semiconductor device, and d is a coefficient greater than or equal to 0.5. Furthermore, the first width of the dielectric via T is smaller than the width of the corresponding connected first electrode 11 along the second direction F2, and the second width of the dielectric via T is smaller than the width of the corresponding connected first electrode 11 along the first direction F1. The first width is the width of the dielectric via T along the second direction F2, and the second width is the width of the dielectric via T along the first direction F1. In each cell 100m, the dielectric vias T are distributed along the first direction F1, and the cross-sectional area of ​​the dielectric via T gradually decreases along the direction from the center to the edge of the cell 100m in the first direction F1. In some cases, the distance between adjacent cells 100m is large, and the heat source is mainly concentrated at the center of the cell 100m. Therefore, setting the cross-sectional area of ​​the dielectric via T at the center of each cell 100m to be larger can improve the heat dissipation uniformity of the semiconductor device.

[0100] In one possible implementation, such as Figure 16 As shown, Figure 16 This is another top view schematic diagram of the semiconductor device provided in the embodiments of this application. Figure 15Based on the structure shown, along the direction from the center to the edge in the first direction F1 of each cell 100m in the semiconductor device, the cross-sectional area of ​​the dielectric via T at the center of each cell 100m gradually decreases. In some cases, the distance between adjacent cells 100m is large, and the heat source is mainly concentrated at the center of each cell 100m, as well as at the center of the entire semiconductor device. Setting the cross-sectional area of ​​the dielectric via T at the center of each cell 100m to be larger, and setting the cross-sectional area of ​​the dielectric via T in the cell 100m located at the center of each cell 100m in the semiconductor device to be larger, can further improve the heat dissipation uniformity of the semiconductor device. In specific settings, the cross-sectional area of ​​a dielectric via T in a cell 100m near the center of the semiconductor device can be larger than the cross-sectional area of ​​the dielectric via T at the corresponding position in a cell 100m near the edge of the semiconductor device. For example, in Figure 15 In the second cell 100m, the cross-sectional area of ​​the first medium through hole T is greater than the cross-sectional area of ​​the first medium through hole T in the first cell 100m.

[0101] The above describes various implementation methods of the dielectric via in the embodiments of this application. In specific settings, the cross-sectional area of ​​the dielectric via can be reasonably set according to the specific structure of the semiconductor device and the location of the heat source. Examples will not be given here.

[0102] Based on the same technical concept, embodiments of this application also provide a method for fabricating a semiconductor device. Figure 17 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Figures 18 to 21 The accompanying drawings are schematic diagrams illustrating the structural steps of the fabrication method provided in the embodiments of this application. The fabrication method of the semiconductor device provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0103] like Figure 17 As shown, the method for fabricating a semiconductor device provided in this application embodiment may include:

[0104] S201 Figure 18 (2) is Figure 18 The top view shown in (1) is a cross-sectional schematic diagram at the dashed line DD', referencing... Figure 18A plurality of first electrodes 11, a plurality of second electrodes 12, and a plurality of control electrodes 13 are formed on the substrate 10. In a specific implementation, insulating material may be deposited in the gaps between each of the first electrodes 11, each of the second electrodes 12, and each of the control electrodes 13 to form an insulating layer 17 for insulating the first electrodes 11, the second electrodes 12, and the control electrodes 13 from each other. Furthermore, prior to step S201, an epitaxial layer 16 may be formed on the substrate 10. Exemplarily, the epitaxial layer 16 may specifically include a channel layer, a barrier layer, or other film layers, and the specific structure of the epitaxial layer 16 may be configured accordingly based on the type of semiconductor device.

[0105] S202, Figure 19 (2) is Figure 19 The top view shown in (1) is a cross-sectional schematic diagram at the dashed line EE', referencing... Figure 19 A dielectric layer 14 is formed on each of the first electrodes 11, each of the second electrodes 12, and each of the control electrodes 13, and a plurality of dielectric vias T are formed in the dielectric layer 14. The projection of the dielectric vias T in the thickness direction of the substrate 10 lies within the projection range of the first electrodes 11. The plurality of dielectric vias T in the dielectric layer 14 may include a first dielectric via T1 and a second dielectric via T2, wherein the cross-sectional area of ​​the first dielectric via T1 is larger than the cross-sectional area of ​​the second dielectric via T2; wherein the cross-sectional area is the cross-sectional area of ​​the dielectric via T along the direction perpendicular to the thickness of the substrate 10.

[0106] Figure 20 (2) is Figure 20 The top view shown in (1) is a cross-sectional view at the dashed line FF', referencing... Figure 20 In step S202 above, forming multiple dielectric vias in the dielectric layer can specifically include:

[0107] A buffer layer 18 is formed on the dielectric layer 14, and the buffer layer 18 is patterned to form openings U in the buffer layer 18. For example, the buffer layer 18 can be made of an organic material such as polyimide (PI), and the thickness of the buffer layer 18 can be greater than 5 micrometers. Then, holes are drilled in the region of the openings U in the dielectric layer 14, and conductive materials are filled into the formed holes. For example, metal materials such as copper, tin, or gold can be filled into the formed holes to form dielectric vias T in the dielectric layer 14 and conductive connectors disposed in the dielectric vias T. Thus, the projection of each dielectric via T onto the substrate 10 can be located within the projection range of the openings U onto the substrate 10, so that the subsequently formed heat dissipation bumps can be connected to the conductive connectors in the dielectric vias T through the openings U. Furthermore, the projection of the openings U onto the substrate 10 is smaller than the area of ​​the heat dissipation bumps to be formed, so that a portion of the subsequently formed heat dissipation bumps is embedded in the openings U, and the heat dissipation bumps 15 engage with the edges of the openings U.

[0108] S203, Figure 21 (2) is Figure 21 The top view shown in (1) is a cross-sectional view at the dashed line KK'. To clearly illustrate the location of the heat dissipation bump, Figure 21 Some component designations have been omitted; refer to Figure 21 A heat dissipation bump 15 is formed on the dielectric layer 14. Each dielectric via T has a conductive connector, allowing the heat dissipation bump 15 to be electrically connected to the first electrode 11 via the conductive connector. The heat dissipation bump 15 is insulated from the second electrode 12 and the control electrode 13 via the dielectric layer 14. The thermal conductivity of the heat dissipation bump 15 is greater than that of the substrate 10. In one possible implementation, the ratio of the thermal conductivity of the heat dissipation bump 15 to that of the substrate 10 can be greater than 1.05, indicating that the heat dissipation bump 15 has a high thermal conductivity and good heat dissipation effect. For example, the thermal conductivity of the heat dissipation bump 15 can be greater than 50 W / (m·K). The heat dissipation bump 15 can be made of thermally and electrically conductive materials, such as copper, tin, or gold.

[0109] Furthermore, the bottom of the heat dissipation bump 15 is embedded in the opening U of the buffer layer 18, and the edge of the heat dissipation bump 15 overlaps the surface of the buffer layer 18 on the side away from the substrate 10. In this way, the buffer layer 18 can support and reinforce the heat dissipation bump 15, preventing the heat dissipation bump 15 from detaching from the dielectric through hole T under the action of high temperature, high stress, etc., thereby improving the structural stability of the heat dissipation bump 15.

[0110] In one possible implementation, the semiconductor device includes an active region, and in the thickness direction of the substrate, the projections of each first electrode and the projection of the active region overlap. In step S203 above, continuing with... Figure 21 The aforementioned formation of heat dissipation bumps 15 on the dielectric layer 14 can specifically include: forming heat dissipation bumps 15 at positions corresponding to the active region A, such that the projection of the heat dissipation bumps 15 in the thickness direction of the substrate 10 overlaps with the active region A. When the semiconductor device is operating, the heat source is mainly concentrated in the region between the first electrode 11 and the second electrode 12. By placing the heat dissipation bumps 15 in the active region A, the heat generated by the semiconductor device can be directly dissipated through the first electrode 11, the conductive connectors in the dielectric via T, and the heat dissipation bumps 15, thereby improving the heat dissipation efficiency of the semiconductor device.

[0111] In the semiconductor device fabrication method provided in this application embodiment, a dielectric via T is formed in the dielectric layer 14, and a heat dissipation bump 15 is formed on the dielectric layer 14. The heat dissipation bump 15 can be electrically connected to the first electrode 11 through a conductive connector in the dielectric via T. Furthermore, the thermal conductivity of the heat dissipation bump 15 is greater than that of the substrate 10, i.e., the heat dissipation bump 15 has a higher thermal conductivity. Thus, the heat generated by the semiconductor device during operation can be dissipated through the first electrode 11, the conductive connector in the dielectric via T, and the heat dissipation bump 15. Moreover, the plurality of dielectric vias T in the dielectric layer 14 may include a first dielectric via T1 and a second dielectric via T2, wherein the cross-sectional area of ​​the first dielectric via T1 is greater than the cross-sectional area of ​​the second dielectric via T2. The heat generated by the semiconductor device during operation is dissipated through the first electrode 11, the conductive connector in the dielectric via T, and the heat dissipation bump 15. The heat dissipation capacity of the semiconductor device is related to the contact area between the first electrode 11 and the conductive connector, that is, the heat dissipation capacity of the semiconductor device is related to the cross-sectional area of ​​the dielectric via T. The larger the cross-sectional area of ​​the dielectric via T, the better the heat dissipation effect at that location. The first dielectric via T1 can be placed at a location where heat dissipation of the semiconductor device is relatively concentrated, thereby improving the heat dissipation uniformity of the semiconductor device, and thus improving the output power and reliability of the semiconductor device. In addition, the structure of the semiconductor device in this embodiment has low requirements for processing equipment, is less difficult to manufacture, and has high mass production capability.

[0112] The technical solution of this application embodiment can effectively improve the problem of uneven temperature distribution by changing the cross-sectional area of ​​the medium through hole T at different locations. It is understood that in this application embodiment, the difference between the cross-sectional areas of the first medium through hole T1 and the second medium through hole T2 is greater than the error range of the manufacturing process. For example, the difference between the cross-sectional areas of the first medium through hole T1 and the second medium through hole T2 can be greater than 5%.

[0113] Reference Figure 19In some embodiments of this application, the first electrodes 11 in the semiconductor device can be arranged along a first direction F1, which is perpendicular to the thickness direction of the substrate 10. In step S202 above, the distance between the first dielectric via T1 and the center of each first electrode 11 in the semiconductor device along the first direction F1 can be smaller than the distance between the second dielectric via T2 and the center of each first electrode 11 in the semiconductor device along the first direction F1. That is, the first dielectric via T1 is closer to the center of each first electrode 11 in the semiconductor device along the first direction F1 than the second dielectric via T2. Among the first electrodes 11 arranged along the first direction F1, the distance between the first first electrode 11 and the center is equal to the distance between the last first electrode 11 and the center. During the operation of the semiconductor device, heat is more concentrated at the center of each first electrode 11 in the semiconductor device. Therefore, setting a larger cross-sectional area of ​​the dielectric via T near the center of each first electrode 11 along the first direction F1 can improve the heat dissipation uniformity of the semiconductor device, thereby improving the output power and reliability of the semiconductor device.

[0114] Of course, in some cases, the distance between the first dielectric via T1 and the center of each first electrode 11 in the semiconductor device along the first direction F1 can also be equal to the distance between the second dielectric via T2 and the center of each first electrode 11 in the semiconductor device along the first direction F1. In specific configurations, the positions of the first dielectric via T1 and the second dielectric via T2 can be reasonably set according to the heat dissipation requirements of the semiconductor device.

[0115] Based on the same technical concept, this application also provides a power amplifier, see reference. Figure 6 The power amplifier provided in this application embodiment may include any of the aforementioned semiconductor devices 100 and a circuit board 200. The semiconductor device 100 can be electrically connected to the circuit board 200 via a heat dissipation bump 15, meaning the semiconductor device 100 can be flip-chip mounted on the circuit board 200. In a specific configuration, a plastic encapsulation layer (not shown in the figure) may also be wrapped around the side of the semiconductor device 100 facing away from the circuit board 200. Since the plastic encapsulation layer is generally quite thick and has very low thermal conductivity (<1W / (m*K)), its thermal conductivity is very poor. In this application embodiment, by flip-chip mounting the semiconductor device 100 onto the circuit board 200, the circuit board 200 dissipates heat more easily than the plastic encapsulation layer, providing a better heat dissipation path for the semiconductor device 100. The heat generated by the semiconductor device 100 can be quickly dissipated through the heat dissipation bump 15 and the circuit board 200, further improving the heat dissipation efficiency of the semiconductor device 100. Because the semiconductor device 100 in this application embodiment has high output power and reliability, the power amplifier including any of the aforementioned semiconductor devices 100 also has good performance and reliability.

[0116] Based on the same technical concept, this application also provides an electronic device, which may include the aforementioned power amplifier and a housing, wherein the power amplifier may be located within the housing. Because the aforementioned power amplifier has good performance and reliability, the electronic device including the aforementioned power amplifier also has good performance and reliability.

[0117] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0118] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate, a plurality of first electrodes, a plurality of second electrodes, a plurality of control electrodes, a dielectric layer, and a heat dissipation bump; wherein the thermal conductivity of the heat dissipation bump is greater than the thermal conductivity of the substrate; the plurality of first electrodes, the plurality of second electrodes, and the plurality of control electrodes are located between the substrate and the dielectric layer, and the heat dissipation bump is located on the side of the dielectric layer away from the substrate; the dielectric layer comprises a plurality of dielectric vias, each of the plurality of dielectric vias is provided with a conductive connecting piece, the heat dissipation bump is electrically connected with the first electrode through the conductive connecting piece, the heat dissipation bump is insulated from the second electrode and the control electrode through the dielectric layer, and the projection of the dielectric via in the thickness direction of the substrate is located within the projection of the first electrode; the plurality of dielectric vias comprises first dielectric vias and second dielectric vias, the cross-sectional area of the first dielectric via is greater than the cross-sectional area of the second dielectric via; wherein the cross-sectional area is the cross-sectional area of the dielectric via in the direction perpendicular to the thickness direction of the substrate.

2. The semiconductor device of claim 1, wherein, The semiconductor device comprises an active region, and the projection of the plurality of first electrodes and the projection of the active region have an overlapping region in the thickness direction of the substrate, and the projection of the heat dissipation bump and the projection of the active region have an overlapping region.

3. The semiconductor device according to claim 1 or 2, wherein The ratio of the thermal conductivity of the heat dissipation bump to the thermal conductivity of the substrate is greater than 1.

05.

4. The semiconductor device according to any one of claims 1 to 3, wherein The thermal conductivity of the heat dissipation bump is greater than 50 W / (m·K).

5. The semiconductor device according to any one of claims 1 to 4, wherein The semiconductor device further comprises a buffer layer located on the side of the dielectric layer away from the substrate; the buffer layer is provided with an opening at a position corresponding to the heat dissipation bump; in the thickness direction of the substrate, the projection of the dielectric via is located within the projection of the opening, and the projection of the heat dissipation bump covers the projection of the opening; a part of the heat dissipation bump is embedded in the opening, and the edge of the heat dissipation bump overlaps the surface of the side of the buffer layer away from the substrate.

6. The semiconductor device according to any one of claims 1 to 5, wherein The plurality of first electrodes are arranged along a first direction, and the first direction is perpendicular to the thickness direction of the substrate; the distance between the first dielectric via and the center of the plurality of first electrodes in the first direction is less than or equal to the distance between the second dielectric via and the center of the plurality of first electrodes in the first direction; wherein the distance between the first first electrode and the center and the distance between the last first electrode and the center in the plurality of first electrodes arranged along the first direction are equal.

7. The semiconductor device of claim 6, wherein the first and second semiconductor layers are formed of a same material. The plurality of first electrodes, the plurality of second electrodes, and the plurality of control electrodes in the semiconductor device are arranged along the first direction; the first width of the first dielectric via is greater than the first width of the second dielectric via; wherein the first width is the width of the dielectric via in a second direction, the second direction is perpendicular to the thickness direction of the substrate, and the first direction and the second direction are perpendicular to each other.

8. The semiconductor device of claim 7, wherein, A difference between a maximum value and a minimum value of the first width of the dielectric via is greater than or equal to (n-1)*d microns, where n is a number of the control electrodes in the semiconductor device, and d is a coefficient greater than or equal to 0.5; The first width of the dielectric via is less than a width of the first electrode corresponding to the connection in the second direction.

9. The semiconductor device of claim 6, wherein, The plurality of first electrodes, the plurality of second electrodes and the plurality of control electrodes in the semiconductor device are arranged along a first direction; A second width of the first dielectric via is greater than the second width of the second dielectric via, the second width being a width of the dielectric via along the first direction.

10. The semiconductor device according to any one of claims 6 to 8, wherein The plurality of first electrodes, the plurality of second electrodes and the plurality of control electrodes in the semiconductor device are arranged along a first direction; The plurality of dielectric vias in the dielectric layer are distributed along the first direction, and a cross-sectional area of the dielectric via gradually decreases in a direction of a center pointing edge of the plurality of first electrodes in the first direction.

11. The semiconductor device of claim 10, wherein, The cross-sectional area of the dielectric via gradually decreases in a direction of a center pointing edge of the first electrode corresponding to the connection in the first direction.

12. The semiconductor device according to claim 10 or 11, wherein The semiconductor device comprises a cell, and the cell is provided with the plurality of first electrodes, the plurality of second electrodes and the plurality of control electrodes; The cell further comprises a first connection part and a second connection part, the plurality of control electrodes are connected to each other through the first connection part, and the plurality of second electrodes are connected to each other through the second connection part; The cross-sectional area of the dielectric via gradually decreases in a direction of a center pointing edge of the cell in the first direction.

13. The semiconductor device of claim 10, wherein, The semiconductor device comprises a plurality of cells arranged along the first direction, and each of the cells is provided with the plurality of first electrodes, the plurality of second electrodes, the plurality of control electrodes, the first connection part and the second connection part, the plurality of control electrodes in the cell are connected to each other through the first connection part, and the plurality of second electrodes in the cell are connected to each other through the second connection part; The cross-sectional area of the dielectric via gradually decreases in a direction of a center pointing edge of the plurality of cells in the first direction.

14. The semiconductor device of claim 13, wherein, The cross-sectional area of at least two adjacent dielectric vias in the dielectric layer in the first direction is equal.

15. The semiconductor device of claim 10, wherein, The semiconductor device comprises a plurality of cells arranged along the first direction, and each of the cells is provided with the plurality of first electrodes, the plurality of second electrodes, the plurality of control electrodes, the first connection part and the second connection part, the plurality of control electrodes in the cell are connected to each other through the first connection part, and the plurality of second electrodes in the cell are connected to each other through the second connection part; The cross-sectional area of each of the dielectric vias in each of the cells is equal, and the cross-sectional area of the dielectric via in each of the cells gradually decreases in a direction of a center pointing edge of the plurality of cells in the first direction.

16. The semiconductor device according to any one of claims 6 to 8, wherein The semiconductor device comprises a plurality of cells arranged along a first direction, each of the cells being provided with a plurality of the first electrodes, a plurality of the second electrodes and a plurality of the control electrodes arranged along the first direction; Each of the cells further comprises a first connecting portion and a second connecting portion, the plurality of the control electrodes in the cell are connected to each other through the first connecting portion, and the plurality of the second electrodes in the cell are connected to each other through the second connecting portion; In each of the cells, the dielectric vias are distributed along the first direction, and the cross-sectional area of the dielectric vias gradually decreases along a direction from the center of the cell to the edge in the first direction F1.

17. The semiconductor device of claim 16, wherein the first and second semiconductor layers are formed of a same material. The cross-sectional area of the dielectric via at the center of each of the cells gradually decreases along a direction from the center of the cell to the edge in the first direction of the plurality of the cells.

18. The semiconductor device according to any one of claims 1 to 17, wherein The cross-sectional shape of the dielectric via along the direction parallel to the substrate is rectangular, octagonal, circular or elliptical.

19. The semiconductor device according to any one of claims 1 to 18, wherein In the direction perpendicular to the substrate, the projection of the first electrode has one or more projections of the dielectric vias.

20. A method of fabricating a semiconductor device, comprising: Comprising: forming a plurality of first electrodes, a plurality of second electrodes and a plurality of control electrodes on a substrate; forming a dielectric layer on the plurality of first electrodes, the plurality of second electrodes and the plurality of control electrodes, and forming a plurality of dielectric vias in the dielectric layer; wherein in the thickness direction of the substrate, the projection of the dielectric via is located within the projection range of the first electrode; the plurality of dielectric vias comprises first dielectric vias and second dielectric vias, the cross-sectional area of the first dielectric vias is greater than that of the second dielectric vias; wherein the cross-sectional area is the cross-sectional area of the dielectric via along the direction perpendicular to the thickness direction of the substrate; forming a heat dissipation bump on the dielectric layer; each of the plurality of dielectric vias is provided with a conductive connecting piece, the heat dissipation bump is electrically connected to the first electrode through the conductive connecting piece; and the heat dissipation bump is insulated from the second electrode and the control electrode through the dielectric layer; wherein the thermal conductivity of the heat dissipation bump is greater than that of the substrate.

21. The method of claim 20, wherein The semiconductor device comprises an active region, and in the thickness direction of the substrate, the projection of the plurality of first electrodes has an overlapping region with the projection of the active region; forming a heat dissipation bump on the dielectric layer, specifically comprising: forming the heat dissipation bump at a position corresponding to the active region, so that the projection of the heat dissipation bump in the thickness direction of the substrate has an overlapping region with the active region.

22. A power amplifier, comprising: Comprising: the semiconductor device according to any one of claims 1-19, and a circuit board; the semiconductor device is electrically connected to the circuit board through the heat dissipation bump.

23. An electronic device, comprising: Comprising: the power amplifier according to claim 22, and a housing; the power amplifier is located in the housing.

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