Low-noise InP HEMT device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor device preparation, in particular to a low-noise InP HEMT device and a preparation method thereof. The buffer layer, the channel layer and the barrier layer are sequentially stacked on the substrate; a heavily doped cap layer disposed on the barrier layer; the source-drain metal electrode is arranged on the heavily doped cap layer; and a gate structure; the gate structure comprises a gate groove, a gate lower layer Pt metal and a gate upper layer metal, the gate lower layer Pt metal and the gate upper layer metal are arranged in the gate groove, the gate groove penetrates through the heavily doped cap layer and extends into the barrier layer, and the gate lower layer Pt metal is in contact with the barrier layer and is diffused downwards to form a Pt buried gate embedded in the barrier layer. And the thickness of the Pt buried gate is a depth interval which enables the reverse leakage of the gate of the InP HEMT device to be in a minimum value. The InP HEMT device has an ultra-low noise coefficient and can detect and amplify extremely weak signals, so that the receiving sensitivity of a communication system and the detection capability of deep space detection and scientific instruments are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication technology, and in particular to a low-noise InP HEMT device and its fabrication method. Background Technology

[0002] Indium phosphide high electron mobility transistors (InP HEMTs) have become core components in modern cutting-edge communication, deep space exploration, and radio astronomy systems due to their superior low-noise performance in the millimeter-wave band. The noise figure of a system directly determines its ability to receive weak signals, and the gate leakage current of the device is a key factor affecting noise characteristics. Therefore, effectively suppressing gate reverse leakage current is a core technological challenge in realizing extremely high-sensitivity receiving devices.

[0003] In typical InP HEMT device fabrication processes, gate formation usually involves wet etching of the InAlAs barrier layer. However, during epitaxial growth, InAlAs materials tend to form microscopically non-uniform regions rich in indium (In) and aluminum (Al), and these two components exhibit significantly different etching rates in the wet etching solution. This leads to microscopic defects and roughness degradation on the etched semiconductor surface. These surface defects can become channels for gate leakage, significantly increasing the device's noise figure.

[0004] To address the problem of gate trench interface defects, traditional technical solutions such as Figure 2 As shown, the epitaxial structure of the material was optimized, mainly by introducing an InP etching stop layer between the heavily doped InGaAs cap layer and the InAlAs barrier layer. The purpose of this layer is to take advantage of the different selectivity of InP and InAlAs in the etchant, effectively slowing down or stopping the etching when the gate trench reaches the InP layer, thereby obtaining a smoother gate interface with fewer defects, in order to reduce the thermionic emission current caused by surface defects.

[0005] However, this traditional approach has inherent contradictions and limitations. To form a good ohmic contact with the InP etched stop layer, conventional processes commonly use titanium in the underlying gate metal. Although Ti adheres well to InP, its low work function, with a small difference between it and InP, results in an insufficient Schottky barrier. This low barrier directly leads to a significant increase in thermionic emission current. Therefore, conventional technology faces a dilemma: introducing the InP etched stop layer aims to reduce thermionic emission current by improving interface quality, but choosing Ti as the gate metal to achieve ohmic contact, due to its low barrier, conversely increases the thermionic emission current. These two mutually canceling effects mean that reverse leakage current cannot be effectively suppressed overall, resulting in mediocre noise characteristics that fail to meet the current cutting-edge applications' pursuit of ultra-low noise performance.

[0006] Therefore, how to significantly increase the Schottky barrier height of the metal-semiconductor contact while ensuring a flat gate trench interface and few defects, thereby fundamentally suppressing leakage mechanisms such as thermionic emission and tunneling, and achieving a leapfrog improvement in device noise characteristics, is a technical problem that urgently needs to be solved by those skilled in the art.

[0007] In view of this, the present invention is proposed. Summary of the Invention

[0008] The purpose of this invention is to provide a low-noise InP HEMT device and its fabrication method, wherein the InP HEMT device has an ultra-low noise figure.

[0009] In a first aspect, the present invention provides a low-noise InP HEMT device, comprising: Substrate; A buffer layer, a channel layer, and a barrier layer are sequentially stacked on the substrate; A heavily doped cap layer disposed on the barrier layer; Source and drain metal electrodes disposed on the heavily doped cap layer; and gate structure; The gate structure includes a gate trench and a lower gate Pt metal layer and an upper gate metal layer disposed within the gate trench. The gate trench penetrates the heavily doped cap layer and extends into the interior of the barrier layer. The lower gate Pt metal layer contacts the barrier layer and diffuses downward to form a buried Pt gate embedded in the barrier layer. The thickness of the buried Pt gate is within the depth range corresponding to the minimum gate reverse leakage current of the InPHEMT device.

[0010] In a preferred embodiment of this technical solution, a Si planar doped layer is further disposed between the channel layer and the barrier layer.

[0011] As a preferred embodiment of this technical solution, the gate top metal is a Ti / Pt / Au or Pt / Ti / Pt / Au multilayer metal structure.

[0012] As a preferred embodiment of this technical solution, the material of the buffer layer is In. x Al 1-x As, where x = 0.52.

[0013] As a preferred embodiment of this technical solution, the channel layer is made of undoped In. y Ga 1-y As, where 0.53≤y≤0.8.

[0014] As a preferred embodiment of this technical solution, the material of the barrier layer is In. x Al 1-x As, where x = 0.52.

[0015] As a preferred embodiment of this technical solution, the material of the heavily doped cap layer is n-type heavily doped In. z Ga 1-z As, where 0.53 ≤ z ≤ 0.65, and the doping concentration is 1E19 cm⁻¹. -3 Up to 3E19 cm -3 .

[0016] Secondly, this invention also discloses a method for fabricating the aforementioned low-noise InP HEMT device, which should also fall within the scope of protection of this invention, specifically including the following steps: S1. A buffer layer, a channel layer, a barrier layer, and a heavily doped cap layer are sequentially grown on a substrate using molecular beam epitaxy or metal-organic chemical vapor deposition techniques. S2. The heavily doped cap layer is isolated by wet etching or dry etching process to form an active region; S3. Form the source and drain on the heavily doped cap layer; S4. A gate trench is formed on the active region, penetrating the heavily doped cap layer and stopping at the barrier layer, and a lower gate Pt metal layer and an upper gate metal layer are sequentially deposited in the gate trench. S5. Anneal the device in an inert gas atmosphere to allow the Pt metal under the gate to diffuse into the barrier layer, forming a buried Pt gate, thus obtaining a low-noise InP HEMT device.

[0017] As a preferred embodiment of this technical solution, an optimal process determination step is included before the fabrication of the low-noise InP HEMT device: A series of test samples of Pt metal under the gate with different initial thicknesses were prepared, and each sample was annealed for different times. The reverse leakage current value was obtained by measuring the current-voltage characteristic curve of the gate of each test sample after annealing. Based on the relationship between the reverse leakage current value and the annealing time and the initial thickness of the Pt metal, the optimal Pt buried gate depth, the optimal annealing time, and the corresponding optimal initial thickness of the Pt metal under the gate are determined to minimize the reverse leakage current. Preferably, a low-noise InP HEMT device is fabricated based on the determined optimal Pt buried gate depth, optimal annealing time, and optimal initial thickness of the Pt metal under the gate.

[0018] As a preferred embodiment of this technical solution, the annealing process is carried out in a nitrogen or argon atmosphere at 200-300 °C for 30 s-20 min.

[0019] The low-noise InP HEMT device of the present invention has at least the following beneficial effects: 1. In the low-noise InP HEMT device of the present invention, the thickness of the buried Pt gate is within the depth range corresponding to the minimum gate reverse leakage current of the InP HEMT device. The present invention minimizes the device's inherent noise by precisely controlling the depth of the buried Pt gate to the "optimal point" that minimizes leakage current. Gate reverse leakage current is one of the main sources of inherent noise in the device, and its magnitude directly determines the noise figure of the device. Therefore, the InP HEMT device of the present invention has an ultra-low noise figure, enabling it to detect and amplify extremely weak signals, thereby greatly improving the receiving sensitivity of communication systems, deep space exploration, and the detection capabilities of scientific instruments. 2. In the low-noise InP HEMT device of this invention, the optimization of the Pt buried gate depth is not simply a matter of "the deeper the better" or "the shallower the better." If the depth is too shallow, interface defects cannot be effectively repaired, resulting in a large thermionic emission current; if the depth is too deep, the barrier region between the gate and the channel becomes too thin, leading to a sharp increase in tunneling current. This invention, through system optimization, finds the optimal balance between the two contradictory goals of suppressing thermionic emission and suppressing tunneling, enabling the device to achieve low leakage current while avoiding performance degradation caused by increased tunneling current. 3. In the low-noise InP HEMT device of this invention, the downward diffusion of the Pt metal under the gate layer forms a novel, higher-quality metal-semiconductor interface. The formation of this new interface repairs the microscopic defects generated on the surface of the InAlAs barrier layer during the wet etching process of the gate trench. Therefore, this invention effectively repairs the gate trench interface defects and improves the long-term stability and reliability of the device. 4. In the low-noise InP HEMT device of the present invention, the Pt buried gate structure allows the effective metal gate to be closer to the two-dimensional electron gas channel. The shortened distance between the gate and the channel enhances the gate control capability, meaning that the channel current can be effectively controlled with a smaller gate voltage change. Therefore, the present invention effectively enhances the gate control capability and improves the device frequency characteristics.

[0020] In summary, this invention transforms the experience-dependent Pt buried gate process into a data-driven, quantitatively controllable manufacturing process, which greatly improves process repeatability and product yield, ensures the consistency and uniformity of device performance in mass production, and lays a solid foundation for the large-scale and commercial production of high-performance InP HEMTs. Attached Figure Description

[0021] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of the low-noise InP HEMT device of the present invention; Figure 2 This is a schematic diagram of the gate metal-semiconductor contact interface of a traditional InP HEMT device. Figure 3 This is a schematic diagram of the gate metal-semiconductor contact interface of the low-noise InP HEMT device of the present invention.

[0023] Explanation of reference numerals in the attached figures: 1: Gate top metal; 2: Gate bottom Pt metal; 3: Pt buried gate; 4: Source / drain metal electrodes; 5: Heavily doped cap layer; 6: Barrier layer; 7: Si planar doped layer; 8: Channel layer; 9: Buffer layer; 10: Substrate; 11: InP etch stop layer; 12: Thermionic emission current; 13: Tunneling current; 14: Ti metal. Detailed Implementation

[0024] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0026] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Furthermore, the terms "installed," "connected," and "linked" should be interpreted broadly; for example, they may refer to a fixed connection, a detachable connection, or an integral connection; they may refer to a mechanical connection or an electrical connection; they may refer to a direct connection or an indirect connection through an intermediate medium; and they may refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0027] Example 1 like Figure 1 As shown, this embodiment provides a low-noise InP HEMT device, including: a substrate 10; a buffer layer 9, a channel layer 8 and a barrier layer 6 sequentially stacked on the substrate 10; A heavily doped cap layer 5 is disposed on the barrier layer 6; Source / drain metal electrodes 4 are disposed on the heavily doped cap layer 5; and gate structure; The gate structure includes a gate trench and a lower gate layer Pt metal 2 and an upper gate layer metal 1 disposed within the gate trench. The gate trench penetrates the heavily doped cap layer 5 and extends into the interior of the barrier layer 6. The lower gate layer Pt metal 2 contacts the barrier layer 6 and diffuses downward to form a buried Pt gate 3 embedded in the barrier layer 6. The thickness of the buried Pt gate 3 is within the depth range corresponding to the minimum gate reverse leakage current of the InP HEMT device.

[0028] In the low-noise InP HEMT device of this embodiment, the thickness of the Pt buried gate 3 is within the depth range corresponding to the minimum gate reverse leakage current of the InP HEMT device. This invention minimizes the device's inherent noise by precisely controlling the depth of the Pt buried gate 3 to the "optimal point" that minimizes leakage current. Gate reverse leakage current is one of the main sources of inherent device noise, and its magnitude directly determines the device's noise figure. Therefore, the InP HEMT device of this invention has an ultra-low noise figure, enabling the detection and amplification of extremely weak signals, thereby greatly improving the receiving sensitivity of communication systems, deep space exploration, and the detection capabilities of scientific instruments.

[0029] Based on the above technical solution, and further preferably, a Si planar doped layer 7 is disposed between the channel layer 8 and the barrier layer 6. The Si planar doped layer 7 provides a high concentration of free electrons to the lower channel layer 8 without introducing scattering centers, thereby forming a high-density two-dimensional electron gas. Therefore, the Si planar doped layer 7 of this invention is the physical basis for achieving all the superior performance characteristics of InP HEMT devices, such as low noise, high frequency, and high gain.

[0030] Based on the above technical solution, and more preferably, the upper metal layer is a Ti / Pt / Au or Pt / Ti / Pt / Au multilayer metal structure.

[0031] Based on the above technical solution, and more preferably, the material of the buffer layer 9 is In. x Al 1-x As, where x = 0.52.

[0032] Based on the above technical solution, and more preferably, the material of the channel layer 8 is undoped In. y Ga 1-y As, where 0.53≤y≤0.8.

[0033] Based on the above technical solution, and more preferably, the material of the barrier layer 6 is In. x Al 1-x As, where x = 0.52.

[0034] Based on the above technical solution, and more preferably, the material of the heavily doped cap layer 5 is n-type heavily doped In. z Ga 1-z As, where 0.53 ≤ z ≤ 0.65, and the doping concentration is 1E19 cm⁻¹. -3 Up to 3E19 cm -3 .

[0035] like Figure 2As shown, the reverse leakage current of InP HEMT devices mainly consists of the thermionic emission current 12 caused by the potential difference between the gate and drain, and the tunneling current 13 caused by the tunneling effect. To reduce semiconductor surface defects after gate trench etching, traditional InP HEMT devices add an InP etching cutoff layer 11 between the heavily doped cap layer 5 and the barrier layer 6 during epitaxial growth to reduce the thermionic emission current 12. However, the lower gate metal uses Ti metal 14. Due to the small difference in work function between Ti and InP, the resulting Schottky barrier is small, which actually increases the thermionic emission current 12. Therefore, traditional InP HEMT devices cannot effectively reduce reverse leakage current overall, resulting in generally poor noise characteristics.

[0036] like Figure 3 As shown, this invention boldly removes the traditional InP etching stop layer 11, returning to the direct InAlAs barrier layer 6 for gate trench etching. This fundamentally avoids the inherent contradiction caused by the forced use of a low work function Ti metal 14 gate due to the introduction of the InP etching stop layer 11. Simultaneously, Pt is used as the lower gate metal, and through an annealing process, it diffuses into the InAlAs barrier layer 6, forming a Pt buried gate 3 structure. The diffusion process of Pt bypasses the original surface defects generated by wet etching, forming a completely new and higher-quality metal-semiconductor interface with fresh InAlAs inside the semiconductor. Furthermore, since the work function of Pt is much greater than that of Ti, and the work function of InAlAs is less than that of InP, according to the Schottky barrier formation principle, a very high Schottky barrier can be formed between Pt and InAlAs. This high Schottky barrier can extremely effectively suppress the hot electron emission current 12.

[0037] The buried gate (Pt) reduces the effective distance between the gate and the channel, enhancing gate control and thus optimizing the transconductance and frequency characteristics of the device. However, burying the gate also reduces the thickness of the barrier region. If the depth is uncontrolled, it can lead to a sharp increase in the tunneling current (I3), which in turn degrades the device performance.

[0038] This invention, through systematic experiments, reveals that the total reverse leakage current exhibits a U-shaped trend, first decreasing and then increasing, with the change in the depth of the Pt buried gate 3. The descending segment of the curve originates from interface repair and the suppression of thermionic current by the high potential barrier; the ascending segment is dominated by the tunneling current 13 caused by excessively deep buried gates. Therefore, the trough of the U-shaped curve, where thermionic current and tunneling current 13 are balanced, represents the point where the total reverse leakage current is minimized. The study also found a quantitative relationship between the maximum diffusion depth of Pt and the initial thickness of the Pt metal 2 under the gate. Therefore, by pre-establishing a model of "Pt thickness - maximum depth - optimal depth," the required initial thickness of the Pt metal 2 under the gate can be precisely designed in reverse.

[0039] In summary, this invention, through the structural innovation of "removing the InP etch stop layer 11 and employing a Pt buried gate 3," successfully resolves the contradiction between interface quality and barrier height in traditional technologies. Simultaneously, by using a quantitative model, its depth is precisely controlled to achieve the optimal performance of "minimum total reverse leakage current." This not only achieves a synergistic improvement in low-noise and high-frequency characteristics of the device but also ensures the repeatability and yield of high-performance device fabrication.

[0040] Example 2 This embodiment discloses the fabrication method of the most preferred low-noise InP HEMT device, specifically including the following steps: First, before fabricating low-noise InP HEMT devices, the optimal process conditions are determined as follows: A series of test samples with identical conditions but different initial thicknesses were prepared, each containing a Pt metal layer 2 beneath the gate. Subsequently, each sample was annealed for different durations (e.g., 30 s–20 min) at 200 ℃–300 ℃ under a nitrogen or argon atmosphere. During annealing, energy is provided to the Pt atoms, enabling them to diffuse into the InAlAs barrier layer 6, forming the buried Pt gate 3. Therefore, the annealing time directly determines the diffusion depth of the Pt atoms, i.e., the buried gate depth. The current-voltage characteristic curves of the gate of each test sample after annealing were measured to obtain the reverse leakage current value, which is used as the most direct parameter to measure the noise performance of the device. In addition, the capacitance-voltage curves of the gate of each test sample after annealing can be measured to assist in the analysis of the characteristics of the Schottky junction, such as barrier height and carrier distribution, and to verify the repair effect of Pt buried gate 3 on the interface. Based on the relationship between the reverse leakage current value and the annealing time and the initial thickness of the Pt metal, the optimal Pt buried gate 3 depth, the optimal annealing time and the corresponding optimal initial thickness of the Pt metal 2 under the gate are determined when the reverse leakage current reaches the minimum value. Specifically, the measured reverse leakage current value was correlated with the annealing time and the initial thickness of the Pt metal for data analysis.

[0041] Among them, the relationship between reverse leakage current and annealing time (i.e., Pt buried gate depth 3) (U-shaped curve) is as follows: as the annealing time increases, the buried gate becomes deeper, Pt diffusion repairs the corrosion defects on the InAlAs surface, forming a high-quality new interface, and the dominance of the hot electron emission current 12 decreases; as the annealing time further increases, the hot electron emission current and tunneling current 13 reach the optimal balance point, at which point the reverse leakage current is the minimum; when the annealing time is too long, the buried gate is too deep, the barrier region between the gate and the channel becomes extremely thin, and the tunneling current 13 increases exponentially and becomes dominant; Regarding the relationship between the buried gate depth (Pt) and annealing time: The capacitance value of the gate Schottky contact at the zero-point voltage is selected, and the following formula is used based on r:

[0042] The width of the space charge region is calculated. Using the unannealed width as a reference, the capacitance of the gate Schottky contact at the zero point is measured after each annealing to calculate the width of the space charge region. The change in the width of the space charge region is the diffusion depth, thereby determining the actual diffusion depth of Pt at different annealing times. Regarding the relationship between the maximum Pt buried depth 3 and the initial thickness of the Pt metal 2 under the gate: Under certain conditions, the maximum diffusion depth that Pt can achieve is proportional to the total amount of Pt metal initially deposited in the gate trench (proportional to the thickness).

[0043] Based on the above quantitative relationships, an analytical model was established to find the optimal annealing time and optimal Pt buried gate 3 depth for each initial Pt thickness from the "U-shaped curve." Among all thicknesses, the scheme that achieves the lowest overall reverse leakage current was selected. Finally, a unique and optimal combination of process parameters was determined: the optimal initial thickness of the Pt metal 2 under the gate and the optimal annealing time.

[0044] Low-noise InP HEMT devices were fabricated based on the determined optimal Pt buried gate 3 depth, optimal annealing time, and optimal initial thickness of the Pt metal 2 under the gate.

[0045] Specifically, the method for fabricating the low-noise InP HEMT device of the present invention includes the following steps: S1. A buffer layer 9, a channel layer 8, a barrier layer 6 and a heavily doped cap layer 5 are sequentially grown on a substrate 10 by molecular beam epitaxy or metal-organic chemical vapor deposition. S2. The heavily doped cap layer 5 is isolated by wet etching or dry etching process to form an active region; S3. Form the source and drain on the heavily doped cap layer 5; S4. A gate trench is formed on the active region, penetrating the heavily doped cap layer 5 and stopping at the barrier layer 6, and a lower gate Pt metal 2 and an upper gate metal 1 are sequentially deposited in the gate trench, wherein the initial thickness of the lower gate Pt metal 2 is the optimal initial thickness of the lower gate Pt metal 2. S5. Under an inert gas atmosphere, the device is annealed using the optimal annealing time determined above, so that the Pt metal 2 under the gate diffuses into the barrier layer 6 to form a Pt buried gate 3. At this time, the thickness of the Pt buried gate 3 is the optimal Pt buried gate 3 depth, and a low-noise InP HEMT device is obtained.

[0046] The above description does not provide detailed explanations of the technical aspects of each layer's patterning and etching. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to create the same structure, those skilled in the art can design methods that are not entirely identical to those described above.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-noise InP HEMT device, characterized in that, The low-noise InP HEMT device comprises: a substrate; a buffer layer, a channel layer and a barrier layer which are sequentially arranged on the substrate; a heavily doped cap layer arranged on the barrier layer; a source-drain metal electrode arranged on the heavily doped cap layer; and a gate structure; the gate structure comprises a gate trench and a lower Pt metal and an upper metal arranged in the gate trench, the gate trench penetrates the heavily doped cap layer and extends to the inside of the barrier layer, wherein the lower Pt metal is in contact with the barrier layer and diffuses downward to form a Pt buried gate embedded in the barrier layer, and the thickness of the Pt buried gate is in a depth interval corresponding to a minimum value of gate reverse leakage current of the InP HEMT device.

2. The low-noise InP HEMT device of claim 1, wherein, A Si planar doping layer is further arranged between the channel layer and the barrier layer.

3. The low-noise InP HEMT device of claim 1, wherein, The upper metal is a Ti / Pt / Au or Pt / Ti / Pt / Au multilayer metal structure.

4. The low-noise InP HEMT device of claim 1, wherein, The material of the buffer layer is In x Al 1-x As, wherein x = 0.

52.

5. The low-noise InP HEMT device of claim 1, wherein, The material of the channel layer is undoped In y Ga 1-y As, where 0.53≤y≤0.

8.

6. The low-noise InP HEMT device of claim 1, wherein, The material of the barrier layer is In x Al 1-x As, wherein x = 0.

52.

7. The low-noise InP HEMT device of claim 1, wherein, The material of the heavily doped cap layer is n-type heavily doped In z Ga 1-z As, where 0.53≤z≤0.65, with a doping concentration of 1E19 cm -3 to 3E19 cm -3 .

8. A method of fabricating a low noise InP HEMT device, characterized by, The method comprises the following steps: S1, sequentially growing a buffer layer, a channel layer, a barrier layer and a heavily doped cap layer on a substrate by molecular beam epitaxy or metal organic chemical vapor deposition technology; S2, isolating the heavily doped cap layer by mesa etching to form an active region; S3, forming a source electrode and a drain electrode on the heavily doped cap layer; S4, forming a gate trench which penetrates the heavily doped cap layer and stops on the barrier layer on the active region, and sequentially depositing a lower Pt metal and an upper metal in the gate trench; S5, annealing the device in an inert gas atmosphere to diffuse the lower Pt metal into the barrier layer to form a Pt buried gate, thereby obtaining a low-noise InP HEMT device.

9. The method of fabricating a low-noise InP HEMT device of claim 8, wherein, Before the preparation of the low-noise InP HEMT device, the method further comprises an optimal process determination step: a series of test samples with different initial thicknesses of the lower Pt metal are prepared, and each sample is annealed for different time; the current-voltage characteristic curve of the gate of each test sample after annealing is measured to obtain a reverse leakage value; the optimal Pt buried gate depth, the optimal annealing time and the corresponding optimal initial thickness of the lower Pt metal corresponding to the minimum value of the reverse leakage are determined according to the relationship between the reverse leakage value, the annealing time and the initial thickness of the Pt metal; Preferably, the low-noise InP HEMT device is prepared according to the determined optimal Pt buried gate depth, the optimal annealing time and the optimal initial thickness of the lower Pt metal.

10. The method of fabricating a low-noise InP HEMT device of claim 8, wherein, The annealing is performed at 200-300 ℃ for 30 s-20 min in a nitrogen or argon atmosphere.

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