GaN-based enhanced high electron mobility transistor

Abstract

The invention discloses a GaN-based enhanced high electron mobility transistor, and relates to the technical field of microelectronic devices. The buffer layer, the channel layer and the barrier layer are sequentially stacked on the substrate; and the p-GaN cap layer is positioned on the barrier layer. The GaN-based enhanced high electron mobility transistor comprises a communication structure, one end of the communication structure is electrically connected with a device source, and the other end of the communication structure is in Schottky contact with a device gate-drain region channel. When the device is in an off state, the potential of the channel below the communication structure is close to the potential of the source electrode, the influence of the high voltage of the drain electrode on the p-GaN layer is avoided, the charge storage and potential floating phenomena of the p-GaN layer are relieved, and therefore the threshold voltage stability of the device is improved. And when the device is reversely conducted, the Schottky junction at the communication structure is conducted under relatively low source-drain voltage, so that the reverse conduction capability of the device is improved, and the reverse conduction voltage drop of the device is prevented from being influenced by negative gate voltage turn-off.

Description

Technical Field

[0001] This invention relates to the field of microelectronic device technology, specifically to a GaN-based enhancement-mode high electron mobility transistor. Background Technology

[0002] GaN has advantages such as large bandgap, high breakdown field strength, and high electron saturation drift velocity, and it also exhibits polarization effects. High electron mobility transistors based on AlGaN / GaN heterojunctions have advantages such as high voltage withstand capability, high switching speed, and high power density, and can replace traditional silicon-based devices in power conversion circuits.

[0003] GaNHEMTs have various structures, among which p-GaN Schottky gate HEMTs, as enhancement-mode devices, offer advantages such as simple driving circuits and a wide gate operating voltage range, making them widely applicable in power electronics. However, the p-GaN gate layer is floating during device turn-on, making it prone to charge storage and potential fluctuations, leading to dynamic threshold voltage drift. This results in increased conduction losses and a higher risk of false turn-on, which needs to be addressed. Furthermore, GaNHEMTs possess reverse conduction capability, allowing for reverse freewheeling in power circuits. However, the reverse conduction voltage drop is typically large and coupled with the gate voltage, which can further increase reverse conduction losses in drive scenarios such as negative gate voltage turn-off, requiring further research and improvement. Summary of the Invention

[0004] The present invention addresses the problem of overly simplistic solutions in existing technologies by providing a significantly different solution. Specifically, the present invention aims to provide a GaN-based enhancement-mode high electron mobility transistor to solve the problem mentioned in the background that reverse conduction losses are easily increased in driving scenarios such as negative gate voltage turn-off.

[0005] A GaN-based enhancement-mode high electron mobility transistor includes a interconnect structure, wherein the interconnect structure is an interconnect metal layer located above a passivation layer and extends from the device source to the device gate-drain region, forming an ohmic contact with the source and a Schottky contact with the gate-drain region.

[0006] Specifically, the GaN-based hybrid gate enhancement HEMT provided by the present invention includes a substrate, a buffer layer, a channel layer, a barrier layer, a p-GaN cap layer, a passivation layer, a source, a drain, a gate, and a connection structure. The buffer layer, the channel layer, and the barrier layer are stacked sequentially on the substrate. The p-GaN cap layer is located on the barrier layer. The source and drain are located on opposite sides of the p-GaN cap layer, and the gate is located on the p-GaN cap layer. The passivation layer covers the source, the p-GaN cap layer, the gate, and the drain. The connection structure is located on the passivation layer.

[0007] In the aforementioned GaN-based hybrid gate enhancement HEMT, the source and drain form ohmic contacts with the barrier layer or channel layer; the gate forms a Schottky contact with the p-GaN cap layer; the interconnect structure forms an electrical connection with the device source and forms a Schottky contact with the channel layer or barrier layer of the gate-drain region.

[0008] In the GaN-based hybrid gate enhanced HEMT described above, the passivation layer can be a single passivation layer or a composite passivation layer composed of multiple dielectric layers.

[0009] In the above-mentioned GaN-based hybrid gate enhanced HEMT, the substrate can be a Si substrate, a sapphire substrate, a GaN substrate, or a SiC substrate.

[0010] The buffer layer can be made of GaN, AlN, or Al. x Ga 1-x N (0 ≤ x ≤ 0.3) or combinations thereof, optionally, the buffer layer doping concentration is 10. 17 -10 19 cm −3 The buffer layer contains C or Fe elements to reduce substrate leakage current and improve device performance. The thickness of the buffer layer is preferably 2-5 μm.

[0011] The channel layer can be made of GaN and has a thickness of 50-500 nm.

[0012] The material of the barrier layer can be Al. y Ga 1-y N (0.12≤y≤0.25), thickness is 10~20nm.

[0013] The thickness of the p-GaN cap layer is preferably 50-120 nm, and the doping concentration is preferably 1-3 × 10⁻⁶. 19 cm −3 .

[0014] The passivation layer can be made of Al2O3, SiO2, SiN, AlN, or HfO2, and has a thickness of 20-500 nm.

[0015] The variations in parameters such as length, thickness, and doping concentration in each region of the aforementioned GaN-based hybrid gate enhanced HEMT depend on different design requirements and fabrication processes. It is worth noting that the key aspect of this invention is that the interconnect structure can shield the p-GaN cap layer from the influence of high drain voltage, mitigating p-GaN charge storage and potential fluctuations, and solving the device threshold voltage drift problem. The interconnect structure also provides reverse conduction capability, reducing reverse conduction voltage drop and losses. It is understood that other structural, material, and parameter variations are possible without departing from the scope of this invention, and different structures, materials, and processes can be combined to achieve the same purpose.

[0016] The present invention also provides a method for preparing the GaN-based hybrid gate enhanced HEMT, comprising the following steps: (1) A buffer layer, a channel layer, a barrier layer and a p-GaN layer are epitaxially grown sequentially on the substrate; (2) A p-GaN cap layer is formed by defining and etching the p-GaN layer using photolithography; (3) Define the source and drain electrode regions on both sides of the p-GaN cap layer by photolithography. Optionally, etch away part or all of the barrier layer in the region, and then prepare the source metal and drain metal. (4) Define the gate metal region by photolithography, and then prepare the gate metal so that the gate metal and the p-GaN cap layer form a Schottky contact; (5) A passivation layer is formed by depositing a medium material on the structure obtained in step (4); (6) Define the source / drain / gate openings by photolithography, and then remove the passivation layer material in the area by etching to expose the source / drain / gate metal; (7) Define the gate-drain opening by photolithography, and then remove the passivation layer material in the region by etching; optionally, partially or completely etch away the barrier layer in the region; optionally, further etch away part of the channel layer in the region. (8) Define the interconnect metal deposition region by photolithography, and then prepare the interconnect metal. The interconnect metal partially or completely covers the source / drain / gate openings and completely covers the gate-drain openings to complete the preparation of GaN-based hybrid gate enhancement HEMT.

[0017] In steps (3)-(4) above, a passivation layer deposition step can be added before the preparation of the gate / source / drain metals, and the passivation layer can be etched away during the preparation of the metal electrodes. The passivation layer material is the same as the passivation layer material prepared in step (5).

[0018] Compared with the prior art, the beneficial effects of the present invention are: (1) The GaN-based enhancement-mode HEMT device structure proposed in this invention can suppress the charge storage and potential fluctuation of the gate p-GaN layer caused by the drain voltage, thereby alleviating the device threshold voltage drift. (2) The GaN-based enhancement-mode HEMT device structure proposed in this invention can improve the reverse conduction capability of the device, so that the reverse conduction voltage drop of the device is no longer affected by the off-state gate voltage, which helps to reduce the reverse conduction loss of the device. (3) The GaN-based enhancement-mode high electron mobility transistor of the present invention includes a connecting structure, one end of which forms an electrical connection with the source of the device, and the other end of which forms a Schottky contact with the gate-drain channel of the device. When the device is off, the channel potential below the connecting structure is close to the source potential, avoiding the influence of high drain voltage on the p-GaN layer, alleviating the charge storage and potential fluctuation phenomenon of the p-GaN layer, thereby improving the stability of the device threshold voltage. When the device is reverse-biased, the Schottky junction at the connecting structure conducts at a lower source-drain voltage, improving the reverse conduction capability of the device and avoiding the influence of negative gate voltage turn-off on the reverse conduction voltage drop of the device. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of a GaN-based hybrid gate enhancement high electron mobility transistor according to the present invention; Figures 2(a) to 2(h) are schematic diagrams of the fabrication steps of a GaN-based hybrid gate enhancement high electron mobility transistor according to the present invention.

[0020] In the figure: 1—substrate, 200—buffer layer, 201—channel layer, 202—barrier layer, 203—p-GaN cap layer, 204—passivation layer, 301—source metal, 302—drain metal, 300—gate metal, 210—source / drain / gate opening, 211—gate-drain opening, 400—connection metal. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This embodiment provides a GaN-based hybrid gate enhancement high electron mobility transistor, the structure of which is as follows: Figure 1 As shown, the system includes a substrate 1, on which a buffer layer 200, a channel layer 201, a barrier layer 202, a p-GaN cap layer 203, and a passivation layer 204 are sequentially stacked. The source metal 301 and the drain metal 302 pass through the passivation layer 204 to form an ohmic contact with the barrier layer 202 or the channel layer 201. The p-GaN cap layer 203 is located between the source metal 301 and the drain metal 302, and the gate metal 300 forms a Schottky contact with the p-GaN cap layer 203. The passivation layer 204 is located above the gate metal 300 and the p-GaN cap layer 203. The connecting metal 400 is located above the passivation layer 204, forms an electrical connection with the source metal 301, and forms a Schottky contact with the gate-drain opening 211 region.

[0023] The preparation steps are shown in Figures 2(a) to 2(h), including: (1) Epitaxial structure preparation: First, a buffer layer 200 is grown on the surface of substrate 1 using MOCVD. The material is GaN, AlN, or Al. x Ga 1-x N or combinations thereof, with a total thickness of 2-5 μm, and a doping concentration of 10 during epitaxy. 19 cm −3 The material is C or Fe doped; subsequently, a channel layer 201 of GaN with a thickness of 50-500 nm is grown on the surface of the buffer layer 200 using MOCVD; subsequently, a barrier layer 202 of Al is grown on the surface of the channel layer 201 using MOCVD. y Ga 1-y N (y=0.15-0.25), with a thickness of 10-20 nm; subsequently, GaN was grown on the surface of the barrier layer 202 using MOCVD, with a thickness of 50-120 nm. During the epitaxial process, Mg was used for p-type doping with a doping concentration of 1-3 × 10⁻⁶. 19 cm −3 A p-GaN cap layer 203 is formed, as shown in Figure 2(a); (2) Patterning of p-GaN cap layer 203: The p-GaN cap layer 203 is selectively etched on the epitaxial structure 2 using photolithography and ICP technology, as shown in Figure 2(b); (3) Source / drain metal preparation: The source / drain metal deposition regions are defined at both ends of the aforementioned structure using photolithography; optionally, part or all of the barrier layer 202 is etched; optionally, part of the channel layer 201 is further etched; the metal is prepared by electron beam evaporation or sputtering, and ohmic contacts are formed by peeling and rapid annealing to obtain source metal 301 and drain metal 302, as shown in Figure 2(c); (4) Gate metal 300 fabrication: The gate metal deposition area is defined on the aforementioned structure using photolithography, and then the metal is fabricated using electron beam evaporation / sputtering and lift-off, as shown in Figure 2(d); (5) Preparation of passivation layer 204: On the aforementioned structure, a medium material is integrally deposited using CVD or ALD technology to form a passivation layer 204 with a thickness of 20-500 nm. The material is Al2O3, SiO2, SiN, AlN, HfO2, etc., as shown in Figure 2(e). (6) Source / drain / gate opening 210: The source / drain / gate opening 210 is defined on the aforementioned structure using photolithography, and the passivation layer 204 is etched using RIE technology to expose the gate metal 300, source metal 301 and drain metal 302, forming the opening 210, as shown in Figure 2(f). (7) Preparation of gate-drain aperture 211: On the aforementioned structure, the gate-drain aperture 211 is defined by photolithography. The aperture 211 is located between the gate metal 300 and the drain metal 302 and does not contact the gate metal 300, the drain metal 302 or the p-GaN cap layer 203. Then, the passivation layer 204 is etched by RIE technology to expose the barrier layer 202 and form the aperture 210. Optionally, the barrier layer 202 is partially or completely etched by ICP technology, as shown in Figure 2(f). Optionally, part of the channel layer 201 is further etched by ICP technology. (8) Fabrication of Connecting Metal 400: The deposited region of connecting metal 400 is defined on the aforementioned structure using photolithography, and then metal is prepared by electron beam evaporation / sputtering and lift-off to form connecting metal 400; connecting metal 400 partially or completely covers the source / drain / gate opening 210, forming an electrical connection with the source metal 301; connecting metal 400 completely covers the gate-drain opening 211, forming a Schottky contact with the underlying barrier layer 202 or channel layer 201, as shown in Figure 2(h). This completes the fabrication of the GaN-based hybrid gate enhancement-mode high electron mobility transistor.

[0024] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A GaN-based enhancement-mode high electron mobility transistor, characterized in that, include: Substrate (1); A buffer layer (200), a channel layer (201) and a barrier layer (202) are sequentially stacked on the substrate (1). p-GaN cap layer (203) located on the barrier layer (202); The source (301) and drain (302) are respectively disposed on both sides of the p-GaN cap layer (203), and the source (301) and drain (302) form an ohmic contact with the barrier layer (202) or the channel layer (201); A gate (300) is disposed on the p-GaN cap layer (203), and the gate (300) forms a Schottky contact with the p-GaN cap layer (203); A passivation layer (204) covering the source (301), drain (302), gate (300) and p-GaN cap layer (203). And a connection structure (400) located on the passivation layer (204), the connection structure (400) forming an electrical connection with the source (301) and forming a Schottky contact with the region between the gate (300) and the drain (302).

2. The GaN-based enhancement-mode high electron mobility transistor according to claim 1, characterized in that: The passivation layer (204) has a source / drain / gate opening (210) and a gate-drain opening (211). The interconnection structure (400) is an interconnect metal layer that partially or completely covers the source / drain / gate opening (210) and forms an electrical connection with the source (301). It also completely covers the gate-drain opening (211) and forms a Schottky contact with the area between the gate (300) and the drain (302).

3. The GaN-based enhancement-mode high electron mobility transistor according to claim 1, characterized in that: The substrate (1) is a Si substrate, a sapphire substrate, a GaN substrate or a SiC substrate.

4. The GaN-based enhancement-mode high electron mobility transistor according to claim 1, characterized in that: The material of the buffer layer (200) is GaN, AlN, or Al. x Ga 1-x N or combinations thereof; Where 0 ≤ x ≤ 0.3; The buffer layer (200) has a doping concentration of 10. 17 -10 19 cm −3 The buffer layer (200) has a thickness of 2-5 μm and contains C or Fe elements to reduce leakage current in the substrate (1).

5. A GaN-based enhancement-mode high electron mobility transistor according to claim 1, characterized in that: The channel layer (201) is made of GaN and has a thickness of 50-500 nm.

6. A GaN-based enhancement-mode high electron mobility transistor according to claim 1, characterized in that: The material of the barrier layer (202) can be Al. y Ga 1-y N, with a thickness of 10-20 nm; Where 0.12≤y≤0.

25.

7. A GaN-based enhancement-mode high electron mobility transistor according to claim 1, characterized in that: The thickness of the p-GaN cap layer (203) ranges from 50 to 120 nm, and the doping concentration ranges from 1 to 3 × 10⁻⁶. 19 cm −3 .

8. A GaN-based enhancement-mode high electron mobility transistor according to claim 1, characterized in that: The passivation layer (204) is made of Al2O3, SiO2, SiN, AlN, or HfO2, and has a thickness ranging from 20 to 500 nm. The passivation layer (204) can be a single passivation layer or a composite passivation layer composed of multiple dielectric layers.

9. A method for fabricating a GaN-based enhancement-mode high electron mobility transistor, comprising the GaN-based enhancement-mode high electron mobility transistor according to any one of claims 1-8, characterized in that, Includes the following steps: (1) A buffer layer (200), a channel layer (201), a barrier layer (202) and a p-GaN layer are epitaxially grown sequentially on a substrate (1); (2) The p-GaN layer is patterned by photolithography and etching to form a p-GaN cap layer (203). (3) A source (301) and a drain (302) are fabricated on both sides of the p-GaN cap layer (203) to form an ohmic contact with the barrier layer (202) or the channel layer (201); (4) A gate (300) is fabricated on the p-GaN cap layer (203) to form a Schottky contact with the p-GaN cap layer (203); (5) Deposit a passivation layer (204) on the structure obtained in step (4); (6) Etch the passivation layer (204) to form a source / drain / gate opening (210) to expose part of the source (301), drain (302) and gate (300) metal; (7) Etch the passivation layer (204) in the region between the gate (300) and the drain (302) to form a gate-drain opening (211). (8) A connecting metal (400) is prepared on the structure obtained in steps (6) and (7) to form a connecting structure, such that the connecting structure partially or completely covers the source / drain / gate opening (210) and is electrically connected to the source (301), and completely covers the gate-drain opening (211) and forms a Schottky contact with the region between the gate (300) and the drain (302).

10. The method for fabricating a GaN-based enhancement-mode high electron mobility transistor according to claim 9, characterized in that: In steps (3) and (4), the electrode metal is prepared by electron beam evaporation or sputtering and then rapidly annealed to form ohmic or Schottky contacts; In step (5), the passivation layer (204) is formed by chemical vapor deposition or atomic layer deposition.

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