Silicon carbide transistor device and preparation method thereof
By intermittently placing injection layers in silicon carbide transistor devices and utilizing Schottky contact integrated diodes, the problems of increased module area and parasitic parameters were solved, resulting in a reduction in on-state voltage drop and an improvement in surge current resistance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-03-31
AI Technical Summary
Existing silicon carbide transistor devices have problems such as increased module area and introduction of additional parasitic parameters in high-power converter applications. Furthermore, they are prone to high-temperature damage at the source bond wire connection and metal melting at the gate bus under large surge currents.
By spacing multiple injection layers in a silicon carbide transistor device and setting two layers with different polarities in each injection layer, a Schottky contact integrated diode is used to reduce the forward voltage drop and integrate the diode inside the device, avoiding the need for an external FRD.
It effectively reduces the on-state voltage drop of the device, avoids the increase in module area and the introduction of additional parasitic parameters, and improves the surge current resistance capability, thus solving the reliability problem of the device under high current.
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Figure CN121772276A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a silicon carbide transistor device and its fabrication method. Background Technology
[0002] The high voltage and high temperature resistance of silicon carbide (SiC) allows it to achieve the same voltage withstand level as silicon-based IGBTs using simple MOSFET devices, while avoiding their high energy consumption and inability to withstand high-frequency operation. High-power converter applications typically require a freewheeling diode (FRD) in the MOSFET switching device to handle reverse current. Traditional silicon-based MOSFETs' body parasitic diodes suffer from poor reverse recovery characteristics due to minority carrier storage effects, resulting in significant switching power consumption and making them unsuitable for this purpose. Related technologies use a fast recovery diode (FRD) connected in reverse parallel across the MOSFET source and drain to suppress parasitic body diode conduction and provide a new freewheeling path. However, external FRDs often increase circuit module area and introduce additional parasitic parameters. Under large surge currents, existing devices often suffer from high-temperature damage at the source bond wire connection and metal melting at the gate bus, leading to unstable on-state voltage drop. Furthermore, damage can occur on the surface of silicon carbide. Summary of the Invention
[0003] The main objective of this application is to provide a silicon carbide transistor device and its fabrication method, so as to at least solve the problems of increased module area and introduction of additional parasitic parameters caused by external diodes in the prior art.
[0004] To achieve the above objectives, according to one aspect of this application, a silicon carbide transistor device is provided, comprising: a substrate including a stacked substrate and an epitaxial layer, the epitaxial layer having a first surface; a plurality of implantation layers, each implantation layer being a region in the epitaxial layer formed by ion implantation of a portion of the first surface; wherein the plurality of implantation layers are spaced apart along a first direction; a plurality of first doped layers, each first doped layer being a region in the epitaxial layer formed by ion implantation or trench filling of a first surface corresponding to one of the implantation layers; wherein each first doped layer includes a first layer and a second layer, the polarity of the trench filling material of the first layer being different from the polarity of the implantation material of the second layer; a gate disposed on the epitaxial layer, the gate having an ohmic contact with the first doped layer and a Schottky contact with a third layer; wherein the third layer is a region on the epitaxial layer that is in contact with the gate and does not belong to the first doped layer. This application provides multiple injection layers spaced apart, and in each injection layer, two layers with different polarities of injection materials are provided. Through Schottky contacts, the on-state voltage drop of the device is reduced. On the other hand, this application integrates diodes inside the device through Schottky contacts, which alleviates the problems of increased module area and introduction of additional parasitic parameters in related technologies.
[0005] Optionally, the first layer and the second layer are spaced apart, with the spacing between the first layer and the second layer being 0.1µm to 0.4µm.
[0006] Optionally, the first layer is disposed in a first trench, the first trench extending from the first surface to the interior of the epitaxial layer, and the depth of the first trench is 0.2 μm to 0.6 μm.
[0007] Optionally, the silicon carbide transistor device further includes:
[0008] The second doped layer is disposed on the first surface extending into the interior of the epitaxial layer and is adjacent to the plurality of implanted layers along the first direction;
[0009] A third doped layer is disposed on the first surface extending into the interior of the epitaxial layer and adjacent to the second doped layer along the first direction; wherein the trench filling material of the second doped layer and the third doped layer is the same as the trench filling material of the first layer; the doping concentration of the third doped layer is less than the doping concentration of the second doped layer.
[0010] To achieve the above objectives, according to another aspect of this application, a method for fabricating a silicon carbide transistor device is provided, comprising:
[0011] A substrate is provided; wherein the substrate comprises a stacked substrate and an epitaxial layer, the epitaxial layer having a first surface;
[0012] Ion implantation is performed on a portion of the first surface of the epitaxial layer to form a plurality of implanted layers spaced apart along a first direction; wherein the plurality of implanted layers are spaced apart along the first direction.
[0013] Ion implantation is performed on the first surface corresponding to each implantation layer to form multiple first doped layers, wherein each first doped layer includes a first layer and a second layer;
[0014] A gate is formed on the epitaxial layer; wherein the gate is in an ohmic contact with the first doped layer and in a Schottky contact with the third layer; the third layer is a region on the epitaxial layer that is in contact with the gate and does not belong to the first doped layer;
[0015] The process involves ion implantation on the first surface corresponding to each implanted layer to form multiple first doped layers, including:
[0016] A second preset material is injected into the first surface corresponding to each injection layer to form a second layer;
[0017] A first preset material is filled into the first surface corresponding to each injection layer through grooves to form a first layer; wherein the first preset material and the second preset material have different polarities.
[0018] Optionally, the step of ion implantation on a portion of the first surface of the epitaxial layer to form a plurality of implanted layers spaced apart along a first direction includes:
[0019] A predetermined metal at a first dose and a first depth is implanted into a portion of the first surface of the epitaxial layer to form a plurality of implanted layers spaced apart along a first direction; wherein the first dose is 1E11 to 9E14 cm-2, the first depth is 0.7um to 0.8um, and the spacing between two consecutive implanted layers is 0.1um to 1.0um.
[0020] Optionally, the first layer is formed by filling the first surface corresponding to each injection layer with a first preset material through trenches, comprising:
[0021] A first etching is performed on the first surface corresponding to each injection layer to form a first trench; wherein the depth of the first trench is 0.2um to 0.6um;
[0022] A first preset material is filled into the first trench to form a first layer; wherein the spacing between the first layer and the second layer is 0.1um to 0.4um.
[0023] Optionally, the method further includes:
[0024] A second etching is performed on a portion of the first surface corresponding to each injection layer to form a second trench; wherein the depth of the second trench is 0.2um to 0.6um, and the second trench is adjacent to the plurality of injection layers along the first direction;
[0025] The second trench is filled with a first preset material to form a second doped layer;
[0026] A third etching is performed on a portion of the first surface corresponding to each injection layer to form a third trench; wherein the depth of the third trench is 0.2um to 0.5um, and the third trench is adjacent to the second trench along the first direction;
[0027] A first preset material is filled into the third trench to form a third doped layer; wherein the doping concentration of the third doped layer is less than the doping concentration of the second doped layer.
[0028] Optionally, forming a gate on the epitaxial layer includes:
[0029] A gate oxide layer and a polysilicon gate are grown on the first surface of the epitaxial layer, and the gate oxide layer and the polysilicon gate are etched to form a gate.
[0030] A dielectric material is deposited on the gate and etched to obtain a dielectric layer; wherein the dielectric material includes silicon dioxide.
[0031] Optionally, the method further includes:
[0032] A source electrode is formed on the dielectric layer in a region corresponding to the plurality of implanted layers, and the source electrode is made in ohmic contact with the first doped layer.
[0033] By applying the technical solution of this application, this application provides multiple injection layers spaced apart, and in each injection layer, two layers with different polarities of injection materials are provided. Through Schottky contacts, the on-state voltage drop of the device is reduced. On the other hand, this application integrates diodes inside the device through Schottky contacts, which alleviates the problems of increased module area and introduction of additional parasitic parameters in related technologies. Attached Figure Description
[0034] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:
[0035] Figure 1 A schematic diagram of the structure of a silicon carbide transistor according to an embodiment of the related art is shown;
[0036] Figure 2 A schematic diagram of the structure of a silicon carbide transistor device provided in an embodiment of this application is shown;
[0037] Figure 3 A schematic diagram of the substrate preparation process provided according to an embodiment of this application is shown;
[0038] Figure 4 A schematic diagram of the injection layer preparation process provided according to an embodiment of this application is shown;
[0039] Figure 5 A schematic diagram of the second layer preparation process provided according to an embodiment of this application is shown;
[0040] Figure 6 A schematic diagram of the first layer preparation process according to an embodiment of this application is shown;
[0041] Figure 7 A schematic diagram of the substrate preparation process provided according to an embodiment of this application is shown;
[0042] Figure 8 A schematic diagram of the JFET layer fabrication process according to an embodiment of this application is shown;
[0043] Figure 9 A schematic diagram of the gate fabrication process provided according to an embodiment of this application is shown;
[0044] Figure 10 A schematic diagram of the fabrication process of the interlayer dielectric layer according to an embodiment of this application is shown;
[0045] Figure 11 A schematic diagram of the drain and source fabrication process according to an embodiment of this application is shown;
[0046] The above figures include the following reference numerals:
[0047] For the embodiments of this application:
[0048] 101, Source; 103, Silicon dioxide layer; 102, Polysilicon layer; 104, Ohmic contact layer; 105, Schottky contact layer; 106, Drain; 107, Substrate; 108, Epitaxial layer; 109, Third doped layer; 110, Second doped layer; 111, Interlayer dielectric layer; 112, Implanted layer; 113, Second layer; 114, First layer; 116, JFET layer;
[0049] For embodiments of the relevant technology:
[0050] 1011, Source electrode of related technology; 1021, Polysilicon gate electrode; 1031, Gate oxide layer; 1041, Ohmic contact; 1061, Drain electrode of related technology; 1071, Substrate of related technology; 1081, Drift region; 1091, JTE; 1101, Main junction; 1111, Interlayer dielectric layer of related technology. Detailed Implementation
[0051] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0052] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.
[0053] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0054] As described in the background section, in related technologies:
[0055] Traditional silicon (Si)-based high-voltage devices have approached their theoretical limits and are unable to meet the high-performance requirements of current power conversion devices. Silicon carbide (SiC), as one of the third-generation wide-bandgap semiconductor materials, has become the focus of research and development both domestically and internationally, and has gradually replaced silicon-based devices in some fields.
[0056] The high voltage and high temperature resistance of silicon carbide (SiC) allows it to achieve the same voltage withstand level as silicon-based IGBTs using simple MOSFET devices, while avoiding their high energy consumption and inability to withstand high-frequency operating conditions. Currently, in the new energy vehicle industry, SiC is used in inverters for driving and controlling motors, on-board chargers, and fast charging piles. Leading photovoltaic inverter companies have adopted SiC power devices to replace silicon devices. In existing technologies, high-power converter applications typically require the addition of a freewheeling diode to the MOS switching device to handle reverse current. Traditional silicon-based MOSFETs' body parasitic diodes suffer from poor reverse recovery characteristics due to minority carrier storage effects, resulting in significant switching power consumption and making them unsuitable for this purpose. Therefore, in practical applications, a fast recovery diode (FRD) is connected in reverse parallel across the MOSFET source and drain to suppress parasitic body diode conduction and provide a new freewheeling path. However, external FRDs often increase the circuit module area and introduce additional parasitic parameters. Under large surge currents, existing devices often suffer from high-temperature damage at the source bond wire connection and metal melting at the gate bus. Based on this, the present invention integrates JBS into the planar MOS to reduce the on-state voltage drop of the transistor and improve its resistance to surge current impact.
[0057] This patent completes PWLL and N + P after injection process + Etching of the main junction, followed by P + Type GaAs filler (filler material can be P) +The process involves first etching with materials such as P-type GaAs, PolySi, and GaN, followed by JTE etching and then filling with P-type GaAs (filler materials can include P-type GaAs, PolySi, GaN, etc.). After completing the front-end processes, thinning and drain processing are performed. When the device is reverse biased, P... + The n-junction depletion layer extends into the channel, pinching off the Schottky barrier and thus suppressing leakage current. During forward conduction, current flows through the lower P-junction of the Schottky contact. + Conductive channels between regions reduce on-state voltage drop. Furthermore, due to P... + The main junction and JTE region are filled with SiC trenches, which reduces ion implantation damage to the SiC surface.
[0058] To address the aforementioned issues, embodiments of this application provide a silicon carbide transistor device, which includes multiple injection layers spaced apart, and two layers with different polarities of injection materials in each injection layer. By using Schottky contacts, the on-state voltage drop of the device is reduced. Furthermore, this application integrates diodes within the device using Schottky contacts, mitigating the problems of increased module area and the introduction of additional parasitic parameters in related technologies.
[0059] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
[0060] Figure 1 This is a schematic diagram of a silicon carbide transistor according to an embodiment of the related technology. The drain 1061 of the related technology is located at... Figure 1 Under substrate 1071, a drift region 1081 is formed on the substrate. A main junction 1101 formed by ion implantation and a junction electrode 1091 formed by ion implantation are formed in the drift region. A gate oxide layer 1031 and a polysilicon gate electrode 1021 are also formed on the drift region. Figure 1 Interlayer dielectric layer 1111 and Figure 1 The source of 1011. Figure 1 The middle gate and the implantation region form an ohmic contact 1041.
[0061] Figures 2 to 11 These are schematic diagrams of the structure and fabrication process of a silicon carbide transistor device according to embodiments of this application. The silicon carbide transistor device includes:
[0062] The substrate includes a stacked substrate 107 and an epitaxial layer 108, the epitaxial layer having a first surface;
[0063] Multiple implanted layers 112, wherein each implanted layer is a region in the epitaxial layer formed by ion implantation of a portion of the first surface; wherein the multiple implanted layers are spaced apart along a first direction;
[0064] Multiple first doped layers, each first doped layer being a region in the epitaxial layer formed by ion implantation or trench filling of a first surface corresponding to an implantation layer; wherein each first doped layer includes a first layer and a second layer, the polarity of the trench filling material of the first layer 114 being different from the polarity of the implantation material of the second layer 113;
[0065] A gate 102 is disposed on the epitaxial layer. The gate is in an ohmic contact with the first doped layer and in a Schottky contact with the third layer. The third layer is a region on the epitaxial layer that is in contact with the gate and does not belong to the first doped layer.
[0066] The first surface can be a surface on the epitaxial layer that does not contact the substrate. For example... Figure 2 As shown, for an N-type silicon carbide device, the substrate is as shown in the figure. The epitaxial layer can be a drift region disposed on the substrate. The implantation layer can be a P-Well layer, and the implanted ions can be aluminum or other metals; this application does not impose specific limitations. Figure 2 As shown, aluminum is implanted into a portion of the first surface of the epitaxial layer, forming three implanted layers. These three implanted layers are arranged at intervals, with the first direction parallel to the first surface. Of course... Figure 2 For illustrative purposes, this application does not limit the specific number of implanted layers. Each implanted layer contains a first doped layer. Specifically, each implanted layer contains a first layer and a second layer. The first layer is filled with a first preset material, which can be P, by trench filling; the second layer is implanted with a second preset material, which can be N, by ion implantation. An ohmic contact is formed between the gate and the first doped layer, forming an ohmic contact layer 104, and a Schottky contact is formed between the gate and layers other than the first doped layer, forming a Schottky contact layer 105. The third layer can be the region in the implanted layer other than the first doped layer. The source 101, the gate oxide layer 103, and the interlayer dielectric layer 111 are disposed on the epitaxial layer, and the drain 106 is disposed below the substrate. This application integrates a junction barrier Schottky diode in a silicon carbide transistor through spaced implanted layers, and reduces the voltage drop when the device is turned on by adjusting the Schottky barrier, thus providing a freewheeling function.
[0067] Optionally, the first layer and the second layer are spaced apart, with the spacing between the first layer and the second layer being 0.1µm to 0.4µm.
[0068] In this application, the first layer and the second layer are separated and connected by a subsequent metal layer, which can also serve as short-circuit protection.
[0069] Optionally, the first layer is disposed in a first trench, the first trench extending from the first surface to the interior of the epitaxial layer, and the depth of the first trench is 0.2 μm to 0.6 μm.
[0070] This application obtains a first trench by etching a first surface, and then obtains a first layer by filling the first trench. The filling process for setting the first layer helps to reduce surface implantation damage to silicon carbide.
[0071] Optionally, the silicon carbide transistor device further includes:
[0072] The second doped layer 110 is disposed on the first surface extending into the interior of the epitaxial layer and is adjacent to the plurality of implanted layers along the first direction;
[0073] The third doped layer 109 is disposed on the first surface extending into the interior of the epitaxial layer and adjacent to the second doped layer along the first direction; wherein the trench filling material of the second doped layer and the third doped layer is the same as the trench filling material of the first layer; the doping concentration of the third doped layer is less than the doping concentration of the second doped layer.
[0074] The second doped layer can have the same composition and fabrication method as the first layer, and is located in a region adjacent to the implanted layer in the first direction. The third doped layer is adjacent to the second doped layer. Both the second and third doped layers are fabricated using a trench filling method.
[0075] To achieve the above objectives, according to another aspect of this application, a method for fabricating a silicon carbide transistor device is provided, comprising:
[0076] A substrate is provided; wherein the substrate comprises a stacked substrate and an epitaxial layer, the epitaxial layer having a first surface;
[0077] Ion implantation is performed on a portion of the first surface of the epitaxial layer to form a plurality of implanted layers spaced apart along a first direction; wherein the plurality of implanted layers are spaced apart along the first direction.
[0078] Ion implantation is performed on the first surface corresponding to each implantation layer to form multiple first doped layers, wherein each first doped layer includes a first layer and a second layer;
[0079] A gate is formed on the epitaxial layer; wherein the gate is in an ohmic contact with the first doped layer and in a Schottky contact with the third layer; the third layer is a region on the epitaxial layer that is in contact with the gate and does not belong to the first doped layer;
[0080] The process involves ion implantation on the first surface corresponding to each implanted layer to form multiple first doped layers, including:
[0081] A second preset material is injected into the first surface corresponding to each injection layer to form a second layer;
[0082] A first preset material is filled into the first surface corresponding to each injection layer through grooves to form a first layer; wherein the first preset material and the second preset material have different polarities.
[0083] Optionally, the step of ion implantation on a portion of the first surface of the epitaxial layer to form a plurality of implanted layers spaced apart along a first direction includes:
[0084] A predetermined metal at a first dose and a first depth is implanted into a portion of the first surface of the epitaxial layer to form a plurality of implanted layers spaced apart along a first direction; wherein the first dose is 1E11 to 9E14 cm. -2 The first depth is 0.7um to 0.8um, and the spacing between two consecutive injection layers is 0.1um to 1.0um.
[0085] Optionally, the first layer is formed by filling the first surface corresponding to each injection layer with a first preset material through trenches, comprising:
[0086] A first etching is performed on the first surface corresponding to each injection layer to form a first trench; wherein the depth of the first trench is 0.2um to 0.6um;
[0087] A first preset material is filled into the first trench to form a first layer; wherein the spacing between the first layer and the second layer is 0.1um to 0.4um.
[0088] Optionally, the method further includes:
[0089] A second etching is performed on a portion of the first surface corresponding to each injection layer to form a second trench; wherein the depth of the second trench is 0.2um to 0.6um, and the second trench is adjacent to the plurality of injection layers along the first direction;
[0090] The second trench is filled with a first preset material to form a second doped layer;
[0091] A third etching is performed on a portion of the first surface corresponding to each injection layer to form a third trench; wherein the depth of the third trench is 0.2um to 0.5um, and the third trench is adjacent to the second trench along the first direction;
[0092] A first preset material is filled into the third trench to form a third doped layer; wherein the doping concentration of the third doped layer is less than the doping concentration of the second doped layer.
[0093] Optionally, forming a gate on the epitaxial layer includes:
[0094] A gate oxide layer and a polysilicon gate are grown on the first surface of the epitaxial layer, and the gate oxide layer and the polysilicon gate are etched to form a gate.
[0095] A dielectric material is deposited on the gate and etched to obtain a dielectric layer; wherein the dielectric material includes silicon dioxide.
[0096] Optionally, the method further includes:
[0097] A source electrode is formed on the dielectric layer in a region corresponding to the plurality of implanted layers, and the source electrode is made in ohmic contact with the first doped layer.
[0098] In this application, a source electrode is provided on the dielectric layer in an active region corresponding to multiple injection layers, that is, on the dielectric layer corresponding to the active region containing multiple injection layers, and the source electrode is connected to the third layer by a Schottky contact.
[0099] By applying the technical solution of this application, this application provides multiple injection layers spaced apart, and in each injection layer, two layers with different polarities of injection materials are provided. Through Schottky contacts, the on-state voltage drop of the device is reduced. On the other hand, this application integrates diodes inside the device through Schottky contacts, which alleviates the problems of increased module area and introduction of additional parasitic parameters in related technologies.
[0100] To enable those skilled in the art to better understand the technical solution of this application, the implementation process of the silicon carbide transistor device of this application will be described in detail below with reference to specific embodiments.
[0101] The technical problems addressed by this solution include:
[0102] 1. When the device is forward-biased, the on-state voltage drop is reduced by adjusting the Schottky barrier;
[0103] 2. No external FRD is required, avoiding an increase in circuit module area and introducing no additional parasitic parameters; in addition, under large surge currents, it avoids device damage at source bond wire connections due to high temperature and metal melting at the gate bus.
[0104] This application involves etching SiC trenches to fill P... + The material processing integrates the JBS diode into the SiC MOSFET, modulating the Schottky barrier to reduce the voltage drop during conduction, thus providing freewheeling and handling large currents. Furthermore, due to P... + The main junction and JTE region employ SiC trench filling technology, which reduces SiC surface implantation damage (P). +For p-type fillers, GaAs, PolySi, and GaN are used; for p-type fillers, GaAs, PolySi, and GaN are also available.
[0105] The fabrication process of the silicon carbide transistor provided in this application includes:
[0106] 1. First, in N + An EPI layer is grown as a drift layer on a SiC substrate (with a resistivity of 0.02 ± 20% Ωcm), as a reference. Figure 3 As shown, the doping concentration is 1E+15~1E+16 cm⁻¹ -3 The thickness varies depending on the product requirements. The thickness of the 1200V MOS EPI layer is 9~11um, and the thickness of the 650V MOS EPI layer is 5~7um. These parameters are for reference only.
[0107] 2. Prepare the PWLL layer (i.e., the implanted layer in this application), such as Figure 4 As shown, the injected element is Al, and the injection dose is 1E11 ~ 9E14 cm⁻¹. -2 The injection depth is 0.7~0.8um, the PWLL length is 0.4~3.0um, and the spacing is 0.1~1.0um. These parameters are for reference only.
[0108] 3. Preparation of N + Layer (i.e., the second layer in this application), such as Figure 5 As shown, the injected element is nitrogen, and the injection dose is 1E13~9E15 cm⁻¹. -2 The injection depth is 0.2~0.6um, and the data is for reference only.
[0109] 4. Preparation of P + Layers (i.e., the first and second doped layers in this application), such as Figure 6 As shown, the first trench is formed by etching silicon carbide, with a trench depth of 0.2~0.6µm and a main junction length of 10~40µm, wherein P + With N + After spacing 0.1~0.4µm, GaAs filling (GaAs, PolySi, GaN, etc. can be used as filler materials) is performed. The filler is p-type doped with a concentration of 1E17~2.0E20 cm⁻¹. -2 The data is for reference only.
[0110] 5. Prepare the JTE layer (i.e., the third doped layer in this application), such as Figure 7 As shown, trenches are formed by etching silicon carbide, with a trench depth of 0.2~0.5µm, followed by GaAs filling (GaAs, PolySi, GaN, etc. can be used as filler materials). The filler is p-type doped with a concentration of 1E17~2.0E20 cm⁻¹. -2The doping concentration of the JTE layer is lower than that of the main junction; the data is for reference only.
[0111] 6. Fabricate JFET layer 116, such as Figure 8 As shown, the implanted element was nitrogen, and the implantation dose was 1.0E+11~9.0E+13 cm⁻¹. -2 The injection depth is 0.8~1.5um, followed by activation of the injection layer. The data is for reference only.
[0112] 7. Growth of gate oxide layer and polysilicon gate, such as Figure 9 As shown, a silicon dioxide layer 103 and a polysilicon layer 102 are sequentially disposed on the epitaxial layer. Specifically, a gate oxide layer and a polysilicon gate are grown and etched. The gate oxide layer has a thickness of 600 Å, and the polysilicon layer has a thickness of 2000-6000 Å, as shown in the figure below.
[0113] 8. Interlayer media, such as Figure 10 As shown, the excess dielectric layer is etched away. The material can be SiO2 or others, with a thickness of 600~1000nm. The data is for reference only, see the figure below.
[0114] 9. Forming a metal drain and source, where N + and P + The contacts are ohmic, commonly made of metals such as Ni, Ti, or other materials; the remaining portion is a Schottky contact. (See...) Figure 11 .
[0115] Compared to traditional SiC MOSFETs, integrating the diode into the SiC MOSFET allows for modulation of the Schottky barrier, reducing the voltage drop during conduction. Furthermore, the JBS can function as a freewheeling diode, eliminating the need for an external FRD and avoiding increased circuit module area. Because P + The main junction and JTE region are filled with SiC trench technology, which reduces the damage caused by SiC surface injection. It should be noted that the above are exemplary examples and do not specifically limit the methods, steps and execution logic provided in this application.
[0116] In the description of this application, it should be understood that if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0117] Furthermore, where the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0118] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0119] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0120] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.
[0121] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0122] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
[0123] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A silicon carbide transistor device, characterized by, The silicon carbide transistor device comprises: a substrate comprising a stacked substrate and an epitaxial layer, the epitaxial layer having a first surface; a plurality of implantation layers, the implantation layers being regions in the epitaxial layer formed by ion implantation on part of the first surface; wherein the plurality of implantation layers are spaced apart along a first direction; a plurality of first doped layers, each of the first doped layers being a region in the epitaxial layer formed by ion implantation or trench filling on a corresponding first surface of one of the implantation layers; wherein each of the first doped layers comprises a first layer and a second layer, the polarity of the trench filling material of the first layer being different from the polarity of the implantation material of the second layer; a gate disposed on the epitaxial layer, the gate and the first doped layer being in ohmic contact, the gate and a third layer being in Schottky contact; wherein the third layer is a region on the epitaxial layer in contact with the gate and not belonging to the first doped layer.
2. The silicon carbide transistor device of claim 1, wherein: the first layer and the second layer are spaced apart, the spacing between the first layer and the second layer being 0.1-0.4 um.
3. The silicon carbide transistor device of claim 1, wherein: the first layer is disposed in a first trench, the first trench extending from the first surface to the interior of the epitaxial layer, the depth of the first trench being 0.2-0.6 um.
4. The silicon carbide transistor device of Claim 1, wherein, The silicon carbide transistor device further comprises: a second doped layer disposed on the first surface extending to the interior of the epitaxial layer, adjacent to the plurality of implantation layers along the first direction; a third doped layer disposed on the first surface extending to the interior of the epitaxial layer, adjacent to the second doped layer along the first direction; wherein the trench filling material of the second doped layer and the third doped layer is the same as the trench filling material of the first layer; the doping concentration of the third doped layer is less than the doping concentration of the second doped layer.
5. A method of fabricating a silicon carbide transistor device, characterized by, The method comprises: providing a substrate; wherein the substrate comprises a stacked substrate and an epitaxial layer, the epitaxial layer having a first surface; ion implantation on part of the first surface of the epitaxial layer to form a plurality of implantation layers spaced apart along a first direction; wherein the plurality of implantation layers are spaced apart along a first direction; ion implantation on a corresponding first surface of each implantation layer to form a plurality of first doped layers, wherein each of the first doped layers comprises a first layer and a second layer; forming a gate on the epitaxial layer; wherein the gate and the first doped layer are in ohmic contact, the gate and a third layer are in Schottky contact; the third layer is a region on the epitaxial layer in contact with the gate and not belonging to the first doped layer; the ion implantation on a corresponding first surface of each implantation layer to form a plurality of first doped layers comprises: ion implantation of a second predetermined material on a corresponding first surface of each implantation layer to form a second layer; trench filling of a first predetermined material on a corresponding first surface of each implantation layer to form a first layer; wherein the polarity of the first predetermined material is different from the polarity of the second predetermined material.
6. The method of producing a silicon carbide transistor device according to claim 5, wherein The ion implantation is performed on the partial first surface of the epitaxial layer to form a plurality of implantation layers spaced apart along a first direction, comprising: The preset metal is ion implanted on the partial first surface of the epitaxial layer at a first dose and a first depth to form a plurality of implantation layers arranged at intervals along a first direction; wherein the first dose is 1E11 to 9E14 cm -2 , the first depth is 0.7um to 0.8um, and the interval between two adjacent implantation layers is 0.1um to 1.0um.
7. The method of producing a silicon carbide transistor device according to claim 5, wherein The first surface corresponding to each implantation layer is filled with a first preset material through a trench to form a first layer, comprising: Performing first etching on the first surface corresponding to each implantation layer to form a first trench; wherein the depth of the first trench is 0.2um to 0.6um; The first trench is filled with a first preset material to form a first layer; wherein the interval between the first layer and the second layer is 0.1um to 0.4um.
8. The method of producing a silicon carbide transistor device according to claim 5, wherein The method further comprises: Performing second etching on the partial first surface corresponding to each implantation layer to form a second trench; wherein the depth of the second trench is 0.2um to 0.6um, and the second trench is adjacent to the plurality of implantation layers along the first direction; The second trench is filled with a first preset material to form a second doping layer; Performing third etching on the partial first surface corresponding to each implantation layer to form a third trench; wherein the depth of the third trench is 0.2um to 0.5um, and the third trench is adjacent to the second trench along the first direction; The third trench is filled with a first preset material to form a third doping layer; wherein the doping concentration of the third doping layer is less than the doping concentration of the second doping layer.
9. The method of producing a silicon carbide transistor device according to claim 5, wherein The method further comprises: Growth of a gate oxide layer and a polysilicon gate on the first surface of the epitaxial layer, and etching of the gate oxide layer and the polysilicon gate to form a gate electrode; Deposition of a dielectric material on the gate electrode, and etching of the dielectric material to obtain a dielectric layer; wherein the dielectric material comprises silicon dioxide.
10. The method of producing a silicon carbide transistor device according to claim 9, wherein The method further comprises: Formation of a source electrode on the dielectric layer and in a region corresponding to the plurality of implantation layers, and ohmic contact between the source electrode and the first doping layer.