Semiconductor device and preparation method thereof
By introducing deep-level impurities into the source region structure of SiC MOSFETs to form recombination centers, the problem of high turn-off loss in SiC MOSFET devices is solved, and performance improvement is achieved in high-frequency power electronics applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-23
- Publication Date
- 2026-03-31
AI Technical Summary
The SiC MOSFET device has a long reverse recovery time of the body diode during the turn-off process, resulting in large turn-off losses, which limits its advantages in high-frequency power electronics applications.
By introducing deep-level impurities into the source region structure of SiC MOSFETs to form recombination centers, and by creating lattice defects in the second doped region, local lifetime control is achieved, minority carrier lifetime is shortened, and the reverse recovery process of the body diode is accelerated.
This significantly reduces the turn-off loss of SiC MOSFETs and improves the performance of the devices in high-frequency power electronics applications.
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Figure CN121772285A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device technology, and more specifically, to a semiconductor device and a method for fabricating the same. Background Technology
[0002] Silicon carbide (SiC) semiconductor devices are considered ideal materials for next-generation power devices in the field of power electronics due to their excellent physical properties, such as high breakdown field strength, high thermal conductivity, and wide bandgap. Especially under high voltage and high temperature operating conditions, SiC-based MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) exhibit lower power consumption and higher reliability compared to traditional silicon-based IGBTs (Insulated-Gate Bipolar Transistors). However, the traditional structure of SiC MOSFETs has some inherent limitations, particularly the reverse recovery characteristics of the body diode in the off-state, which directly affects the overall dynamic performance of the device.
[0003] During the turn-off process of a SiC MOSFET, the reverse recovery time of the body diode is relatively long. This is due to the inherent characteristics of SiC material, which results in a large reverse recovery charge at the moment of switching, thus increasing turn-off losses. This phenomenon is particularly pronounced under high-frequency operating conditions, limiting the advantages of SiC MOSFETs in high-frequency power electronics applications.
[0004] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention
[0005] The main objective of this application is to provide a semiconductor device and its fabrication method to solve the problem of high turn-off loss of the body diode in the prior art semiconductor device.
[0006] To achieve the above objectives, according to one aspect of this application, a semiconductor device is provided, comprising: a substrate including a substrate and an epitaxial layer, the epitaxial layer being located on one side of the substrate, the substrate having a first doping type; a plurality of source region structures spaced apart in the epitaxial layer, each source region structure including a first doped region, a second doped region, and a third doped region, the second doped region and the third doped region being in contact and both located within the first doped region, the second doped region including a deep-level impurity for forming recombination centers, the first doped region and the second doped region having a second doping type, and the third doped region having the first doping type; a JFET region located in the epitaxial layer and between any two adjacent source region structures, the second doped region being located on the side of the third doped region away from the JFET region, a portion of the first doped region being between the third doped region and the JFET region; a gate structure located on the side of the JFET region and a portion of the source region structures away from the substrate; a source electrode located on the surface of the source region structure away from the substrate; and a drain electrode located on the side of the substrate away from the epitaxial layer.
[0007] Optionally, the second doped region includes a first sub-doped region, a second sub-doped region, and a third sub-doped region, wherein the second sub-doped region is in contact with the first doped region, the first sub-doped region is located on the side of the second sub-doped region away from the substrate, and the third sub-doped region is located on the side of the first sub-doped region away from the second sub-doped region.
[0008] Optionally, the second sub-doped region is in contact with the third doped region, and the doping concentration of the second sub-doped region is higher than that of the first doped region.
[0009] Optionally, the doping concentration of the third sub-doped region is higher than that of the first sub-doped region and also higher than that of the second sub-doped region.
[0010] Optionally, the gate structure includes a gate oxide layer, a polysilicon gate, and a gate electrode, wherein the gate oxide layer is located on the side of the JFET region and part of the source region structure opposite to the substrate, the polysilicon gate is located on the side of the gate oxide layer opposite to the substrate, and the gate electrode is located on the side of the polysilicon gate opposite to the gate oxide layer.
[0011] Optionally, the semiconductor device further includes an ohmic contact metal and an insulating layer, wherein the ohmic contact metal is located between the epitaxial layer and the source electrode, and the insulating layer is located between the gate structure and the source electrode, and covers a portion of the third doped region.
[0012] Optionally, the deep-level impurities include at least one of the following: vanadium and gold.
[0013] According to another aspect of this application, a method for fabricating a semiconductor device is provided. The method includes: providing a substrate, the substrate including a substrate and an epitaxial layer, the epitaxial layer being located on one side of the substrate, and the substrate having a first doping type; forming a plurality of spaced source region structures in the epitaxial layer, the source region structures including a first doped region, a second doped region, and a third doped region, the second doped region and the third doped region being in contact and both located within the first doped region, the second doped region including a deep-level impurity for forming recombination centers, the first doped region and the second doped region having a second doping type, and the third doped region having the first doping type; forming a JFET region in the epitaxial layer, the JFET region also being located between any two adjacent source region structures, the second doped region being located on the side of the third doped region away from the JFET region, and a portion of the first doped region being between the third doped region and the JFET region; forming a gate structure on the side of the JFET region and the portion of the source region structures away from the substrate; forming a source electrode on the surface of the source region structures away from the substrate; and forming a drain electrode on the side of the substrate away from the epitaxial layer.
[0014] Optionally, the step of forming a plurality of spaced source region structures in the epitaxial layer includes: performing ion implantation in the epitaxial layer to form a first doped region; performing ion implantation in a portion of the first doped region to form a second sub-doped region, performing ion implantation in a portion of the second sub-doped region to form a first sub-doped region, performing ion implantation in a portion of the first sub-doped region to form a third sub-doped region, the remaining first sub-doped region, second sub-doped region and third sub-doped region constituting the second doped region; and performing ion implantation in a portion of the first doped region to form the third doped region.
[0015] Optionally, the step of forming a plurality of spaced source region structures in the epitaxial layer includes: performing ion implantation in the epitaxial layer to form a second sub-doped region; performing ion implantation in a portion of the second sub-doped region to form a first sub-doped region; performing ion implantation in a portion of the first sub-doped region to form a third sub-doped region; and the remaining first sub-doped region, second sub-doped region, and third sub-doped region constituting the second doped region; performing ion implantation in the epitaxial layer to form the first doped region; and performing ion implantation in a portion of the first doped region to form the third doped region.
[0016] The semiconductor device using the technical solution of this application includes a substrate, a source region structure, a gate structure, a JFET region, a source electrode, and a drain electrode. The source region structure includes a first doped region, a second doped region, and a third doped region. The second and third doped regions are in contact and located within the first doped region. The second doped region includes deep-level impurities for forming recombination centers. By providing portions with specific impurities (deep-level impurities) in the second doped region, lattice defects are created in this region, introducing recombination centers. This significantly shortens the minority carrier lifetime, achieves local lifetime control, accelerates the reverse recovery process during body diode turn-off, and reduces turn-off losses, thereby solving the problem of high turn-off losses in body diodes of existing semiconductor devices. Attached Figure Description
[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:
[0018] Figure 1 A cross-sectional structural schematic diagram of a semiconductor device according to an embodiment of this application is shown;
[0019] Figure 2 A schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application is shown.
[0020] Figure 3 It indicates Figure 2 A schematic diagram of the cross-sectional structure of the substrate after the substrate is provided in the fabrication method of semiconductor devices;
[0021] Figure 4 It indicates that in Figure 3 A schematic diagram of the cross-sectional structure of the substrate after the formation of the first doped region in the structure;
[0022] Figure 5 It indicates that in Figure 3 A schematic diagram of the cross-sectional structure of the substrate after the formation of the second doped region in the structure;
[0023] Figure 6 It indicates that in Figure 4 A schematic diagram of the cross-sectional structure of the substrate after the formation of the second doped region in the structure, or an illustration of the cross-sectional structure of the substrate after the formation of the second doped region in the structure. Figure 5 A schematic diagram of the cross-sectional structure of the substrate after the formation of the first doped region in the structure;
[0024] Figure 7 It indicates that in Figure 6 A schematic diagram of the cross-sectional structure of the substrate after the formation of the third doped region in the structure;
[0025] Figure 8It indicates that in Figure 7 A schematic diagram of the cross-sectional structure of the substrate after forming the JFET region, gate oxide layer, polysilicon gate and insulating layer in the structure;
[0026] Figure 9 It indicates that in Figure 8 A schematic diagram of the cross-sectional structure of the substrate after the gate electrode is formed in the structure.
[0027] The above figures include the following reference numerals:
[0028] 10. Substrate; 11. Substrate; 12. Epitaxial layer; 20. Source region structure; 21. First doped region; 22. Second doped region; 221. First sub-doped region; 222. Second sub-doped region; 223. Third sub-doped region; 23. Third doped region; 30. JFET region; 40. Gate structure; 41. Gate oxide layer; 42. Polysilicon gate; 43. Gate electrode; 50. Source electrode; 60. Drain electrode; 70. Ohmic contact metal; 80. Insulating layer. Detailed Implementation
[0029] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0030] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0032] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.
[0033] As described in the background section, in the prior art, the reverse recovery time of the body diode during the turn-off process of SiC MOSFETs is relatively long. This is due to the inherent characteristics of SiC material, which results in a large reverse recovery charge at the moment of switching, thereby increasing turn-off losses. This phenomenon is particularly pronounced under high-frequency operating conditions, limiting the advantages of SiC MOSFETs in high-frequency power electronics applications. To address the problem of high turn-off losses in the body diode of semiconductor devices, embodiments of this application provide a semiconductor device and its fabrication method.
[0034] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
[0035] Embodiments of this application provide a semiconductor device, such as Figure 1 As shown, it includes: a substrate 10, comprising a substrate 11 and an epitaxial layer 12, the epitaxial layer 12 being located on one side of the substrate 11, the substrate 10 having a first doping type; and a plurality of source region structures 20, spaced apart within the epitaxial layer 12, each source region structure 20 including a first doped region 21, a second doped region 22, and a third doped region 23, the second doped region 22 and the third doped region 23 being in contact and both located within the first doped region 21, the second doped region 22 including deep-level impurities for forming recombination centers, the first doped region 21 and the second doped region 22 having a second doping type, and the third doped region 23 having a second doping type. 3 has a first doping type; JFET region 30, located in epitaxial layer 12 and between any two adjacent source region structures 20, second doped region 22 located on the side of third doped region 23 away from JFET region 30, and a portion of first doped region 21 between third doped region 23 and JFET region 30; gate structure 40, located on the side of JFET region 30 and portion of source region structure 20 away from substrate 10; source electrode 50, located on the surface of source region structure 20 away from substrate 11; drain electrode 60, located on the side of substrate 11 away from epitaxial layer 12.
[0036] By setting a portion with specific impurities (deep-level impurities) in the second doped region of the source region structure in a semiconductor device, lattice defects are created in this region, recombination centers are introduced, the minority carrier lifetime can be significantly shortened, local lifetime control is achieved, the reverse recovery process during body diode turn-off is accelerated, and the turn-off loss is reduced, thereby solving the problem of large turn-off loss of body diodes in existing semiconductor devices.
[0037] In the above embodiments, the substrate can consist of an N-type SiC substrate and an epitaxial layer grown thereon. The resistivity of the substrate can be 0.02 ± 20% Ωcm, while the epitaxial layer, as the drift region of the device, can bear the main breakdown voltage, and the doping concentration can be 1E15~1E16 cm⁻¹. -3 The drift region thickness can be 9~11μm for a 1200V MOS and 5~7μm for a 650V MOS. Both the substrate and the epitaxial layer are N-type doped, ensuring the stability and conductivity of the overall structure.
[0038] In the above embodiments, the implanted element in the first doped region can be Al, and its doping concentration can be 1E17±50%cm⁻¹. -3 The implantation depth can be 0.1~0.3 μm. The implanted element in the third doped region can be nitrogen, and its doping concentration can be 1E19~1E20 cm⁻¹. -3 The implantation depth can be 0.2~0.3μm, and the channel width after the third doping region is in the first doping region can be 0.3~0.6μm.
[0039] In the above embodiment, the implanted element in the JFET region can be N element, and its doping concentration can be 1E18±50%cm. -3 With an implantation depth of 0.8~0.9μm, the JFET region allows for adjustment of the current between the source and drain regions. By controlling its width and doping concentration, the balance between the device's switching speed and on-resistance can be optimized.
[0040] In the above embodiments, the first doping type can be N-type doping or P-type doping, and the second doping type can be P-type doping or N-type doping. For example, the first doping type is N-type doping and the second doping type is P-type doping, or the first doping type is P-type doping and the second doping type is N-type doping. The N-type doping element can be any one of pentavalent elements, including phosphorus (P), arsenic (As), and antimony (Sb), and the P-type doping element can be any one of trivalent elements, including boron (B), aluminum (Al), and gallium (Ga). This application does not impose specific limitations.
[0041] In the above embodiments, the source electrode can be made of Ni or Ti, and its thickness can be 2000~8000 Å. The source electrode provides an efficient carrier injection and extraction path, ensuring the ohmic connection between the source region and the circuit. The drain electrode can be made of Ni or Ti, and its thickness can be 500~1500 Å. The drain electrode can collect carriers transported from the drift region and is also part of the device package. It can be connected to the external circuit through materials such as solder.
[0042] In some alternative embodiments, the deep-level impurities include at least one of the following: vanadium and gold. These deep-level impurities, acting as "efficient traps," introduce energy levels far from the conduction and valence bands into the band gap of SiC, i.e., "deep levels." These deep-level impurities can form highly efficient recombination centers in SiC. These recombination centers, like "traps," greatly promote the meeting and recombination of electrons and holes, resulting in annihilation in a very short time. Other elements can also be selected as deep-level impurities depending on the specific circumstances; this application does not impose specific limitations.
[0043] In some alternative implementations, such as Figure 1 As shown, the second doped region 22 includes a first sub-doped region 221, a second sub-doped region 222, and a third sub-doped region 223. The second sub-doped region 222 is in contact with the first doped region 21. The first sub-doped region 221 is located on the side of the second sub-doped region 222 facing away from the substrate 11, and the third sub-doped region 223 is located on the side of the first sub-doped region 221 facing away from the second sub-doped region 222. By implanting deep-level impurities such as vanadium or gold into the intermediate layer (first sub-doped region 221) of the second doped region 22, recombination centers are introduced in this region, achieving local lifetime control. This effectively shortens the minority carrier lifetime, accelerates the reverse recovery process of the body diode (a structure composed of the first doped region and an epitaxial layer) during turn-off, and reduces turn-off losses.
[0044] In some alternative implementations, such as Figure 1 As shown, the second sub-doped region 222 is in contact with the third doped region 23, and the doping concentration of the second sub-doped region 222 is higher than that of the first doped region 21. The third doped region 23 and the second sub-doped region 222 constitute a diode. Since the second sub-doped region 222 is highly doped relative to the first doped region 21, its lateral resistance is lower, thus effectively reducing the lateral resistance of the device. The open region of an NPN bipolar transistor needs to reach the turn-on voltage. Due to the reduced resistance in this region, the voltage drop in this region is reduced, making it more difficult to reach the turn-on voltage. This suppresses the accidental turn-on (latch-up effect) of the parasitic NPN bipolar transistor, ensuring the reliability of the device.
[0045] In some alternative implementations, the doping concentration of the third sub-doped region is higher than that of the first sub-doped region and also higher than that of the second sub-doped region. The third sub-doped region enables excellent ohmic contact, which is the interface directly connected to the source metal. The extremely high doping concentration ensures extremely low contact resistance, providing an unobstructed path for holes to flow from the device interior to the electrode. The first sub-doped region can introduce recombination centers to control carrier lifetime: by injecting deep-level impurities such as vanadium and gold, lattice defects are intentionally created in this layer, forming a large number of recombination centers. Its sole purpose is to drastically shorten the lifetime of minority carriers (electrons) in and around its location. The second sub-doped region ensures junction characteristics and suppresses the turn-on of parasitic NPN bipolar transistors (composed of the third doped region, the first doped region, and the epitaxial layer). This layer is the transition region where the second doped region and the main body of the first doped region are combined. The doping concentration of the second sub-doped region can be 8E18~9E18 cm⁻¹. -3 The thickness can be 0.15~0.25μm, and the doping element can be Al; the doping concentration of the first sub-doped region can be 3E18~5E18cm. -3 The thickness can be 0.10~0.15μm, the doping element can be vanadium ions or gold ions, and the doping dose can be 1E12cm. -3 The doping concentration of the third sub-doped region can be 1E20cm³. -3 The thickness can be 0.08~0.12μm, and the doping element can be Al. The above concentration design can reduce the reverse recovery charge of the body diode of the device by about 30~50%, while increasing the on-resistance by only 2%~5%, which significantly improves the reliability of the device.
[0046] In some alternative implementations, such as Figure 1 As shown, the gate structure 40 includes a gate oxide layer 41, a polysilicon gate 42, and a gate electrode 43. The gate oxide layer 41 is located on the side of the JFET region 30 and part of the source region structure 20 away from the substrate 10. The polysilicon gate 42 is located on the side of the gate oxide layer 41 away from the substrate 10. The gate electrode 43 is located on the side of the polysilicon gate 42 away from the gate oxide layer 41.
[0047] The gate oxide layer 41 ensures that the polysilicon gate 42 does not make direct electrical contact with the underlying JFET region 30 and source region structure 20. The material can be silicon dioxide, and the thickness can be 300~800 Å. The polysilicon gate layer 42 can effectively control the current flow in the JFET region 30, achieving precise control of the MOSFET switching behavior. The thickness can be 2000~8000 Å. The gate electrode 43 can provide a stable voltage input to the polysilicon gate 42, thereby controlling the operating state of the device. The material can be aluminum, copper or molybdenum, and the thickness can be 500~1200 Å.
[0048] In some alternative implementations, such as Figure 1 As shown, the semiconductor device also includes an ohmic contact metal 70 and an insulating layer 80. The ohmic contact metal 70 is located between the epitaxial layer 12 and the source electrode 50, and the insulating layer 80 is located between the gate structure 40 and the source electrode 50, and covers a portion of the third doped region 23.
[0049] The ohmic contact metal 70 forms an ohmic contact with the second doped region 22, creating a low-resistivity connection that reduces current loss. The material can be any one or more of titanium, aluminum, nickel, and molybdenum, and the thickness can be 300~800 Å. The insulating layer 80 ensures electrical isolation between the gate structure and the source electrode, preventing current from flowing from the source electrode to the gate or from the gate to the source electrode when not needed, thereby avoiding the risk of gate short circuit. The material can be SiO2 or others, and the thickness can be 600~1000 nm.
[0050] Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. For example... Figure 2 As shown, the method includes the following steps:
[0051] Step S1, as follows Figure 3 As shown, a substrate 10 is provided, the substrate including a substrate 11 and an epitaxial layer 12, the epitaxial layer 12 being located on one side of the substrate 11, and the substrate 10 having a first doping type;
[0052] Specifically, the substrate can consist of an N-type SiC substrate and an epitaxial layer grown thereon. The resistivity of the substrate can be 0.02 ± 20% Ωcm, while the epitaxial layer, as the drift region of the device, can bear the main breakdown voltage, and the doping concentration can be 1E15~1E16cm. -3 The drift region thickness of a 1200V MOS can be 9~11μm, and the drift region thickness of a 650V MOS can be 5~7μm.
[0053] Step S2, as follows Figures 4 to 7 As shown, multiple spaced source region structures 20 are formed in the epitaxial layer 12. The source region structure 20 includes a first doped region 21, a second doped region 22 and a third doped region 23. The second doped region 22 and the third doped region 23 are in contact and are both located in the first doped region 21. The second doped region 22 includes deep-level impurities for forming recombination centers. The first doped region 21 and the second doped region 22 have a second doping type, and the third doped region 23 has a first doping type.
[0054] Specifically, the deep-level impurities include at least one of the following: vanadium and gold; the second doped region further includes a second sub-doped region and a third sub-doped region; the implanted element in the first doped region can be Al, and its doping concentration can be 1E17 ±50%cm³.-3 The implantation depth can be 0.1~0.3 μm. The implanted element in the third doped region can be nitrogen, and its doping concentration can be 1E19~1E20 cm⁻¹. -3 The implantation depth can be 0.2~0.3μm, and the channel width after the third doping region is formed in the first doped region can be 0.3~0.6μm; the doping concentration of the first sub-doped region can be 3E18~5E18cm. -3 The thickness can be 0.10~0.15μm, the doping element can be vanadium ions or gold ions, and the doping dose can be 1E12cm. -3 The doping concentration of the second sub-doped region can be 8E18~9E18 cm⁻¹ -3 The thickness can be 0.15~0.25μm, and the doping element can be Al; the doping concentration of the third sub-doped region can be 1E20cm⁻¹. -3 The thickness can be 0.08~0.12μm, and the doping element can be Al.
[0055] Step S3, as follows Figure 8 As shown, a JFET region 30 is formed in the epitaxial layer 12. The JFET region 30 is also located between any two adjacent source region structures 20. The second doped region 22 is located on the side of the third doped region 23 away from the JFET region 30. A portion of the first doped region 21 is located between the third doped region 23 and the JFET region 30.
[0056] Specifically, the implanted element in the JFET region can be N element, and its doping concentration can be 1E18±50%cm. -3 The injection depth is 0.8~0.9μm.
[0057] Step S4, as follows Figure 8 and Figure 9 As shown, a gate structure 40 is formed on the side of the JFET region 30 and the partial source region structure 20 facing away from the substrate 10.
[0058] Specifically, the gate structure 40 includes a gate oxide layer 41, a polysilicon gate 42, and a gate electrode 43. The gate oxide layer 41 can be made of silicon dioxide and has a thickness of 300 to 800 Å. The polysilicon gate 42 can have a thickness of 2000 to 8000 Å. The gate electrode 43 can be made of aluminum, copper, or molybdenum and has a thickness of 500 to 1200 Å.
[0059] Step S5, as follows Figure 1 As shown, a source electrode 50 is formed on the surface of the source region structure 20 facing away from the substrate 11.
[0060] Step S6, as follows Figure 1 As shown, a drain electrode 60 is formed on the side of the substrate 11 opposite to the epitaxial layer 12;
[0061] Specifically, the source electrode can be made of Ni or Ti, with a thickness of 2000~8000 Å. The source electrode provides an efficient carrier injection and extraction path, ensuring an ohmic connection between the source region and the circuit. The drain electrode can be made of Ni or Ti, with a thickness of 500~1500 Å. The drain electrode can collect carriers transported from the drift region and is also part of the device package, which can be connected to the external circuit through materials such as solder.
[0062] The semiconductor device prepared by the above-described preparation method in this embodiment has a source region structure in which a portion of a second doped region containing a specific impurity (deep-level impurity) is formed. This region creates lattice defects and introduces recombination centers, which can significantly shorten the minority carrier lifetime, achieve local lifetime control, accelerate the reverse recovery process when the body diode is turned off, and reduce the turn-off loss. This solves the problem of high turn-off loss of the body diode in the prior art semiconductor device.
[0063] In the specific implementation process, the above step S2, which forms multiple spaced source region structures in the epitaxial layer, can be achieved through the following steps:
[0064] like Figure 4 As shown, ion implantation is performed in the epitaxial layer 12 to form the first doped region 21; the implanted element can be Al, and the implantation concentration can be 1E17±50%cm³. -3 The implantation depth can be 0.1~0.3μm for the first doped region 21;
[0065] like Figure 6 As shown, ion implantation is performed in a portion of the first doped region 21 to form a second sub-doped region 222, ion implantation is performed in a portion of the second sub-doped region 222 to form a first sub-doped region 221, ion implantation is performed in a portion of the first sub-doped region 221 to form a third sub-doped region 223, and the remaining first sub-doped region 221, second sub-doped region 222 and third sub-doped region 223 constitute the second doped region 22.
[0066] The injection concentration can be 8E18~9E18 cm⁻¹ -3 The implantation depth can be 0.15~0.25μm, and the doping element can be Al to form a second sub-doped region; the implantation concentration can be 3E18~5E18cm. -3 The depth can be 0.10~0.15μm, the doping element can be vanadium ions or gold ions, and the doping dose can be 1E12cm. -3 To form the first sub-doped region; the implantation concentration can be 1E20cm. -3 The depth can be 0.08~0.12μm, and the doping element can be Al to form a third sub-doped region.
[0067] like Figure 7 As shown, ion implantation is performed in a portion of the first doped region 21 to form the third doped region 23. The implanted element can be nitrogen, and the implantation concentration can be 1E19~1E20 cm⁻¹. -3 The implantation depth can be 0.2~0.3μm to form the third doped region 23, and the channel width in the first doped region 21 can be 0.3~0.6μm.
[0068] The above-mentioned step S2 of this application, forming multiple spaced source region structures in the epitaxial layer, can also be achieved through the following steps:
[0069] like Figure 5 As shown, ion implantation is performed in the epitaxial layer 12 to form a second sub-doped region 222, ion implantation is performed in a portion of the second sub-doped region 222 to form a first sub-doped region 221, ion implantation is performed in a portion of the first sub-doped region 221 to form a third sub-doped region 223, and the remaining first sub-doped region 221, second sub-doped region 222, and third sub-doped region 223 constitute the second doped region 22; as shown Figure 6 As shown, ion implantation is performed in the epitaxial layer 12 to form the first doped region 21; as Figure 7 As shown, ion implantation is performed in a portion of the first doped region 21 to form the third doped region 23. The above steps can use the same technical parameters as the previously described scheme of first forming the first doped region 21, then forming the second doped region 22, and finally forming the third doped region 23, and will not be repeated here.
[0070] The above preparation method also includes: such as Figure 8 As shown, in Figure 7 On the upper surface of the structure, silicon dioxide and polysilicon materials can be deposited sequentially, and etched to obtain a gate oxide layer 41 and a polysilicon gate 42; then an insulating material is deposited to form an insulating layer 80 covering the gate oxide layer 41, the polysilicon gate 42, and part of the source region structure 20; such as Figure 9 As shown, the insulating layer 80 is etched (photolithography can be used) to form a groove, and the material of the gate electrode 43 is filled into the groove to form the gate electrode 43. Finally, an ohmic contact metal 70 is formed on the source region structure 20, and then source metal is deposited on it to form the source electrode 50. Drain metal is deposited on the back side of the substrate 11 to form the drain electrode 60, forming as shown. Figure 1 The device structure shown.
[0071] The aforementioned deposition process can employ physical vapor deposition, chemical vapor deposition, and atomic layer deposition, etc., and this application does not impose any specific limitations.
[0072] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0073] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A semiconductor device, characterized by, Comprising: a substrate comprising a substrate and an epitaxial layer on a side of the substrate, the substrate having a first doping type; a plurality of source region structures spaced apart in the epitaxial layer, the source region structures comprising a first doped region, a second doped region, and a third doped region, the second doped region and the third doped region being in contact and both being in the first doped region, the second doped region comprising deep level impurities for forming recombination centers, the first doped region and the second doped region having a second doping type, the third doped region having the first doping type; a JFET region in the epitaxial layer and between any two adjacent source region structures, the second doped region being on a side of the third doped region facing away from the JFET region, the third doped region and the JFET region having a portion of the first doped region therebetween; a gate structure on a side of the JFET region and a portion of the source region structures facing away from the substrate; a source electrode on a surface of the source region structures facing away from the substrate; a drain electrode on a side of the substrate facing away from the epitaxial layer.
2. The semiconductor device according to claim 1, wherein The second doped region comprises a first sub-doped region, a second sub-doped region, and a third sub-doped region, wherein the second sub-doped region is in contact with the first doped region, the first sub-doped region is on a side of the second sub-doped region facing away from the substrate, and the third sub-doped region is on a side of the first sub-doped region facing away from the second sub-doped region.
3. The semiconductor device of claim 2, wherein, The second sub-doped region is in contact with the third doped region, and a doping concentration of the second sub-doped region is higher than a doping concentration of the first doped region.
4. The semiconductor device according to claim 2, wherein A doping concentration of the third sub-doped region is higher than a doping concentration of the first sub-doped region and higher than a doping concentration of the second sub-doped region.
5. The semiconductor device of claim 1, wherein The gate structure comprises a gate oxide layer, a polysilicon gate, and a gate electrode, wherein the gate oxide layer is on a side of the JFET region and a portion of the source region structures facing away from the substrate, the polysilicon gate is on a side of the gate oxide layer facing away from the substrate, and the gate electrode is on a side of the polysilicon gate facing away from the gate oxide layer.
6. The semiconductor device of claim 1, wherein The semiconductor device further comprises an ohmic contact metal between the epitaxial layer and the source electrode, and an insulating layer between the gate structure and the source electrode and covering a portion of the third doped region.
7. The semiconductor device of claim 1, wherein The deep level impurities comprise at least one of vanadium and gold.
8. A method of manufacturing a semiconductor device, characterized by A method for manufacturing the semiconductor device of any one of claims 1 to 7, the method comprising: providing a substrate comprising a substrate and an epitaxial layer on a side of the substrate, the substrate having a first doping type; forming a plurality of spaced apart source region structures in the epitaxial layer, the source region structures comprising a first doped region, a second doped region, and a third doped region, the second doped region and the third doped region being in contact and both being in the first doped region, the second doped region comprising deep level impurities for forming recombination centers, the first doped region and the second doped region having a second doping type, the third doped region having the first doping type; forming a JFET region in the epitaxial layer, the JFET region also being located between any two adjacent source region structures, the second doped region being located on a side of the third doped region facing away from the JFET region, the third doped region and the JFET region having part of the first doped region therebetween; forming a gate structure on a side of the JFET region and part of the source region structures facing away from the substrate; forming a source electrode on a surface of the source region structures facing away from the substrate; forming a drain electrode on a side of the substrate facing away from the epitaxial layer.
9. The production method according to claim 8, characterized by, The step of forming a plurality of spaced source region structures in the epitaxial layer comprises: forming a first doped region by ion implantation in the epitaxial layer; forming a second sub-doped region by ion implantation in part of the first doped region, forming a first sub-doped region by ion implantation in part of the second sub-doped region, forming a third sub-doped region by ion implantation in part of the first sub-doped region, the remaining first sub-doped region, second sub-doped region and third sub-doped region constituting the second doped region; forming the third doped region by ion implantation in part of the first doped region.
10. The preparation method according to claim 8, characterized in that, The step of forming a plurality of spaced source region structures in the epitaxial layer comprises: forming a second sub-doped region by ion implantation in the epitaxial layer, forming a first sub-doped region by ion implantation in part of the second sub-doped region, forming a third sub-doped region by ion implantation in part of the first sub-doped region, the remaining first sub-doped region, second sub-doped region and third sub-doped region constituting the second doped region; forming the first doped region by ion implantation in the epitaxial layer; forming the third doped region by ion implantation in part of the first doped region.