Thin film transistor, driving circuit, display panel and display device

Abstract

The invention relates to the technical field of display, in particular to a thin film transistor, a driving circuit, a display panel and a display device. According to the thin film transistor, at least a second semiconductor layer is arranged in the thickness direction of a substrate layer, and a grid electrode controls the second semiconductor layer and a first semiconductor layer at the same time, so that an upper conducting channel and a lower conducting channel are formed in the second semiconductor layer and the first semiconductor layer during working, and the channel width of the thin film transistor is equivalently increased under the condition that the occupied area on a plane is not changed; therefore, the channel current of the thin film transistor is increased, the problem that a traditional thin film transistor is difficult to meet the pixel charging requirement of a high-end display panel due to the material mobility characteristic and layout space limitation is solved, the refresh rate of a displayer is effectively increased, and the smoother display effect is achieved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a thin-film transistor and its driving circuit, a display panel, and a display device. Background Technology

[0002] With the development of information technology, human society has ushered in an era of information explosion. As an important channel for obtaining information, display technology has been widely used in education, medical care, commerce and military fields. The market's requirements for the performance of display products are also becoming increasingly stringent. However, traditional thin-film transistors are difficult to meet the needs of high-end display panels. Summary of the Invention

[0003] The purpose of this application is to provide a thin-film transistor and its driving circuit, a display panel, and a display device to solve the problem of mismatch between existing thin-film transistors and the requirements of high-end display panels.

[0004] To achieve the above objectives, this application provides a thin-film transistor, comprising a substrate layer, a first semiconductor layer, a first insulating layer, a gate, a second insulating layer, a second semiconductor layer, and source and drain electrodes. The first semiconductor layer is located on one side of the substrate layer and includes a first source region, a first drain region, and a first channel located between the first source region and the first drain region. The first insulating layer is located on the side of the first semiconductor layer away from the substrate layer and covers the first semiconductor layer. The gate is located on the side of the first insulating layer away from the substrate layer. The second insulating layer is located on the side of the gate away from the substrate layer and covers the gate. The second semiconductor layer is located on the side of the second insulating layer away from the substrate layer and includes a second source region, a second drain region, and a second channel located between the second source region and the second drain region. The source and drain include a source and a drain, wherein the source is electrically connected to the second source region, the drain is electrically connected to the second drain region, the first source region is electrically connected to the source, and the first drain region is electrically connected to the drain.

[0005] In one embodiment of this application, the first semiconductor layer and the second semiconductor layer have the same conductivity type.

[0006] In one embodiment of this application, the first semiconductor layer and the second semiconductor layer may be made of the same or different materials;

[0007] Preferably, the material of the semiconductor layer includes oxide semiconductor, low-temperature polycrystalline silicon, or amorphous silicon;

[0008] Preferably, the first semiconductor layer and the second semiconductor layer are made of the same material.

[0009] In one embodiment of this application, the orthogonal projection of the gate on the substrate layer overlaps the orthogonal projection of the first channel on the substrate layer; the orthogonal projection of the gate on the substrate layer overlaps the orthogonal projection of the second channel on the substrate layer.

[0010] Preferably, the boundary of the gate near the first source region is aligned with the boundary of the first source region near the first channel; the boundary of the gate near the first drain region is aligned with the boundary of the first drain region near the first channel.

[0011] In one embodiment of this application, the orthographic projection of the first semiconductor layer on the substrate layer overlaps the orthographic projection of the gate on the substrate layer; the orthographic projection of the second semiconductor layer on the substrate layer overlaps the orthographic projection of the gate on the substrate layer.

[0012] Preferably, the orthographic projection of the second source region on the substrate layer at least partially overlaps with the orthographic projection of the first source region on the substrate layer; the orthographic projection of the second drain region on the substrate layer at least partially overlaps with the orthographic projection of the first drain region on the substrate layer.

[0013] In one embodiment of this application, the first source region is electrically connected to the source electrode, and the first drain region is electrically connected to the drain electrode;

[0014] Preferably, the first source region is electrically connected to the second source region through a first contact via penetrating the first insulating layer and the second insulating layer, and is electrically connected to the source electrode through the second source region; the first drain region is electrically connected to the second drain region through a second contact via penetrating the first insulating layer and the second insulating layer, and is electrically connected to the drain electrode through the second drain region.

[0015] In one embodiment of this application, the thin-film transistor further includes: a third insulating layer to a 2n insulating layer, a second gate to an nth gate, and a third semiconductor layer to an (n+1)th semiconductor layer; wherein the (2m-1)th insulating layer is located on the side of the mth semiconductor layer away from the substrate; the mth gate is located on the side of the (2m-1)th insulating layer away from the substrate; the 2m insulating layer is located on the side of the mth gate away from the substrate; the (m+1)th semiconductor layer is located on the side of the 2m insulating layer away from the substrate, and the (m+1)th semiconductor layer includes an (m+1)th source region, an (m+1)th drain region, and an (m+1)th channel located between the (m+1)th source region and the (m+1)th drain region; wherein the source is electrically connected to the (m+1)th source region, the drain is electrically connected to the (m+1)th drain region, and the source and drain are always located on the side of the semiconductor layer furthest from the substrate along the thickness direction of the semiconductor layer (n is an integer greater than or equal to 2, and m is an integer greater than or equal to 2 and less than or equal to n).

[0016] In one embodiment of this application, the (n+1)th semiconductor layer has the same conductivity type as the first semiconductor layer and the second semiconductor layer.

[0017] This application also provides a driving circuit, which includes a thin-film transistor as described above.

[0018] This application also provides a display panel, which includes thin-film transistors or driving circuits as described above.

[0019] In one embodiment of this application, the display panel further includes a protective layer, a planarization layer, and a pixel electrode layer. The protective layer is located on the side of the source / drain electrode away from the substrate layer. The planarization layer is located on the side of the protective layer away from the substrate layer. The pixel electrode layer is located on the side of the planarization layer away from the substrate layer. The pixel electrode layer is electrically connected to the drain electrode through a third contact via penetrating the planarization layer and the protective layer.

[0020] This application also provides a display device, which includes a thin-film transistor, or a driving circuit, or a display panel as described above.

[0021] The beneficial effects of the embodiments of this application, which differ from the prior art, are as follows: The thin-film transistor and driving circuit, display panel, and display device provided by this application, by providing at least a second semiconductor layer in the thickness direction of the substrate layer, and controlling the second semiconductor layer and the first semiconductor layer simultaneously by the gate, form two conductive channels in the second semiconductor layer and the first semiconductor layer during operation. This is equivalent to increasing the channel width of the thin-film transistor, thereby increasing the channel current of the thin-film transistor. This solves the problem that traditional thin-film transistors, due to the mobility characteristics of the material itself and the limitations of the layout space, are unable to meet the pixel charging requirements of high-end display panels, effectively improving the refresh rate of the display and achieving a smoother display effect. Attached Figure Description

[0022] To clearly illustrate the technical solutions of the embodiments of this application, the relevant drawings are briefly described below. It should be noted that the following drawings are only some embodiments, and those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0023] Figure 1 A schematic diagram of the layered structure of a thin-film transistor provided in a related embodiment;

[0024] Figure 2 This is a schematic diagram of the layered structure of a thin-film transistor in an embodiment of this application;

[0025] Figure 3 This is a schematic diagram of the layered structure of another thin-film transistor in an embodiment of this application;

[0026] Figure 4 This is a schematic diagram of the layered structure of a display panel in an embodiment of this application.

[0027] The components in the diagram are shown below:

[0028] Substrate 10; First source region 101; First channel 102; First drain region 103; First semiconductor layer 104; First insulating layer 20; First gate 30; Second insulating layer 40; Second source region 501; Second channel 502; Second drain region 503; Second semiconductor layer 504; First contact via 601; Second contact via 602; Source 70; Drain 80; Third insulating layer 220; Second gate 230; Fourth insulating layer 240; Third source region 2501; Third channel 2502; Third drain region 2503; Third semiconductor layer 2504; Third contact via 2601; Fourth contact via 2602; Protective layer 370; Planarization layer 380; Pixel electrode layer 390; Fifth contact via 3901. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0030] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0031] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0032] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0033] With the continuous development of display technology, the market's requirements for the performance of display products are becoming increasingly stringent. In order to achieve better display effects, high refresh rates are gradually becoming a development trend for future display products.

[0034] Reference Figure 1 , Figure 1This is a schematic diagram of the layered structure of a thin-film transistor provided in a related embodiment. In related technologies, a thin-film transistor typically includes a substrate 10, a first semiconductor layer 104, a first insulating layer 20, a first gate 30, a second insulating layer 40, a source 70, and a drain 80. The substrate 10 can be a high-transparency substrate (transparency greater than or equal to 90%), such as a transparent polyimide substrate or a glass substrate. The first semiconductor layer 104 is located on one side of the substrate 10, and includes a first source region 101, a first drain region 103, and a first channel 102 located between the first source region 101 and the first drain region 103. The material of the first semiconductor layer 104 can be an indium bismuth oxide (IGZO), low-temperature polycrystalline silicon (LTPS), or amorphous silicon (α-Si). IGZO materials include indium gallium zinc oxide, indium zinc oxide, and indium tin zinc oxide, which can achieve very low off-state currents, beneficial for maintaining node potential and reducing static power consumption. LTPS has the advantage of a carrier mobility much higher than amorphous silicon or conventional oxide semiconductors, providing strong on-current. The first insulating layer 20 and / or the second insulating layer 40 can be made of silicon nitride, silicon oxide, etc., possessing high dielectric constant, high insulation strength, low defect density, and good compactness. The first insulating layer 20 is located on the side of the first semiconductor layer 104 away from the substrate layer 10, and the first gate 30 and the first channel 102 can be isolated by the first insulating layer 20. The first gate 30 is located on the side of the first insulating layer 20 away from the substrate layer 10, and the material of the first gate 30 can be molybdenum, aluminum-based alloys, etc., possessing low resistance and good adhesion. For example, the boundary of the first gate 30 near the first source region 101 is aligned with the boundary of the first source region 101 near the first channel 102; the boundary of the first gate 30 near the first drain region 103 is aligned with the boundary of the first drain region 103 near the first channel 102. This self-aligned structure helps reduce parasitic capacitance. A second insulating layer 40 is located on the side of the first gate 30 away from the substrate layer 10. This second insulating layer 40 covers the first gate 30, protecting it from physical and chemical damage while electrically isolating the upper-layer circuitry from the first gate 30, thus reducing parasitic capacitance. The source 70 and / or drain 80 can be made of titanium / aluminum / titanium, requiring good ohmic contact with the semiconductor layer. The first source region 101 is electrically connected to the source electrode 70 through a first contact via 601 penetrating the first insulating layer 20 and the second insulating layer 40, and the first drain region 103 is electrically connected to the drain electrode 80 through a second contact via 602 penetrating the first insulating layer 20 and the second insulating layer 40.

[0035] To meet the pixel charging requirements of high-end display panels, optimizing the thin-film transistor (TFT) can increase material costs or affect layout space, thus limiting the resolution of high-resolution display panels. Therefore, improving the channel current of the TFT within limited cost and layout space is currently a challenge in the production process of high-end display panels.

[0036] Based on the technical problems discovered in the aforementioned related display technologies, this application provides a thin-film transistor (TFT). This TFT, while maintaining the same area on a plane, has more conductive channels, thus increasing the equivalent channel width to increase channel current and improve refresh rate. Furthermore, with the same equivalent channel width, the channel distribution on the plane can be reduced, making the TFT occupy less space on the plane and improving the resolution of the display panel.

[0037] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0038] Reference Figure 2 , Figure 2 This is a schematic diagram of the layered structure of a thin-film transistor provided in an embodiment of this application. For example... Figure 2 As shown, the thin-film transistor 1 includes a substrate layer 10, a first semiconductor layer 104, a first insulating layer 20, a first gate 30, a second insulating layer 40, a second semiconductor layer 504, a source 70, and a drain 80. The second semiconductor layer 504 includes a second source region 501, a second drain region 503, and a second channel 502 located between the second source region 501 and the second drain region 503. When the thin-film transistor is operating, the second channel 502 can form a second conductive channel under the control of the first gate 30, increasing the number of channels in the thin-film transistor, which is equivalent to increasing the channel width of the thin-film transistor, thereby increasing the channel current of the thin-film transistor and preventing the thin-film transistor from failing to charge the pixel voltage or capacitor voltage to a predetermined value within a short time after processing.

[0039] The substrate 10 provides mechanical support for the entire device. The substrate material is a high-transmittance substrate (transmittance greater than or equal to 90%), such as a glass substrate. For flexible display applications, the substrate can be replaced with a polyimide (PI) film.

[0040] The first semiconductor layer 104 is located on one side of the substrate layer 10. The first semiconductor layer 104 includes a first source region 101, a first drain region 103, and a first channel 102 located between the first source region 101 and the first drain region 103. The material of the first semiconductor layer 104 can be an oxide semiconductor, low-temperature polycrystalline silicon, or amorphous silicon. The oxide semiconductor includes indium gallium zinc oxide, indium zinc oxide, indium tin zinc oxide, etc. This material, after annealing, can form a stable amorphous structure with high mobility and extremely low off-state current. For example, when the conductivity type of the first semiconductor layer 104 is N-type, both the first source region 101 and the first drain region 103 are heavily N-doped.

[0041] The first insulating layer 20 is located on the side of the first semiconductor layer 104 away from the substrate layer 10, and the first insulating layer 20 covers the first semiconductor layer 104. By providing the first insulating layer 20, the first gate 30 and the first channel 102 can be isolated. The material of the first insulating layer 20 can be silicon nitride, silicon oxide, etc., which has a high dielectric constant, high insulation strength, low defect density and good compactness, and can effectively block water and oxygen diffusion to the semiconductor layer.

[0042] The first gate 30 is located on the side of the first insulating layer 20 away from the substrate layer 10. The first gate 30 can adopt a three-layer metal stack structure of molybdenum (Mo) / aluminum (Al) / molybdenum (Mo). The bottom layer Mo enhances the adhesion to the insulating layer, the middle Al provides low resistance, and the top layer Mo prevents Al diffusion and facilitates subsequent photolithography and etching.

[0043] The second insulating layer 40 is located on the side of the first gate 30 away from the substrate layer 10, and the second insulating layer covers the first gate 30. By providing the second insulating layer 40, the first gate 30 and the second channel 502 can be isolated while protecting the first gate 30 from physical and chemical damage, electrically isolating the upper circuitry from the first gate 30, and reducing parasitic capacitance.

[0044] The second semiconductor layer 504 is located on the side of the second insulating layer 40 away from the substrate layer 10. The material of the second semiconductor layer 504 can be oxide semiconductor, low-temperature polycrystalline silicon, or amorphous silicon. The materials of the second semiconductor layer and the first semiconductor layer can be the same or different. For example, when the conductivity type of the first semiconductor layer 104 is N-type, the conductivity type of the second semiconductor layer 504 is also N-type, so that a single gate can synchronously control the upper and lower conductive channels, causing both conductive channels to be turned on or off simultaneously, thereby increasing the equivalent channel width and improving device performance. For example, the second semiconductor layer 504 is made of the same material as the first semiconductor layer 104, so that the upper and lower channels have the same electrical characteristics (such as threshold voltage, subthreshold swing, etc.).

[0045] The source and drain include a source 70 and a drain 80. Source 70 is electrically connected to the second source region 501, and drain 80 is electrically connected to the second drain region 503. The first source region 101 is electrically connected to source 70, and the first drain 103 is electrically connected to drain 80. The source 70 and / or drain 80 can be made of titanium / aluminum / titanium and need to form good ohmic contacts with the semiconductor layer.

[0046] In one embodiment of this application, the orthogonal projection of the first gate 30 on the substrate 10 covers the orthogonal projection of the first channel 102 on the substrate 10; the orthogonal projection of the first gate 30 on the substrate 10 covers the orthogonal projection of the second channel 502 on the substrate 10.

[0047] For example, the boundary of the first gate 30 near the first source region 101 is aligned with the boundary of the first source region 101 near the first channel 102; the boundary of the first gate 30 near the first drain region 103 is aligned with the boundary of the first drain region 103 near the first channel 102. This self-aligned structure helps to reduce parasitic capacitance.

[0048] In one embodiment of this application, the orthogonal projection of the first semiconductor layer 104 on the substrate 10 covers the orthogonal projection of the first gate 30 on the substrate 10; the orthogonal projection of the second semiconductor layer 504 on the substrate 10 covers the orthogonal projection of the first gate 30 on the substrate 10; ensuring that the gate electric field can effectively regulate the upper and lower channels.

[0049] For example, the orthographic projection of the second source region 501 on the substrate 10 at least partially overlaps with the orthographic projection of the first source region 101 on the substrate 10; the orthographic projection of the second drain region 503 on the substrate 10 at least partially overlaps with the orthographic projection of the first drain region 103 on the substrate 10; these overlapping regions prepare for the subsequent formation of vertical interconnect vias.

[0050] In one embodiment of this application, the first source region 101 is electrically connected to the source electrode 70, and the first drain region 103 is electrically connected to the drain electrode 80. The source and drain electrodes can adopt a three-layer metal stack structure of titanium (Ti) / aluminum (Al) / titanium (Ti), wherein the bottom Ti layer can form a good ohmic contact with the semiconductor, the middle Al layer provides low-resistance wiring, and the top Ti layer serves as a barrier layer and a reflective layer.

[0051] For example, the first source region 101 is electrically connected to the second source region 501 through a first contact via 601 penetrating the first insulating layer 20 and the second insulating layer 40, and is electrically connected to the source electrode 70 through the second source region 501; the first drain region 103 is electrically connected to the second drain region 503 through a second contact via 602 penetrating the first insulating layer 20 and the second insulating layer 40, and is electrically connected to the drain electrode 80 through the second drain region 503.

[0052] This application also provides a thin-film transistor in its embodiments. This embodiment is based on the above... Figure 2 In the existing structure, a gate (second gate), a third semiconductor layer, and a corresponding insulating layer are added, such as... Figure 3 As shown, the thin-film transistor also includes a substrate layer 10, a first semiconductor layer 104, a first insulating layer 20, a first gate 30, a second insulating layer 40, a second semiconductor layer 504, a source 70, and a drain 80. The source and drain are always located on the side of the uppermost semiconductor layer furthest from the substrate layer. The difference lies in that the thin-film transistor also includes a third insulating layer 220, a second gate 230, a fourth insulating layer 240, and a third semiconductor layer 2504. The third semiconductor layer 2504 includes a third source region 2501, a third channel 2502, and a third drain region 2503 located between the third source region 2501 and the third channel 2502. The third source region 2501 is electrically connected to the source 70 during the fabrication of the thin-film transistor, and the second drain region 2503 is electrically connected to the drain 80 during the fabrication of the thin-film transistor. The source 70 is electrically connected to the second source region 501, and the drain 80 is electrically connected to the second drain region 503. The first source region 101 is electrically connected to the source 70, and the first drain region 103 is electrically connected to the drain 80, thereby providing more current transmission paths and increasing the channel current.

[0053] The substrate 10 provides mechanical support for the entire device. The substrate material is a high-transmittance substrate (transmittance greater than or equal to 90%), such as a glass substrate or a polyimide (PI) film. A first semiconductor layer 104 is located on one side of the substrate 10. The first semiconductor layer 104 includes a first source region 101, a first drain region 103, and a first channel 102 located between the first source region 101 and the first drain region 103. A first insulating layer 20 is located on the side of the first semiconductor layer 104 away from the substrate 10, and covers the first semiconductor layer 104. The first gate 30 and the first channel 102 are isolated by the first insulating layer 20. The first gate 30 is located on the side of the first insulating layer 20 away from the substrate 10. A second insulating layer 40 is located on the side of the first gate 30 away from the substrate 10, and covers the first gate 30. By providing the second insulating layer 40, the first gate 30 and the second channel 502 can be isolated. The second semiconductor layer 504 is located on the side of the second insulating layer 40 away from the substrate layer 10.

[0054] The third insulating layer 220 is disposed on the side of the second semiconductor layer 504 away from the substrate layer 10. This third insulating layer 220 covers the second semiconductor layer 504. By providing the third insulating layer 220, the second gate 230 and the second channel 502 can be isolated. The material of the third insulating layer 20 can be silicon nitride, silicon oxide, etc., possessing high dielectric constant, high insulation strength, low defect density, and good compactness, while effectively preventing water and oxygen diffusion into the semiconductor layer.

[0055] The second gate 230 is disposed on the side of the third insulating layer 220 away from the substrate layer 10. The orthogonal projection of the second gate 230 onto the substrate layer 10 overlaps with the orthogonal projection of the second channel 502 onto the substrate layer 10; the orthogonal projection of the second gate 230 onto the substrate layer 10 overlaps with the orthogonal projection of the third channel 2502 onto the substrate layer 10. For example, the boundary of the second gate 230 near the second source region 501 is aligned with the boundary of the second source region 501 near the second channel 502, and the boundary of the second gate 230 near the second drain region 503 is aligned with the boundary of the second drain region 503 near the second channel 502. This self-aligned structure helps to reduce parasitic capacitance.

[0056] The fourth insulating layer 240 is disposed on the side of the second gate 230 away from the substrate layer 10. The fourth insulating layer 240 is located on the side of the second gate 230 away from the substrate layer 10, and this fourth insulating layer covers the second gate 230. By providing the fourth insulating layer 240, the second gate 230 and the third channel 2502 can be isolated while protecting the second gate 230 from physical and chemical damage, electrically isolating the upper layer lines from the second gate 230, and reducing parasitic capacitance.

[0057] The third semiconductor layer 2504 is disposed on the side of the fourth insulating layer 240 away from the substrate layer 10. The conductivity type of the third semiconductor layer 2504 is the same as that of the second semiconductor layer 504 and the first semiconductor layer 104. For example, when the conductivity type of the first semiconductor layer 104 and the second semiconductor layer 504 is N-type, the conductivity type of the third semiconductor layer 2504 is also N-type to achieve synchronous control of the gate, thereby increasing the equivalent channel width and improving device performance. The material of the third semiconductor layer 2504 can be the same as or different from the materials of the second semiconductor layer 504 and the first semiconductor layer 104. The material of the third semiconductor layer 104 can be oxide semiconductor, low-temperature polycrystalline silicon, or amorphous silicon, wherein the oxide semiconductor includes indium gallium zinc oxide, indium zinc oxide, indium tin zinc oxide, etc., which can form a stable amorphous structure after annealing, and has high mobility and extremely low off-state current.

[0058] In one embodiment of this application, the orthographic projection of the second semiconductor layer 504 on the substrate 10 overlaps the orthographic projection of the second gate 230 on the substrate 10; the orthographic projection of the third semiconductor layer 2504 on the substrate 10 overlaps the orthographic projection of the second gate 230 on the substrate 10; ensuring that the electric field of the second gate 230 can effectively regulate the upper and lower channels. Exemplarily, the orthographic projections of the first source region 101, the second source region 501, and the third source region 2501 on the substrate 10 at least partially overlap; the orthographic projections of the first drain region 103, the second drain region 503, and the third drain region 2503 on the substrate 10 at least partially overlap; these overlapping regions prepare for the subsequent formation of vertical interconnect vias.

[0059] In one embodiment of this application, the source 70 is electrically connected to the first source region 101, the drain 80 is electrically connected to the first drain region 103, the source 70 is electrically connected to the second source region 501, the drain 80 is electrically connected to the second drain region 503, the source 70 is electrically connected to the third source region 2501, and the drain 80 is electrically connected to the third drain region 2503. For example, the first source region 101 is electrically connected to the second source region 501 through a first contact via 601 penetrating the first insulating layer 20 and the second insulating layer 40. The second source region 501 is electrically connected to the third source region 2501 through a third contact via 2601 penetrating the third insulating layer 220 and the fourth insulating layer 240, and is electrically connected to the source electrode 70 through the third source region 2501. The first drain region 103 is electrically connected to the second drain region 503 through a second contact via 602 penetrating the first insulating layer 20 and the second insulating layer 40. The second drain region 503 is electrically connected through a third insulating layer 220 through a third contact via 602 penetrating the third insulating layer 40. The fourth contact via 2602 of the 220 and the fourth insulating layer 240 is electrically connected to the third drain region 2503 and electrically connected to the drain electrode 80 through the third drain region 2503. Alternatively, by way of example, the first source region 101 is electrically connected to the source electrode 70 through the first contact via penetrating the first insulating layer 20, the second insulating layer 40, the second source region 501, the third insulating layer and the fourth insulating layer; the first drain region 103 is electrically connected to the drain electrode 80 through the second contact via penetrating the first insulating layer 20, the second insulating layer 40, the second drain region 503, the third insulating layer and the fourth insulating layer.

[0060] In one embodiment of this application, the size of the semiconductor layer on the plane can be reduced, provided that the thin-film transistor only needs to have the same equivalent channel width as the thin-film transistor in the related embodiments. For example, when the equivalent channel widths of the first and second semiconductor layers are consistent with those of the thin-film transistor in the related embodiments, the dimensions of the first and second semiconductor layers perpendicular to the semiconductor layer thickness direction can be reduced to half the dimensions of the thin-film transistor perpendicular to the semiconductor layer thickness direction in the related embodiments. This results in a smaller space occupied by the thin-film transistor on the plane, thereby improving the resolution of the display panel.

[0061] In one embodiment of this application, a thin-film transistor is also provided, including a third insulating layer to a 2n insulating layer, a second gate to an nth gate, and a third semiconductor layer to an (n+1)th semiconductor layer. The (2m-1)th insulating layer is located on the side of the mth semiconductor layer away from the substrate and covers the (2m-2)th semiconductor layer; the mth gate is located on the side of the (2m-1)th insulating layer away from the substrate, and the orthogonal projection of the mth gate onto the substrate covers the orthogonal projection of the 2m-2th channel onto the substrate, and the orthogonal projection of the mth gate onto the substrate covers the orthogonal projection of the 2m-1th channel onto the substrate; the 2m insulating layer is located on the side of the mth gate away from the substrate and covers the mth gate; the (m+1)th semiconductor layer is located on the side of the 2m insulating layer away from the substrate. The orthogonal projection of the (m+1)th semiconductor layer onto the substrate covers the orthogonal projection of the m-th gate onto the substrate. The (m+1)th semiconductor layer includes the (m+1)th source region, the (m+1)th drain region, and the (m+1)th channel located between the (m+1)th source region and the (m+1)th drain region. The source is electrically connected to the (m+1)th source region, and the drain is electrically connected to the (m+1)th drain region. The source and drain are always located on the side of the semiconductor layer furthest from the substrate along the thickness direction (n is an integer greater than or equal to 2, and m is an integer greater than or equal to 2 and less than or equal to n). This embodiment, through a 3D stacking design, significantly improves the performance of thin-film transistors without increasing the planar area, making it suitable for applications with extremely high requirements for drive current and integration density, such as high-resolution, high-refresh-rate display panels.

[0062] In one embodiment of this application, all semiconductor layers have the same conductivity type, that is, the (n+1)th semiconductor layer has the same conductivity type as the first and second semiconductor layers, in order to achieve synchronous control of the gate, thereby increasing the equivalent channel width and improving device performance. The semiconductor layer material includes oxide semiconductor, low-temperature polycrystalline silicon, or amorphous silicon. For example, all n+1 semiconductor layers are made of the same material.

[0063] In one embodiment of this application, the boundary of the xth gate near the xth source region is aligned with the boundary of the xth source region near the xth channel, and the boundary of the xth gate near the xth drain region is aligned with the boundary of the xth drain region near the xth channel (x is an integer greater than or equal to 2 and less than or equal to n, and n is an integer greater than or equal to 2) to reduce parasitic capacitance.

[0064] In one embodiment of this application, the orthographic projection of the (n+1)th source region on the substrate layer at least partially overlaps with the orthographic projection of the nth source region on the substrate layer, and the orthographic projection of the (n+1)th drain region on the substrate layer at least partially overlaps with the orthographic projection of the nth drain region on the substrate layer (n is an integer greater than or equal to 2). These overlapping regions prepare for the subsequent formation of vertical interconnect vias.

[0065] In one embodiment of this application, all source regions are electrically connected to the source, and all drain regions are electrically connected to the drain. For example, the nth source region is electrically connected to the (n+1)th source region via a contact via, the nth drain region is electrically connected to the (n+1)th drain region via a contact via, the (n+1)th source region is electrically connected to the source, and the (n+1)th drain region is electrically connected to the drain (n is an integer greater than or equal to 2). This application provides a driving circuit including the thin-film transistor described above. For example, this driving circuit is suitable for applications with extremely high requirements for driving current and integration density, such as pixel driving circuits in high-resolution, high-refresh-rate display panels (Micro-LED, OLED), directly controlling the light emission of each sub-pixel. Alternatively, it can also be used in high-density integrated circuits, etc. The specific application of the thin-film transistor in this application is not limited.

[0066] This application provides a display panel that includes the thin-film transistors described above, and / or includes the driving circuit described above. Exemplarily, the display panel can be an OLED (Organic Light Emitting Diodes) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, etc. Figure 4 As shown, the display panel also includes a protective layer 370, a planarization layer 380, and a pixel electrode layer 390. The protective layer 370 is disposed on the side of the source electrode 70 and drain electrode 80 away from the substrate layer 10. Its core function is to provide mechanical and chemical protection, preventing the active layer from deteriorating due to moisture or oxygen intrusion from subsequent processes or the environment, while also preventing potential short circuits between the electrodes. The material of the protective layer 370 is preferably silicon nitride, due to its extremely high density and excellent ability to block water and oxygen diffusion. In actual fabrication, a uniformly thick SiN layer can be formed at low temperatures using plasma-enhanced chemical vapor deposition (PECVD). xThin film. In some embodiments, the protective layer 370 may also employ a silicon oxide or silicon nitride / silicon oxide composite stack structure to achieve both good insulation performance and interface characteristics. A planarization layer 380 is disposed on the side of the protective layer 370 away from the substrate layer 10. Due to the significant step difference in the thin-film transistor array structure, failure to planarize it will lead to breakage or uneven thickness of the pixel electrode layer 390 formed above, resulting in uneven brightness or short circuits. The main function of the planarization layer 380 is to provide a smooth and flat surface. Its material is typically an organic resin with good flowability and light transmittance, such as acrylic resin or polyimide. High flatness is crucial for achieving high resolution and high contrast display effects. The pixel electrode layer 390 is disposed on the side of the planarization layer 380 away from the substrate layer 10. This layer needs to have high light transmittance and excellent conductivity. Therefore, the material of the pixel electrode layer 390 is preferably a transparent conductive oxide. The pixel electrode layer 390 is electrically connected to the drain 80 through a fifth contact via 3901 penetrating the planarization layer 380 and the protective layer 370.

[0067] This application also provides a display device, which includes a thin-film transistor, or a driving circuit, or a display panel as described above. This display device can be installed in any terminal with display functionality, such as a watch, mobile phone, virtual reality (VR) / augmented reality (AR) headset, laptop computer, tablet computer, television, automotive display, etc. Other common structures in this display device, such as common electrodes, encapsulation layers, touch sensors, polarizers, etc., can employ conventional technologies and materials in the art that are the same as or similar to those in existing display devices, ensuring technical compatibility and manufacturability. Specific details can be found in existing technologies, and will not be elaborated further here.

[0068] In this embodiment, by setting the Nth semiconductor layer (N≥2), the current transport path in the thin film transistor is optimized, the number of channels in the thin film transistor is increased, which is equivalent to increasing the channel width of the thin film transistor, thereby increasing the channel current of the thin film transistor to meet the needs of current high-end display panels.

[0069] While this application has been described herein with reference to specific embodiments, it should be understood that this application is not limited to the disclosed embodiments. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of this application as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A thin film transistor, characterized by comprising: Comprising: a substrate layer; a first semiconductor layer on one side of the substrate layer, the first semiconductor layer comprising a first source region, a first drain region, and a first channel between the first source region and the first drain region; a first insulating layer on a side of the first semiconductor layer away from the substrate layer, the first insulating layer covering the first semiconductor layer; a gate on a side of the first insulating layer away from the substrate layer; a second insulating layer on a side of the gate away from the substrate layer, the second insulating layer covering the gate; a second semiconductor layer on a side of the second insulating layer away from the substrate layer, the second semiconductor layer comprising a second source region, a second drain region, and a second channel between the second source region and the second drain region; a source-drain electrode, the source-drain electrode comprising a source electrode and a drain electrode; wherein the source electrode is electrically connected to the second source region, the drain electrode is electrically connected to the second drain region, the first source region is electrically connected to the source electrode, and the first drain region is electrically connected to the drain electrode.

2. The thin film transistor of claim 1, wherein: the first semiconductor layer and the second semiconductor layer are of the same conductivity type.

3. The thin film transistor of claim 2, wherein: the first semiconductor layer and the second semiconductor layer are of the same or different materials; preferably, the materials of the semiconductor layers comprise oxide semiconductor, low-temperature polysilicon, or amorphous silicon; preferably, the first semiconductor layer and the second semiconductor layer are of the same material.

4. The thin film transistor of claim 1, wherein: a projection of the gate on the substrate layer covers a projection of the first channel on the substrate layer; and a projection of the gate on the substrate layer covers a projection of the second channel on the substrate layer; preferably, a boundary of the gate near the first source region is aligned with a boundary of the first source region near the first channel; and a boundary of the gate near the first drain region is aligned with a boundary of the first drain region near the first channel.

5. The thin film transistor of claim 1, wherein: a projection of the first semiconductor layer on the substrate layer covers a projection of the gate on the substrate layer; and a projection of the second semiconductor layer on the substrate layer covers a projection of the gate on the substrate layer; preferably, a projection of the second source region on the substrate layer at least partially overlaps a projection of the first source region on the substrate layer; and a projection of the second drain region on the substrate layer at least partially overlaps a projection of the first drain region on the substrate layer.

6. The thin film transistor of claim 5, wherein: the first source region is electrically connected to the source electrode; and the first drain region is electrically connected to the drain electrode; preferably, the first source region is electrically connected to the second source region through a first contact via hole that penetrates the first insulating layer and the second insulating layer, and is electrically connected to the source electrode through the second source region; and the first drain region is electrically connected to the second drain region through a second contact via hole that penetrates the first insulating layer and the second insulating layer, and is electrically connected to the drain electrode through the second drain region. ​ 7. The thin film transistor according to claim 1, wherein Further comprising: the 3rd insulating layer to the 2nth insulating layer, the 2nd gate to the nth gate, the 3rd semiconductor layer to the n+1th semiconductor layer; wherein the 2m-1th insulating layer is located on the side of the mth semiconductor layer away from the base layer; the mth gate is located on the side of the 2m-1th insulating layer away from the base layer; the 2mth insulating layer is located on the side of the mth gate away from the base layer; the m+1th semiconductor layer is located on the side of the 2mth insulating layer away from the base layer, and the m+1th semiconductor layer comprises an m+1th source region, an m+1th drain region, and an m+1th channel located between the m+1th source region and the m+1th drain region; wherein the source electrode is electrically connected to the m+1th source region, and the drain electrode is electrically connected to the m+1th drain region, and the source electrode and the drain electrode are always located on the side of the semiconductor layer farthest away from the base layer in the thickness direction of the semiconductor layer (n is an integer greater than or equal to 2, and m is an integer greater than or equal to 2 and less than or equal to n).

8. The thin film transistor according to claim 7, wherein the n+1th semiconductor layer has the same conductivity type as the 1st semiconductor layer and the 2nd semiconductor layer.

9. A drive circuit, characterized by The thin film transistor according to any one of claims 1 to 8.

10. A display panel, characterized by, The thin film transistor according to any one of claims 1 to 8, or the drive circuit according to claim 9.

11. The display panel of claim 10, wherein, Further comprising: a protective layer located on the side of the source and drain electrodes away from the base layer; a planarization layer located on the side of the protective layer away from the base layer; a pixel electrode layer located on the side of the planarization layer away from the base layer, and the pixel electrode layer is electrically connected to the drain electrode through a third contact via hole penetrating through the planarization layer and the protective layer.

12. A display device, characterized by comprising: The thin film transistor according to any one of claims 1 to 8, or the drive circuit according to claim 9, or the display panel according to any one of claims 10 to 11.

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