Preparation method of super junction power device
By controlling the epitaxial layer growth rate and temperature or gas flow rate, a center-thick and edge-thin structure is formed during the fabrication of superjunction power devices, solving the wafer breakage problem caused by stress fluctuations in the CMP process, improving product yield and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-24
- Publication Date
- 2026-03-31
AI Technical Summary
In the manufacturing process of superjunction power devices, the uneven growth of single crystal silicon in deep trenches leads to uneven pressure distribution of the grinding head in the CMP process, which can easily cause wafer breakage and slippage, reducing product yield.
By controlling the growth rate of the epitaxial layer, which gradually decreases from the center to the edge of the substrate, a structure with a thick center and thin edges is formed, thus avoiding stress fluctuations and concentrations during the grinding process. This effect is achieved by using zoned heating or gas flow control.
It effectively eliminates stress fluctuations during the grinding process, prevents wafer breakage, improves product yield, reduces grinding costs, and meets the needs of large-scale mass production.
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Figure CN121772297A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for fabricating a superjunction power device. Background Technology
[0002] Superjunction power devices are power semiconductor devices with a superjunction withstand voltage layer. The withstand voltage layer adopts a periodically alternating doped PN junction structure, transforming the traditional resistive withstand voltage layer into a junction withstand voltage layer. This structure achieves charge balance and electric field regulation by introducing the reverse depletion characteristics of the PN junction, thereby breaking through the silicon limit relationship between the specific on-resistance and withstand voltage of traditional power devices, significantly reducing conduction losses, and enabling superjunction power devices to have high breakdown voltage and low conduction characteristics, and are widely used in semiconductor device products.
[0003] In the manufacturing process of superjunction power devices, it is usually necessary to etch deep trenches on the epitaxial layer on the surface of the silicon substrate, and then grow monocrystalline silicon in the deep trenches through a depressurized epitaxial process to achieve filling. The process of filling the deep trenches is usually accompanied by uneven overgrowth of monocrystalline silicon at the trench opening. Therefore, CMP process is required to grind and planarize the overgrown monocrystalline silicon layer to meet the flatness requirements of subsequent processes.
[0004] However, in existing technologies, the goal during the growth of a single-crystal silicon layer is to achieve a uniformly grown layer. This is impossible to achieve in actual production due to the inherent non-uniformity of the temperature and airflow fields within the reaction chamber. It is difficult to ensure a high degree of flatness on the surface of the overgrown silicon layer, leading to uneven pressure distribution in the grinding head during subsequent CMP processes, which can cause wafer breakage. For example, after the filling process, the wafer surface exhibits a thick-thin-thickness distribution. During grinding, there are severe stress fluctuations between the grinding head and the wafer surface, which can easily cause vibration and stress concentration. This is especially true in the transition zone between thicker and thinner areas, where wafer breakage and slippage are highly likely, reducing product yield. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method for fabricating a superjunction power device, which can effectively eliminate stress fluctuations during the grinding process after filling the grooves on the surface of the epitaxial layer, avoid stress concentration, reduce the risk of device breakage, and improve product yield.
[0006] To achieve the above and other related objectives, this application provides a method for fabricating a superjunction power device, comprising the following steps: Provide a substrate; A first epitaxial layer is formed on the substrate; A plurality of grooves spaced apart from each other are formed in the first epitaxial layer; A second epitaxial layer is formed on the first epitaxial layer to fill the groove, and the growth rate of the second epitaxial layer gradually decreases along the direction from the center to the edge of the substrate; The surface of the second epitaxial layer is planarized to expose the first epitaxial layer.
[0007] Optionally, in the step of forming the second epitaxial layer, the second epitaxial layer completely fills the groove and covers the first epitaxial layer, with the thickness of the second epitaxial layer protruding outward from the first epitaxial layer above the central region of the substrate as the first thickness, and the thickness of the second epitaxial layer protruding outward from the first epitaxial layer above the edge region of the substrate as the second thickness, the first thickness being greater than the second thickness, and the difference between the first thickness and the second thickness being 1 μm to 10 μm.
[0008] Optionally, in the step of forming the second epitaxial layer, the second epitaxial layer is grown and formed in the process chamber of the semiconductor growth apparatus, and the temperature in the process chamber is controlled to gradually decrease along the direction from the center to the edge of the substrate, so that the growth rate of the second epitaxial layer gradually decreases along the direction from the center to the edge of the substrate.
[0009] Optionally, in the step of forming the second epitaxial layer, the substrate surface has a central region, an intermediate region and an edge region in sequence along the direction from the center to the edge. The temperature of the central region of the substrate is 1000℃~1100℃, the temperature of the intermediate region of the substrate is 950℃~1050℃, and the temperature of the edge region of the substrate is 900℃~1000℃.
[0010] Optionally, in the step of forming the second epitaxial layer, the semiconductor growth apparatus is provided with a heating module for partitioning the process chamber to gradually reduce the temperature within the process chamber along the direction from the center to the edge of the substrate.
[0011] Optionally, in the step of forming the second epitaxial layer, the central region, intermediate region and edge region of the substrate are spaced apart from each other, and the heating module is used to make the temperature of the central region of the substrate 1050°C, the temperature of the intermediate region of the substrate 990°C and the temperature of the edge region of the substrate 900°C, so that the growth rate of the second epitaxial layer gradually decreases along the direction from the center to the edge of the substrate.
[0012] Optionally, in the step of forming the second epitaxial layer, the second epitaxial layer is grown in a process chamber of a semiconductor growth apparatus, and a selective gas is introduced into the process chamber to control the growth rate of the second epitaxial layer, such that the flow rate of the selective gas in the process chamber gradually increases along the direction from the center to the edge of the substrate, so that the growth rate of the second epitaxial layer gradually decreases along the direction from the center to the edge of the substrate.
[0013] Optionally, in the step of forming the second epitaxial layer, the substrate surface has a central region, an intermediate region, and an edge region in sequence along the direction from the center to the edge. The flow rate of the selective gas in the central region of the substrate is 900 sccm to 1000 sccm, the flow rate of the selective gas in the intermediate region of the substrate is 800 sccm to 900 sccm, and the flow rate of the selective gas in the edge region of the substrate is 700 sccm to 800 sccm.
[0014] Optionally, the central region, intermediate region, and edge region of the substrate are spaced apart from each other, such that the flow rate of the selective gas in the central region of the substrate is 950 sccm, the flow rate of the selective gas in the intermediate region of the substrate is 850 sccm, and the flow rate of the selective gas in the edge region of the substrate is 750 sccm, so that the growth rate of the second epitaxial layer gradually decreases along the direction from the center to the edge of the substrate.
[0015] Optionally, after planarizing the second epitaxial layer, the method further includes the following step: performing a preset fabrication process on the first epitaxial layer to form a preset power host structure.
[0016] As described above, compared with the prior art, the method for fabricating superjunction power devices provided in this application has at least the following beneficial effects: In the preparation method of the present invention, by gradually decreasing the growth rate of the second epitaxial layer from the center to the edge of the substrate surface, the formed second epitaxial layer gradually becomes thinner from the center to the edge. During the subsequent grinding process of the surface of the second epitaxial layer, it is possible to ensure that the surface of the second epitaxial layer in contact with the polishing pad has good flatness, prevent the high points and low points of the surface from contacting the polishing pad at the same time, and thus effectively eliminate stress fluctuations in the grinding process from the root, avoid stress concentration, prevent wafer breakage during the grinding process, and improve product yield. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 The diagram shown is a flowchart illustrating a method for fabricating a superjunction power device provided in this application.
[0019] Figure 2 The diagram shown is a schematic diagram of the structure in which a groove is formed on the first epitaxial layer in the preparation method provided in this application.
[0020] Figure 3 The diagram shown is a schematic diagram of the structure in which the second epitaxial layer is formed in the preparation method provided in this application.
[0021] Illustration of reference numerals in the attached diagram: 11. Substrate; 12. First epitaxial layer; 121. Groove; 13. Second epitaxial layer. Detailed Implementation
[0022] To make the technical objectives, technical solutions, and technical effects of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with embodiments. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0023] Therefore, the following detailed description of embodiments of this application is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0024] In the description of this application, it should be noted that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0025] In the description of this application, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.
[0026] Example 1 To address the problems in the background art, this invention provides a method for fabricating a superjunction power device, which can reduce the risk of cracking during the manufacturing process of the superjunction power device and improve the yield of the final product. (Refer to...) Figure 1 This method includes the following steps: S1. Provide a substrate 11; S2. A first epitaxial layer 12 is formed on the substrate 11; S3. A plurality of grooves 121 spaced apart from each other are formed on the first epitaxial layer 12; S4. A second epitaxial layer 13 is formed on the first epitaxial layer 12 to fill the groove 121, and the growth rate of the second epitaxial layer 13 gradually decreases from the center of the substrate 11 to the edge. S5. Planarize the surface of the second epitaxial layer 13 to expose the first epitaxial layer 12.
[0027] In this method, during the growth of the second epitaxial layer 13, the growth rate of the second epitaxial layer 13 is gradually reduced from the center to the edge of the substrate 11 surface, resulting in a gradual decrease in the thickness of the second epitaxial layer 13 from the center to the edge. During the subsequent polishing of the surface of the second epitaxial layer 13, the surface of the second epitaxial layer 13 in contact with the polishing pad can be guaranteed to have relatively good flatness, preventing high points and low points on the surface from contacting the polishing pad at the same time. This effectively eliminates stress fluctuations during the polishing process, avoids stress concentration in the transition area between high and low points, reduces or avoids problems such as wafer breakage during polishing, and improves the final product yield.
[0028] In step S1, the material of the substrate 11 can be any one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The material of the substrate 11 can also be sapphire, silicon carbide, gallium nitride, or other suitable materials. These will not be listed one by one in this embodiment.
[0029] In step S2, refer to Figure 2A first epitaxial layer 12 is formed on the surface of the substrate 11. Subsequently, a drain region of a superjunction power device can be formed on the back side of the substrate 11. A body region and a source region can be formed in the first epitaxial layer 12. Part of the first epitaxial layer 12 can also serve as part of the drift region of the superjunction power device.
[0030] The first epitaxial layer 12 can be formed by epitaxial process or other suitable process. The first epitaxial layer 12 has a first type of impurity ions. The first type of impurity ions can be N-type impurity ions, such as one or more of nitrogen ions, phosphorus ions, arsenic ions, and antimony ions, or P-type impurity ions, such as one or more of boron ions, aluminum ions, gallium ions, and indium ions.
[0031] The thickness of the first epitaxial layer 12 varies depending on the performance and type of the superjunction power device. In some embodiments, the thickness of the first epitaxial layer 12 is 5μm to 100μm, specifically, it can be 5μm, 25μm, 50μm, 75μm, 100μm or other suitable dimensions.
[0032] In step S3, refer to Figure 2 The first epitaxial layer 12 is etched to form several grooves 121 for use in subsequent processes to form a superstructure. The size and distribution of the grooves 121 can be set according to actual needs. It should be noted that the grooves 121 formed in the first epitaxial layer 12 do not penetrate the first epitaxial layer 12, so that the material layer subsequently filled in the grooves 121 does not contact the substrate 11.
[0033] In step S4, refer to Figure 3 A second epitaxial layer 13 is formed on the surface of the first epitaxial layer 12, and the second epitaxial layer 13 is overgrown to completely fill the groove 121 in the first epitaxial layer 12 and cover the first epitaxial layer 12. The second epitaxial layer 13 contains second type impurity ions, which have the opposite conductivity type to the first type impurity ions. In some embodiments, when the first impurity ion is an N-type impurity ion, the second impurity ion is a P-type impurity ion; in other embodiments, when the first impurity ion is a P-type impurity ion, the second impurity ion is an N-type impurity ion.
[0034] The second epitaxial layer 13 filled in the groove 121 is used to adjust the electric field in the entire first epitaxial layer 12. The second epitaxial layer 13 with second type impurity ions and the first epitaxial layer 12 with first type impurity ions form an alternating P-pillar and N-pillar structure. The lateral PN junction can balance the charge distribution, enhance the voltage resistance, and reduce the on-resistance.
[0035] In step S4, which forms the second epitaxial layer 13, the thickness of the second epitaxial layer 13 protruding outward from the first epitaxial layer 12 above the central region of the substrate 11 is defined as the first thickness h1, and the thickness of the second epitaxial layer 13 protruding outward from the first epitaxial layer 12 in the edge region of the substrate 11 is defined as the second thickness h2. The first thickness h1 is greater than the second thickness h2, and the difference between the first thickness h1 and the second thickness h2 is 1 μm to 10 μm. Specifically, the difference between the first thickness h1 and the second thickness h2 can be, for example, 1 μm, 3 μm, 5 μm, 7 μm, 9 μm, 10 μm, or other suitable values. Preferably, the difference between the first thickness h1 and the second thickness h2 is 1 μm to 3 μm.
[0036] By controlling the difference between the first and second thicknesses to be no less than 1 μm, it is possible to prevent the thickness difference between the central and edge regions of the second epitaxial layer 13 from being too small. This would cause the polishing pad to simultaneously contact both the high and low points of the uneven surface of the second epitaxial layer 13 during the polishing process, making it impossible to effectively eliminate stress fluctuations during polishing and thus increasing the risk of device breakage. Conversely, by controlling the difference between the first and second thicknesses to be no more than 10 μm, it is possible to prevent the thickness difference between the central and edge regions of the second epitaxial layer 13 from being too large, which would reduce the growth quality of the second epitaxial layer 13 and significantly increase the cost of subsequent polishing. Therefore, this method, by setting a suitable range for the difference between the first and second thicknesses, can effectively eliminate stress fluctuations during polishing, prevent stress concentration, and reduce or avoid the risk of device breakage while balancing high growth quality and low polishing cost of the second epitaxial layer 13.
[0037] In this embodiment, during step S4 to form the second epitaxial layer 13, the second epitaxial layer 13 is grown and formed in the process chamber of the semiconductor growth equipment. The temperature in the process chamber is controlled to gradually decrease from the center to the edge of the substrate 11, so that the growth rate of the second epitaxial layer 13 gradually decreases from the center to the edge of the substrate 11.
[0038] In some embodiments, the substrate 11 is a silicon substrate 11, and the second epitaxial layer 13 is a single-crystal silicon layer, which is deposited on the first epitaxial layer 12 using a semiconductor growth apparatus. In the step of forming the second epitaxial layer 13 in step S4, the surface of the substrate 11 has a central region, an intermediate region, and an edge region in sequence along the direction from the center to the edge. The temperature of the central region of the substrate 11 is 1000°C to 1100°C, the temperature of the intermediate region of the substrate 11 is 950°C to 1050°C, and the temperature of the edge region of the substrate 11 is 900°C to 1000°C. Specifically, the temperature fields in the three regions are, for example, 1100°C, 1050°C, and 1000°C, or 1050°C, 1000°C, and 950°C, or 1020°C, 970°C, and 920°C, or 1000°C, 950°C, and 900°C, or other suitable distribution forms. Based on the positive correlation between silicon epitaxial growth rate and temperature, by adjusting the temperature gradient above the substrate 11 in the process chamber, the temperature above the central region of the substrate 11 is made greater than the temperature above the edge region, thereby causing the growth rate of the second epitaxial layer 13 to gradually decrease from the center of the substrate 11 towards the edge.
[0039] Furthermore, in the step of forming the second epitaxial layer 13, a heating module is provided in the semiconductor growth equipment for partitioning the process chamber for heating so that the temperature in the process chamber gradually decreases from the center to the edge of the substrate 11.
[0040] Furthermore, in the step of forming the second epitaxial layer 13, the central region, the middle region and the edge region of the substrate 11 are spaced apart from each other. The heating module is used to make the temperature of the central region of the substrate 11 1050°C, the temperature of the middle region of the substrate 11 990°C and the temperature of the edge region of the substrate 11 900°C, thereby forming a temperature field distribution in the process chamber where the temperature gradually decreases from the center to the edge of the substrate 11, so that the growth rate of the second epitaxial layer 13 gradually decreases along the direction from the center to the edge of the substrate 11.
[0041] In this embodiment, after completing step S4, a semiconductor structure with a thick center and thin edges is obtained. Then, step S5 is performed, using a polishing device to planarize the second epitaxial layer 13, removing the second epitaxial layer 13 located on the surface of the first epitaxial layer 12 and exposing the first epitaxial layer 12. Since the second epitaxial layer 13 has a high center and low edges, during the polishing process using a polishing pad, the polishing pad first contacts the central region of the surface of the second epitaxial layer 13. As the polishing process continues, the contact area between the polishing pad and the surface of the second epitaxial layer 13 gradually expands from the center to the edge until the first epitaxial layer 12 is polished. Therefore, during the polishing process of the second epitaxial layer 13 in step S4, it is possible to prevent the polishing pad from simultaneously contacting multiple high and low points on the surface of the second epitaxial layer 13, thereby eliminating stress fluctuations during the CMP process from the root, avoiding stress concentration in the transition area between high and low points, and reducing or preventing problems such as device breakage during the polishing process.
[0042] After planarizing the second epitaxial layer 13 in step S5, the process further includes the following step: performing a preset fabrication process on the first epitaxial layer 12 to form a preset power host structure. The preset fabrication process can be determined based on the type of superjunction power device, which can be a MOSFET, IGBT, or other semiconductor power device. The corresponding preset fabrication process can be the fabrication process for MOSFET devices, the fabrication process for IGBT devices, or other corresponding types of fabrication processes, as detailed in existing technologies. Taking an IGBT device as an example, the power host structure can include structural layers such as an emitter region, emitter electrode, gate, collector region, and collector electrode.
[0043] In summary, this method forms a second epitaxial layer 13 that gradually thins from the center to the edge by adjusting the process parameters in a zoned and collaborative manner. During the subsequent grinding process of the second epitaxial layer 13, the problem of device breakage caused by stress fluctuations is fundamentally solved, significantly improving the product yield. At the same time, it can reduce the frequency of process adjustment caused by thickness distribution fluctuations, adapt to the needs of large-scale mass production, and does not require the addition of new equipment. The preset thickness distribution can be achieved simply by optimizing the parameters, avoiding the high cost investment caused by "modifying the chamber in pursuit of uniform thickness".
[0044] Example 2 This embodiment provides another method for fabricating a superjunction power device, which also includes steps S1 to S5 in Embodiment 1. The similarities with Embodiment 1 will not be repeated. The difference is that in step S4, the growth rate of the second epitaxial layer 13 is controlled by controlling the flow distribution of selective gas in the process chamber.
[0045] In this embodiment, during step S4, which involves forming the second epitaxial layer 13, the second epitaxial layer 13 is grown within the process chamber of a semiconductor growth apparatus. A selective gas is introduced into the process chamber to control the growth rate of the second epitaxial layer 13. A working gas and a carrier gas are also introduced into the process chamber to further grow and form the second epitaxial layer 13. The types of the selective gas, working gas, and carrier gas can be configured according to the type of the second epitaxial layer 13 and actual production needs, as detailed in existing technologies.
[0046] In an optional embodiment, the growth rate of the second epitaxial layer 13 is negatively correlated with the selective gas flow rate; that is, the higher the selective gas flow rate, the lower the growth rate of the second epitaxial layer 13, and vice versa. Specifically, taking the second epitaxial layer 13 containing monocrystalline silicon material as an example, the selective gas can be, for example, HCl. In the step of forming the second epitaxial layer 13, the flow rate of the selective gas in the process chamber is controlled to gradually increase along the direction from the center to the edge of the substrate 11, so that the growth rate of the second epitaxial layer 13 gradually decreases along the direction from the center to the edge of the substrate 11.
[0047] Further, in the step of forming the second epitaxial layer 13, the surface of the substrate 11 has a central region, an intermediate region, and an edge region sequentially along the direction from the center to the edge. The flow rate of the selective gas in the central region of the substrate 11 is 900 sccm to 1000 sccm, the flow rate of the selective gas in the intermediate region of the substrate 11 is 800 sccm to 900 sccm, and the flow rate of the selective gas in the edge region of the substrate 11 is 700 sccm to 800 sccm. Specifically, the selective gas flow rates of the three regions can be, for example, 1000 sccm, 900 sccm, and 800 sccm, or 950 sccm, 850 sccm, and 750 sccm, or 900 sccm, 800 sccm, and 700 sccm, or other suitable flow distribution methods.
[0048] Furthermore, a selective gas introduction module is provided within the process chamber for introducing selective gas into the process chamber in sections. The central region, intermediate region, and edge region of the substrate 11 are spaced apart from each other. The flow rate of the selective gas in the central region of the substrate 11 is controlled to be 950 sccm, the flow rate of the selective gas in the intermediate region of the substrate 11 is 850 sccm, and the flow rate of the selective gas in the edge region of the substrate 11 is 750 sccm, so that the growth rate of the second epitaxial layer 13 gradually decreases from the center to the edge of the substrate 11.
[0049] In this embodiment, by selectively adjusting the gas flow rate parameters in a zoned and coordinated manner, a second epitaxial layer 13 that gradually thins from the center to the edge can be formed. Therefore, the preparation method of this embodiment also has the beneficial effects of Embodiment 1.
[0050] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify, alter, or combine the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.
Claims
1. A method for fabricating a superjunction power device, characterized in that, Includes the following steps: Provide a substrate; A first epitaxial layer is formed on the substrate; Several grooves spaced apart from each other are formed in the first epitaxial layer; A second epitaxial layer is formed on the first epitaxial layer to fill the groove, and the growth rate of the second epitaxial layer gradually decreases along the direction from the center to the edge of the substrate; The surface of the second epitaxial layer is planarized to expose the first epitaxial layer.
2. The method for fabricating a superjunction power device according to claim 1, characterized in that, In the step of forming the second epitaxial layer, the second epitaxial layer completely fills the groove and covers the first epitaxial layer. The thickness of the second epitaxial layer protruding outward from the first epitaxial layer above the central region of the substrate is the first thickness, and the thickness of the second epitaxial layer protruding outward from the first epitaxial layer above the edge region of the substrate is the second thickness. The first thickness is greater than the second thickness, and the difference between the first thickness and the second thickness is 1 μm to 10 μm.
3. The method for fabricating a superjunction power device according to claim 1, characterized in that, In the step of forming the second epitaxial layer, the second epitaxial layer is grown in the process chamber of the semiconductor growth apparatus, and the temperature in the process chamber is controlled to gradually decrease along the direction from the center to the edge of the substrate, so that the growth rate of the second epitaxial layer gradually decreases along the direction from the center to the edge of the substrate.
4. The method for fabricating a superjunction power device according to claim 3, characterized in that, In the step of forming the second epitaxial layer, the substrate surface has a central region, an intermediate region and an edge region in sequence along the direction from the center to the edge. The temperature of the central region of the substrate is 1000℃~1100℃, the temperature of the intermediate region of the substrate is 950℃~1050℃, and the temperature of the edge region of the substrate is 900℃~1000℃.
5. The method for fabricating a superjunction power device according to claim 4, characterized in that, In the step of forming the second epitaxial layer, the semiconductor growth equipment is provided with a heating module for partitioning the process chamber to gradually reduce the temperature in the process chamber along the direction from the center of the substrate to the edge.
6. The method for fabricating a superjunction power device according to claim 5, characterized in that, In the step of forming the second epitaxial layer, the central region, intermediate region and edge region of the substrate are spaced apart from each other. The heating module is used to make the temperature of the central region of the substrate 1050°C, the temperature of the intermediate region of the substrate 990°C and the temperature of the edge region of the substrate 900°C, so that the growth rate of the second epitaxial layer gradually decreases along the direction from the center to the edge of the substrate.
7. The method for fabricating a superjunction power device according to claim 1, characterized in that, In the step of forming the second epitaxial layer, the second epitaxial layer is grown in a process chamber of a semiconductor growth apparatus. A selective gas is introduced into the process chamber to control the growth rate of the second epitaxial layer. The flow rate of the selective gas in the process chamber gradually increases from the center to the edge of the substrate, so that the growth rate of the second epitaxial layer gradually decreases from the center to the edge of the substrate.
8. The method for fabricating a superjunction power device according to claim 7, characterized in that, In the step of forming the second epitaxial layer, a central region, an intermediate region, and an edge region are sequentially formed on the surface of the substrate along the direction from the center to the edge. The flow rate of the selective gas in the central region of the substrate is 900 sccm to 1000 sccm, the flow rate of the selective gas in the intermediate region of the substrate is 800 sccm to 900 sccm, and the flow rate of the selective gas in the edge region of the substrate is 700 sccm to 800 sccm.
9. The method for fabricating a superjunction power device according to claim 8, characterized in that, The central region, intermediate region, and edge region of the substrate are spaced apart from each other, such that the flow rate of the selective gas in the central region of the substrate is 950 sccm, the flow rate of the selective gas in the intermediate region of the substrate is 850 sccm, and the flow rate of the selective gas in the edge region of the substrate is 750 sccm, so that the growth rate of the second epitaxial layer gradually decreases along the direction from the center to the edge of the substrate.
10. The method for fabricating a superjunction power device according to claim 1, characterized in that, After planarizing the second epitaxial layer, the process further includes the following steps: performing a preset fabrication process on the first epitaxial layer to form a preset power host structure.