Silicon-on-insulator semiconductor device and manufacturing method thereof
By designing specific trench structures and process steps in semiconductor devices, the thermal stress problem of silicon-on-insulator substrates in BCD process was solved, improving process yield and shortening development time.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-10
- Publication Date
- 2026-03-31
AI Technical Summary
Silicon-on-insulator substrates are susceptible to thermal stress in the BCD process, leading to problems such as bending and alignment errors. New processes need to be developed to reduce these problems and realize the BCD process.
In semiconductor devices, trench structures are designed, including trench sidewalls defined by a first well, a bottom surface defined by a buried oxide layer, and recessed portions provided between the sidewalls and the buried oxide layer. By removing the base substrate after a high-temperature process to form a silicon-on-insulator structure, the effects of thermal stress are reduced.
It improves the yield of semiconductor processes, shortens process development time, and reduces substrate bending and alignment errors caused by thermal stress.
Smart Images
Figure CN121772301A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a silicon-on-insulator semiconductor device and a method for manufacturing the same. Background Technology
[0002] The content described in this section is only to provide background information for this embodiment and does not constitute prior art.
[0003] Recently, silicon-on-insulator (SOI) substrates have been used in semiconductor devices, and bipolar CMOS (BCD) processes are performed on semiconductor devices that include SOI substrates. Typically, when performing BCD processes on semiconductor devices with SOI substrates, the BCD device formation process is performed after the epitaxial layer is grown on the SOI substrate.
[0004] On the other hand, silicon-on-insulator (SiO2) substrates are highly susceptible to thermal stress, but high-temperature thermal processes are required for epitaxial layer growth and BCD device fabrication. Therefore, SiO2 substrates may bend, and various problems caused by SiO2 substrates, such as alignment errors and wafer defects, may occur.
[0005] Furthermore, when performing BCD process on semiconductor devices that include silicon-on-insulator substrates, there is a need to redevelop a process for silicon-on-insulator substrates to replace the existing BCD process.
[0006] Therefore, there is a need for a technology that minimizes the problems caused by silicon-on-insulator (SiI) semiconductor devices and enables BCD processes. Summary of the Invention
[0007] The problem the invention aims to solve
[0008] The purpose of this invention is to provide a semiconductor device and a method thereof that can employ BCD process on a semiconductor device on a silicon-on-insulator substrate.
[0009] The purpose of this invention is not limited to the objectives mentioned above. Other objectives and advantages of this invention not mentioned can be understood through the following description and can be more clearly understood through embodiments of this invention. Furthermore, it will be readily understood that the objectives and advantages of this invention can be achieved through methods and combinations thereof within the scope of the claims.
[0010] means for solving problems
[0011] The semiconductor device of this invention includes: a substrate; a buried oxide layer disposed on the substrate; a first device region and a second device region disposed on the buried oxide layer; a trench disposed between the first device region and the second device region; and a device separator filling the trench to insulate the first device region and the second device region. The sidewalls of the trench are defined by a first well in the first device region, and the bottom surface of the trench is defined by the buried oxide layer. A portion of the first well in contact with the buried oxide layer includes a recessed portion recessed toward the sidewalls of the trench.
[0012] Furthermore, the recessed portion is disposed between the sidewall of the groove and the buried oxygen layer.
[0013] Furthermore, the sidewall of the trench extends from the upper part of the first device region toward the first point of the buried oxide layer and then bends toward the second point of the buried oxide layer, the second point being the point where the sidewall of the trench contacts the bottom surface.
[0014] Furthermore, the recessed portion is disposed between the portion of the sidewall that bends toward the second point and the buried oxygen layer.
[0015] Furthermore, the first point mentioned above is a point on the boundary where the buried oxygen layer and the first trap come into contact.
[0016] Furthermore, the first height from the third point of the buried oxygen layer between the first point and the second point to the sidewall of the trench is less than the second height from the first point to the sidewall of the trench.
[0017] Furthermore, the first width of the groove at the first position in the first position of the sidewall of the groove is greater than the second width of the bottom surface of the groove.
[0018] Furthermore, the buried oxide layer includes a device formation region, which includes the device diaphragm, the first device region, and the second device region. The width of the device formation region, the width of the buried oxide layer, and the width of the substrate are the same.
[0019] Furthermore, the width of the device formation area, the width of the buried oxide layer, and the width of the substrate are values measured along a direction parallel to the upper surface of the substrate.
[0020] Furthermore, the method for manufacturing the semiconductor device of the present invention includes the following steps:
[0021] A base substrate is provided, wherein a trench is formed on the base substrate and a device separator is formed to fill the trench and insulate a first device region and a second device region. The bottom surface of the front end (pre) of the trench is defined by a first surface of the base substrate. A device forming region is formed on the first surface of the base substrate, the device forming region including the device separator, the first device region, and the second device region. A carrier wafer is attached to a second surface of the device forming region, which is the opposite side of the first surface of the device forming region on which the base substrate is formed, with the device forming region as the center. The base substrate and the lower part of the trench, including the bottom surface of the front end of the trench, are removed. A buried oxide layer and a substrate are formed on the first surface of the device forming region. The carrier wafer is removed, wherein the bottom surface of the trench is defined by the buried oxide layer formed on the first surface of the device forming region.
[0022] Furthermore, the sidewall of the trench is defined by the first well in the first device region. By removing the lower part of the trench that includes the bottom surface of the front end of the trench, a recessed portion is formed in a part of the first well that is in contact with the buried oxide layer, which is recessed toward the sidewall of the trench.
[0023] Furthermore, the recessed portion is disposed between the sidewall of the groove and the buried oxygen layer.
[0024] Furthermore, by removing the lower part of the trench that includes the bottom surface of the front end of the trench, the sidewall of the trench extends from the second surface of the device forming region toward the first point of the buried oxide layer in the direction toward the first surface of the device forming region and then bends toward the second point of the buried oxide layer, the second point being the point where the sidewall of the trench and the bottom surface come into contact.
[0025] Furthermore, the recessed portion is part of the first well located between the first portion of the curved sidewall and the buried oxygen layer.
[0026] Furthermore, the first height from the third point of the buried oxygen layer between the first point and the second point to the sidewall of the trench is less than the second height from the first point to the sidewall of the trench.
[0027] Furthermore, the aforementioned base substrate also includes a wiring layer formed on the aforementioned device diaphragm.
[0028] Furthermore, the present invention also includes the step of forming a wiring layer on the second surface of the device forming region after removing the carrier wafer from the second surface of the device forming region.
[0029] Furthermore, the step of forming the buried oxide layer and the substrate on the first surface of the device forming region includes the following steps: after forming the buried oxide layer on the first surface of the device forming region, the substrate is attached to the buried oxide layer.
[0030] Furthermore, the step of forming the buried oxide layer and the substrate on the first surface of the device forming region includes the following steps: after forming the oxide layer on the substrate, attaching the oxide layer and the substrate in such a way that the first surface of the device forming region is in contact with the oxide layer.
[0031] Furthermore, the step of forming the buried oxide layer and the substrate on the first surface of the device forming region includes the following steps: forming a first oxide layer on the first surface of the device forming region; forming a second oxide layer on the substrate; and attaching the second oxide layer and the substrate on the first surface side of the device forming region in such a way that the first oxide layer on the first surface of the device forming region contacts the second oxide layer.
[0032] The effects of the invention
[0033] The semiconductor device and its manufacturing method of the present invention may include a silicon-on-insulator substrate and may employ a BCD process, thereby improving semiconductor process yield and shortening process development time.
[0034] The above content and the specific effects of the present invention will be described together in the process of explaining the specific embodiments. Attached Figure Description
[0035] Figure 1 This is a cross-sectional view used to illustrate an embodiment of the present invention, specifically a semiconductor device.
[0036] Figure 2 To show Figure 1 A cross-sectional view of the KK region.
[0037] Figure 3 To enlarge Figure 2 An enlarged view of region A in the image.
[0038] Figure 4 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0039] Figure 5 For illustrative purposes Figure 4 The sectional view of step S100 in the process.
[0040] Figure 6 for Figure 5 A magnified view of region B in the image.
[0041] Figure 7For illustrative purposes Figure 4 The diagram for step S200.
[0042] Figure 8 For illustrative purposes Figure 4 The diagram for step S300 in the process.
[0043] Figure 9 and Figure 10 For illustrative purposes Figure 4 The diagram for step S400.
[0044] Figure 11 For illustrative purposes Figure 4 The sectional view of step S100 in the process.
[0045] Figure 12 For illustrative purposes Figure 4 The diagram for step S200.
[0046] Figure 13 For illustrative purposes Figure 4 The diagram for step S300 in the process.
[0047] Figure 14 and Figure 15 For illustrative purposes Figure 4 The diagram for step S400. Detailed Implementation
[0048] The terms or words used in this specification and the scope of the invention claims should not be interpreted in their ordinary or dictionary sense. Based on the principle that inventors may define the concepts of terms or words to best illustrate their invention, they should be interpreted in accordance with the meaning and concept that conforms to the technical idea of the invention. Furthermore, the embodiments described in this specification and the structures shown in the accompanying drawings are merely one embodiment of the invention and do not fully represent the technical idea of the invention. It should be understood that at the time of this application, there were many equivalent technical solutions and numerous variations and applications that could replace them.
[0049] The terms "first," "second," "A," "B," etc., used in this specification and the claims of the invention can be used to describe various structural elements, but the aforementioned structural elements are not limited to the terms used. These terms are used only to distinguish one structural element from other structural elements. For example, without departing from the scope of the invention, a first structural element may be named a second structural element, and similarly, a second structural element may be named a first structural element. The term "and / or" includes a combination of multiple related descriptive items or one of multiple related descriptive items.
[0050] The terminology used in this specification and the claims is for illustrative purposes only and is not intended to limit the invention. Unless otherwise expressly indicated in the context, singular expressions include plural expressions. In this application, terms such as "comprising" or "possessing" should be understood as not precluding the presence or additional possibilities of features, numbers, steps, actions, structural elements, components, or combinations thereof described in the specification.
[0051] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.
[0052] Terms defined in commonly used dictionaries should be interpreted as having the same meaning in the context of the relevant art, and should not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this application. Furthermore, the various structures, steps, processes, or methods included in the various embodiments of the present invention can be shared to the extent that there is no technical contradiction between them.
[0053] The following is for reference Figure 1 , Figure 2 and Figure 3 This describes a semiconductor device according to an embodiment of the present invention.
[0054] Figure 1 This is a cross-sectional view used to illustrate an embodiment of the present invention, specifically a semiconductor device. Figure 2 To show Figure 1 A cross-sectional view of the KK region. Figure 3 To enlarge Figure 2 An enlarged view of region A in the image.
[0055] Reference Figure 1 The semiconductor device in this embodiment of the invention may include a substrate 100, a buried oxide layer 110, a device formation region 120, and a wiring layer 130.
[0056] The substrate 100 may be a silicon substrate. The buried oxide layer 110 may be disposed on the substrate 100. A silicon-on-insulator structure may be formed through the substrate 100 and the buried oxide layer 110.
[0057] Device formation region 120 may be disposed on buried oxide layer 110. Multiple devices may be formed in device formation region 120. For example, multiple devices formed by BCD process may be formed in device formation region 120.
[0058] The wiring layer 130 can be disposed on the device forming area 120.
[0059] For example, the width WW of the substrate 100, the buried oxide layer 110, the device formation region 120, and the wiring layer 130 can all be the same. The width WW can be a value measured along a direction parallel to the upper surface 100U of the substrate 100. As will be described later, the semiconductor device of this embodiment of the invention forms multiple devices on a base substrate (e.g., a bulk silicon substrate) using a BCD process. After the multiple devices are formed, the buried oxide layer 110 and the substrate 100 are formed. Therefore, the width WW of the substrate 100, the buried oxide layer 110, the device formation region 120, and the wiring layer 130 can all be the same.
[0060] Reference Figure 2 and Figure 3 The device forming region 120 may include multiple device regions. For example, the device forming region 120 may include a first device region R1 and a second device region R2.
[0061] The first device region R1 and the second device region R2 can be a portion of the device formation region 120 disposed on the buried oxide layer 110. The same or different devices can be formed in the first device region R1 and the second device region R2. For example, devices formed by BCD process can be disposed in the first device region R1 and the second device region R2. In the accompanying drawings, for clarity, illustrations of the devices formed in each device region are omitted.
[0062] The first device region R1 may include a first well WL1. The second device region R2 may include a second well WL2. For example, the first well WL1 and the second well WL2 may contain silicon.
[0063] The first device region R1 and the second device region R2 can be insulated by a device separator DTI. The device separator DTI can be disposed within a trench TR. The trench TR can be disposed between the first device region R1 and the second device region R2. The trench TR can be disposed within the device formation region 120 extending from the second surface 120b to the first surface 120a. The trench TR can expose the buried oxide layer 110. The sidewall 211 of the trench TR can be defined by a first well WL1. The bottom surface 213 of the trench TR can be defined by the buried oxide layer 110.
[0064] The device diaphragm DTI can be configured to fill the trench TR. The device diaphragm DTI may include a sidewall oxide film 201 and an insulating material 203. The sidewall oxide film 201 may be configured along the sidewall 211 of the trench TR. The insulating material 203 may be configured on the sidewall oxide film 201 to fill the trench TR.
[0065] For example, the sidewall 211 of the trench TR may have an inclination. The sidewall 211 of the trench TR may extend from the upper part of the first device region R1 toward a first point P1 toward the buried oxide layer 110 and then bend toward a second point P2 to contact the buried oxide layer 110.
[0066] The upper part of the first device region R1 may be a portion of the first device region R1 that includes the boundary of the device formation region 120 and the wiring layer 130. The sidewall 211 of the trench TR may extend from the second surface 120b of the device formation region 120 toward the first point P1 and then bend toward the second point P2 to contact the buried oxide layer 110.
[0067] The first point P1 can be a point on the buried oxide layer 110. For example, the first point P1 can be a point on the boundary where the buried oxide layer 110 contacts the first well WL1. For example, when a line with a predetermined inclination is drawn from a point on the second surface 120b of the device formation region 120 starting from the sidewall 211 of the trench TR toward the buried oxide layer 110, the first point P1 can be the point where the line contacts the buried oxide layer 110. The predetermined inclination can be the inclination of the sidewall 211 of the trench TR on the upper part of the first device region R1.
[0068] Although the invention has been described with the sidewall 211 of the trench TR having an inclination, it is not limited thereto. For example, the sidewall 211 of the trench TR may be perpendicular to the upper surface 100U of the substrate 100. In this case, the sidewall 211 of the trench TR may extend toward a first point P1 and then bend toward a second point P2 to contact the buried oxide layer 110. In this case, assuming that the sidewall 211 of the trench TR extends to the buried oxide layer 110, the first point P1 may be the point where the buried oxide layer 110 contacts the sidewall 211 of the trench TR.
[0069] The second point P2 can be a point on the buried oxide layer 110 that is separated from the first point P1. The second point P2 can be the point where the sidewall 211 of the trench TR contacts the bottom surface 213 of the trench TR. The second point P2 can be the point where the sidewall 211 of the trench TR, the bottom surface 213 of the trench TR, and the buried oxide layer 110 contact each other.
[0070] The first width W1 of the groove TR at a first position PP1 in the sidewall 211 of the groove TR can be greater than the second width W2 of the bottom surface 213 of the groove TR. The first position PP1 can be any position on the sidewall 211 of the groove TR. The second width W2 can be the width of the bottom surface 213 of the groove TR measured from the second point P2.
[0071] As the sidewall 211 of the trench TR extends from the upper part of the first device region R1 toward the first point P1 and then bends toward the second point P2 to contact the buried oxide layer 110, the first well WL1 may include a recessed portion 150. For example, a portion WL1P of the first well WL1 that contacts the portion 211P of the sidewall 211 of the trench TR that bends toward the second point P2 may include a recessed portion 150. The portion 211P may be a part of the sidewall 211 of the trench TR. The recessed portion 150 may be a part of the first well WL1 that contacts the portion 211P of the sidewall 211 of the trench TR. The portion 211P of the sidewall 211 of the trench TR may be a portion from point PP2 on the sidewall 211 that is the point on the sidewall 211 that extends from the upper part of the first device region R1 toward the first point P1 at a predetermined inclination and then bends toward the second point P2 due to a change in the predetermined inclination.
[0072] A portion WL1P of the first well WL1 may include the part of the first well WL1 that contacts the buried oxide layer 110. The portion WL1P of the first well WL1 may be a part of the first well WL1 extending from the buried oxide layer 110 to any height. The portion WL1P of the first well WL1 may include a recessed portion 150. The recessed portion 150 may contact the buried oxide layer 110.
[0073] The recessed portion 150 may be provided between the sidewall 211 of the trench TR and the buried oxide layer 110. For example, the recessed portion 150 may be provided between a portion 211P of the sidewall 211 of the trench TR and the buried oxide layer 110.
[0074] The first height H1 from the third point P3 to the sidewall 211 of the trench TR (e.g., portion 211P of the sidewall 211) can be less than the second height H2 from the first point P1 to the sidewall 211 of the trench TR (e.g., portion 211P of the sidewall 211). For example, the first height H1 can be the height of the recessed portion 150 from the third point P3 to the sidewall 211 of the trench TR, and the second height H2 can be the height of the recessed portion 150 from the first point P1 to the sidewall 211 of the trench TR. The third point P3 can be a point on the boundary where the buried oxide layer 110 between the first point P1 and the second point P2 contacts the first well WL1.
[0075] As the sidewall 211 of the trench TR of the device diaphragm (DTI) in the semiconductor device of the present invention includes a portion 211P, it may include a recessed portion 150. According to the semiconductor device of the present invention, after performing a BCD process on the device formation region 120 on a base substrate (e.g., a bulk silicon substrate), the lower portion of the trench TR may be removed during the step of removing the base substrate to form a silicon-on-insulator structure by forming a buried oxide layer 110 and a substrate 100, thereby exposing the recessed portion 150 as the sidewall 211 of the trench TR includes a portion 211P.
[0076] The following is for reference Figures 4 to 15 A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. For clarity, content that is repeated in the previous description will be abbreviated or omitted.
[0077] Figure 4 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0078] Reference Figure 4 The method for manufacturing a semiconductor device according to embodiments of the present invention may include step S100 of providing a base substrate. For example, the base substrate may have trenches, device separators, and device formation regions formed thereon. In several embodiments, a wiring layer on the device formation regions may also be formed on the base substrate. Matters related to the base substrate will be referred to... Figure 5 and Figure 11 This will be explained in the following content.
[0079] The semiconductor device manufacturing method of this embodiment may include step S200 of attaching a carrier wafer to the second side of the device formation region. A base substrate may be formed on the first side of the device formation region, and the carrier wafer may be attached to the second side of the device formation region, which is the opposite side of the first side.
[0080] The semiconductor device manufacturing method of this embodiment may include step S300, which involves removing a base substrate and the lower portion of a trench. When the base substrate is removed from the first surface of the device formation region, the lower portion of the trench formed on the first surface side of the device formation region may also be removed.
[0081] The semiconductor device manufacturing method of this invention may include step S400, which involves forming a buried oxide layer and a substrate on a first surface of the device forming region.
[0082] The method for manufacturing a semiconductor device according to an embodiment of the present invention may include step S500 of removing a carrier wafer from the second side of the device forming region.
[0083] Figures 5 to 10 For illustrating the manufacturing method of a semiconductor device according to several embodiments of the present invention Figure 4A cross-sectional view of multiple steps in the process. Figure 5 For illustrative purposes Figure 4 The sectional view of step S100 in the process. Figure 6 for Figure 5 A magnified view of region B in the image.
[0084] Reference Figure 4 , Figure 5 and Figure 6 A device formation region 120 and a wiring layer 130 may be formed on a base substrate 300. The device formation region 120 may include a first device region R1 and a second device region R2. The device formation region 120 may include a device separator DTI that insulates the first device region R1 and the second device region R2 between them. The device separator DTI may be formed on a first surface 300a of the base substrate 300. The device separator DTI may be formed in a trench TR by filling the trench TR.
[0085] The trench TR can be formed within the device formation region 120 in a manner that penetrates the device formation region 120 and exposes the first surface 300a of the base substrate 300. The sidewalls 211 of the trench TR can be defined by the first well WL1 and the second well WL2. The front bottom surface 213p of the trench TR can be defined by the first surface 300a of the base substrate 300. The lower portion TL of the trench TR can be a part of the trench TR including the front bottom surface 213p.
[0086] The sidewall 211 of the trench TR in the lower TL of the trench TR can be bent from the device diaphragm DTI toward the first well WL1. The sidewall 211 of the trench TR in the lower TL of the trench TR can be bent from the device diaphragm DTI toward the second well WL2.
[0087] Figure 7 For illustrative purposes Figure 4 The diagram for step S200.
[0088] Reference Figure 4 and Figure 7 It can be flipped Figure 6 A semiconductor device is attached to a carrier wafer CW on a wiring layer 130. A base substrate 300 may be formed on a first surface 120a of a device formation region 120, and a wiring layer 130 may be formed on a second surface 120b of the device formation region 120. The carrier wafer CW may be attached to the second surface 120b side of the device formation region 120. The device formation region 120 may be disposed between the base substrate 300 and the carrier wafer CW.
[0089] Figure 8 For illustrative purposes Figure 4 The diagram for step S300 in the process.
[0090] Reference Figure 4 and Figure 8 The base substrate 300 can be removed. When the base substrate 300 is removed, the lower part TL of the trench TR, including the front bottom surface 213p of the trench TR, can also be removed.
[0091] Figure 9 and Figure 10 For illustrative purposes Figure 4 The diagram for step S400.
[0092] Reference Figure 4 and Figure 9 A buried oxide layer 110 can be formed on the first surface 120a of the device forming region 120 where the base substrate 300 and the lower part TL of the trench TR are removed. The bottom surface 213 of the trench TR is reformed by removing the lower part TL of the trench TR, which includes the front bottom surface 213p of the trench TR. The bottom surface 213 of the trench TR can be defined by the buried oxide layer 110.
[0093] Reference Figure 4 and Figure 10 It can be flipped Figure 9 Semiconductor devices are attached to substrate 100. This can form a silicon-on-insulator structure. Figure 10 The magnified view of region A in the image can be compared with... Figure 3 same.
[0094] A recessed portion 150, recessed toward the sidewall 211 of the trench TR, can be formed by removing a portion WL1P of the first well that is in contact with the first well WL1 and the buried oxide layer 110. The recessed portion 150 can be formed between the sidewall 211 of the trench TR and the buried oxide layer 110.
[0095] The buried oxide layer 110 can be disposed between the device formation region 120 and the substrate 100 by providing a substrate 100 on the first surface 120a side of the device formation region 120. Afterwards, the carrier wafer CW can be removed. The attached diagram after removing the carrier wafer CW is comparable to... Figure 2 same.
[0096] Figures 11 to 15 For illustrating the manufacturing method of a semiconductor device according to several embodiments of the present invention Figure 4 A cross-sectional view of multiple steps in the process. Figure 11 For illustrative purposes Figure 4 The sectional view of step S100 in the process.
[0097] Reference Figure 4 and Figure 11 A device formation region 120 and a front-end wiring layer 130p can be formed on the base substrate 300. Figure 11The magnified view of region B in the image can be compared with... Figure 6 same.
[0098] Figure 12 For illustrative purposes Figure 4 The diagram for step S200.
[0099] Reference Figure 4 and Figure 12 It can be flipped Figure 11 A semiconductor device is used to attach a carrier wafer CW to the front-end wiring layer 130p. A base substrate 300 may be formed on a first surface 120a of the device formation region 120, and a front-end wiring layer 130p may be formed on a second surface 120b of the device formation region 120. The carrier wafer CW may be attached to the second surface 120b side of the device formation region 120. The device formation region 120 may be disposed between the base substrate 300 and the carrier wafer CW.
[0100] Figure 13 For illustrative purposes Figure 4 The diagram for step S300 in the process.
[0101] Reference Figure 4 and Figure 13 The base substrate 300 can be removed. When the base substrate 300 is removed, the lower part TL of the trench TR, which includes the front bottom surface 213p of the trench TR, can also be removed.
[0102] Figure 14 and Figure 15 For illustrative purposes Figure 4 The diagram for step S400.
[0103] Reference Figure 4 and Figure 14 A buried oxide layer 110 can be formed on the first surface 120a of the device formation region 120 where the base substrate 300 and the lower TL of the trench TR are removed. The bottom surface 213 of the trench TR can be reformed by removing the lower TL of the trench TR, which includes the front bottom surface 213p of the trench TR. The bottom surface 213 of the trench TR can be defined by the buried oxide layer 110.
[0104] Reference Figure 4 and Figure 15 It can be flipped Figure 14 Semiconductor devices are attached to substrate 100. This can form a silicon-on-insulator structure. Figure 14 The magnified view of region A in the image can be compared with... Figure 3 same.
[0105] The buried oxide layer 110 can be disposed between the device formation region 120 and the substrate 100 by providing a substrate 100 on the first surface 120a side of the device formation region 120. Afterwards, the carrier wafer CW can be removed. After removing the carrier wafer CW, a wiring layer 130 including wiring, connectors, and / or vias can be formed on the front-end wiring layer 130p. A cross-sectional view of the wiring layer 130 formed after removing the carrier wafer CW can be compared with... Figure 2 same.
[0106] In several embodiments, such as Figure 8 and Figure 13 As shown, after removing the base substrate 300, an oxide layer 110 can be attached to the substrate 100 on which the buried oxide layer 110 is formed. Figure 8 and Figure 13 Semiconductor devices in [the context]. For example, replacing [other devices]. Figure 9 and Figure 14 In the steps described, after the oxide layer is formed on the substrate 100, Figure 8 and Figure 13 The semiconductor device can be attached in such a way that the first surface 120a of the device formation region 120 contacts the buried oxide layer 110, which is an oxide layer. This can be achieved by attaching it to a substrate 100 on which the oxide layer is formed. Figure 8 and Figure 13 In a semiconductor device, a buried oxide layer 110, which is an oxide layer, is formed between the device formation region 120 and the substrate 100, thereby forming a silicon-on-insulator structure.
[0107] In several embodiments, such as Figure 8 and Figure 13 As shown, after removing the base substrate 300, it is possible to... Figure 8 and Figure 13 A first oxide layer is formed on the first surface 120a of the device formation region 120, and a second oxide layer may be formed on the substrate 100. The second oxide layer and the substrate 100 are attached to the first surface 120a side of the device formation region 120 in such a way that the first oxide layer and the second oxide layer are in direct contact with each other. A buried oxide layer 110 can be formed by bringing the first oxide layer and the second oxide layer into contact with each other.
[0108] According to the semiconductor device manufacturing method of the present invention, a silicon-on-insulator structure is formed after forming multiple devices in each device region of the device formation region 120 in a state with a base substrate 300 attached, thereby preventing the silicon-on-insulator substrate from bending due to high-temperature thermal processes.
[0109] The above description is merely an illustrative explanation of the technical concept of this embodiment. Those skilled in the art can implement various modifications and variations without departing from the essential characteristics of this embodiment. Therefore, this embodiment is used to illustrate the technical concept of this embodiment, not to limit it. The scope of the technical concept of this embodiment is not limited to these embodiments. The protection scope of this embodiment should be interpreted by the appended claims, and all technical concepts within the equivalent scope should be interpreted as included within the scope of the claims of this embodiment.
Claims
1. A silicon-on-insulator semiconductor device, characterized in that, include: substrate; An oxide layer is disposed on the aforementioned substrate; The first device region and the second device region are disposed on the aforementioned buried oxide layer; A trench is disposed between the first device region and the second device region; as well as A device diaphragm fills the aforementioned trenches, insulating the first device region and the second device region. The sidewalls of the aforementioned trench are defined by the first well in the aforementioned first device region. The bottom surface of the aforementioned trench is defined by the aforementioned buried oxygen layer. A portion of the first well that is in contact with the buried oxygen layer includes a recessed portion that is recessed toward the sidewall of the trench.
2. The silicon-on-insulator semiconductor device according to claim 1, characterized in that, The recessed portion is disposed between the sidewall of the trench and the buried oxygen layer.
3. The silicon-on-insulator semiconductor device according to claim 1, characterized in that, The sidewall of the trench extends from the upper part of the first device region toward the first point of the buried oxide layer and then bends toward the second point of the buried oxide layer. The second point mentioned above is the point where the sidewall and bottom surface of the trench come into contact.
4. The silicon-on-insulator semiconductor device according to claim 3, characterized in that, The recessed portion is located between the portion of the sidewall that bends toward the second point and the buried oxygen layer.
5. The silicon-on-insulator semiconductor device according to claim 3, characterized in that, The first point mentioned above is a point on the boundary where the buried oxygen layer and the first trap come into contact.
6. The silicon-on-insulator semiconductor device according to claim 3, characterized in that, The first height from the third point of the buried oxygen layer between the first point and the second point to the sidewall of the trench is less than the second height from the first point to the sidewall of the trench.
7. The silicon-on-insulator semiconductor device according to claim 1, characterized in that, The first width of the groove at a first position on the sidewall of the groove is greater than the second width of the bottom surface of the groove.
8. The silicon-on-insulator semiconductor device according to claim 1, characterized in that, The buried oxide layer includes a device formation region, which comprises the device diaphragm, the first device region, and the second device region. The width of the device formation area, the width of the buried oxide layer, and the width of the substrate are the same.
9. The silicon-on-insulator semiconductor device according to claim 8, characterized in that, The width of the device formation area, the width of the buried oxide layer, and the width of the substrate are values measured along a direction parallel to the upper surface of the substrate.
10. A method for manufacturing a silicon-on-insulator semiconductor device, characterized in that, Includes the following steps: A base substrate is provided, wherein a trench is formed on the base substrate and a device separator is formed to fill the trench and insulate a first device region and a second device region. The bottom surface of the front end of the trench is defined by a first surface of the base substrate. A device forming region is formed on the first surface of the base substrate, wherein the device forming region includes the device separator, the first device region and the second device region. With the device formation region as the center, a carrier wafer is attached to the second side of the device formation region, which is opposite to the first side of the device formation region on which the base substrate is formed. Remove the aforementioned base substrate and the lower part of the trench that includes the aforementioned front end bottom surface of the trench. A buried oxide layer and a substrate are formed on the first surface of the aforementioned device formation region; and Remove the aforementioned carrier wafer, The bottom surface of the trench can be defined by the buried oxide layer formed on the first surface of the device forming region.
11. The method for manufacturing a silicon-on-insulator semiconductor device according to claim 10, characterized in that, The sidewalls of the aforementioned trench are defined by the first well in the aforementioned first device region. By removing the lower part of the trench that includes the bottom surface of the front end of the trench, a recessed portion is formed in a portion of the first well that is in contact with the buried oxygen layer, recessed toward the sidewall of the trench.
12. The method for manufacturing a silicon-on-insulator semiconductor device according to claim 11, characterized in that, The recessed portion is disposed between the sidewall of the trench and the buried oxygen layer.
13. The method for manufacturing a silicon-on-insulator semiconductor device according to claim 10, characterized in that, By removing the lower portion of the trench that includes the bottom surface of the front end of the trench, the sidewall of the trench extends from the second surface of the device forming region toward the first surface of the device forming region toward the first point of the buried oxide layer and then bends toward the second point of the buried oxide layer, thereby forming a recessed portion. The second point mentioned above is the point where the sidewall and bottom surface of the trench come into contact.
14. The method for manufacturing a silicon-on-insulator semiconductor device according to claim 13, characterized in that, The recessed portion is part of the first well located between the first portion of the curved sidewall and the buried oxygen layer.
15. The method for manufacturing a silicon-on-insulator semiconductor device according to claim 13, characterized in that, The first height from the third point of the buried oxygen layer between the first point and the second point to the sidewall of the trench is less than the second height from the first point to the sidewall of the trench.
16. The method for manufacturing a silicon-on-insulator semiconductor device according to claim 10, characterized in that, The aforementioned base substrate also includes a wiring layer formed on the aforementioned device diaphragm.
17. The method for manufacturing a silicon-on-insulator semiconductor device according to claim 10, characterized in that, It also includes the step of forming a wiring layer on the second surface of the device forming region after removing the carrier wafer from the second surface of the device forming region.
18. The method for manufacturing a silicon-on-insulator semiconductor device according to claim 10, characterized in that, The step of forming the buried oxide layer and the substrate on the first surface of the device forming region includes the following steps: after forming the buried oxide layer on the first surface of the device forming region, the substrate is attached to the buried oxide layer.
19. The method for manufacturing a silicon-on-insulator semiconductor device according to claim 10, characterized in that, The step of forming the buried oxide layer and the substrate on the first surface of the device forming region includes the following steps: after forming the oxide layer on the substrate, attaching the oxide layer and the substrate in such a way that the first surface of the device forming region is in contact with the oxide layer.
20. The method for manufacturing a silicon-on-insulator semiconductor device according to claim 10, characterized in that, The steps of forming the buried oxide layer and the substrate on the first surface of the device formation region include the following steps: A first oxide layer is formed on the first surface of the device formation region described above; A second oxide layer is formed on the above-mentioned substrate; and The second oxide layer and the substrate are attached to the first side of the device formation region in such a way that the first oxide layer on the first side of the device formation region comes into contact with the second oxide layer.