Lateral high voltage semiconductor device and manufacturing method thereof

Abstract

The invention relates to a lateral high voltage semiconductor device and a method of manufacturing the same. The semiconductor device includes: a semiconductor body having a front side and a rear side opposite the front side; a device region at a front side within the semiconductor body, wherein the device region comprises at least one lateral semiconductor element; and a first doped region of the second conductivity type between the device region and the back side, wherein the first doped region overlaps a first portion of the back side. The semiconductor device further includes at least one second doped region within the semiconductor body and an insulating layer at least partially covering a back side of the semiconductor body, where the at least one second doped region overlaps a second portion of the back side, where the first doped region is arranged between the device region and the at least one second doped region. The at least one second doped region differs from the first doped region in at least one of the following: a doping concentration differs by at least 20% and / or doped conductivity types differ. And the first part and the second part on the rear side are transversely overlapped with the insulating layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for manufacturing such semiconductor devices. Specifically, this disclosure relates to semiconductor devices having improved doping configuration and insulating structure on the back side, achieving enhanced electrical performance and reliability, and methods for manufacturing such devices with precise control over doping distribution and insulating layer placement. Background Technology

[0002] High-voltage semiconductor devices in CMOS (Complementary Metal-Oxide-Semiconductor) technology form an interface between a standard CMOS device with an input voltage up to 5 V on one side and an industrial or consumer circuit operating at a signal voltage level higher than 30 V on the other. Applications for such semiconductor devices exist in all types of power conversion and electrical drives up to the kV range, such as in power converters, robotics, and the automotive industry. High-voltage semiconductor devices typically consist of a low-voltage section operating in a low-voltage domain and a high-voltage section operating in a high-voltage domain. In the low-voltage section, most signal processing is performed at a low operating voltage. The high-voltage section operates at a higher voltage level. The low-voltage and high-voltage sections provide a signal interface for power semiconductors using higher voltage levels and / or with higher current drive and absorption capabilities. The potentials in the different voltage domains can differ by several 100 Vs to approximately 1000 V. An example of such a high-voltage semiconductor device is a gate driver circuit. Gate driver circuits enable microcontrollers or DSPs (Digital Signal Processors) to efficiently turn power semiconductor switches on and off. Such semiconductor devices include high-voltage semiconductor elements used to exchange power and / or electrical signals between CMOS circuits in different voltage domains.

[0003] There has always been a need to improve signal transmission in semiconductor devices with HV semiconductor elements with minimal additional effort. Summary of the Invention

[0004] High-voltage semiconductor devices typically include a high-potential transition region formed between a first doped region associated with a low-voltage portion and a second doped region associated with a high-voltage portion. LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) includes a drain extension region extending into the potential transition region, wherein the drain extension is not necessarily laterally diffused, but can also be formed by shallow ion implantation. HV diodes include an anode extension region extending into the potential transition region. The extension region can increase the parasitic capacitance of the HV semiconductor device and the semiconductor volume from which leakage current can be collected.

[0005] This disclosure relates to a semiconductor device comprising: a semiconductor body having a front side and a rear side opposite to the front side; a device region within the semiconductor body at the front side, wherein the device region includes at least one lateral semiconductor element; and a first doped region having a second conductivity type between the device region and the rear side, wherein the first doped region overlaps with a first portion of the rear side. The semiconductor device further comprises: at least one second doped region within the semiconductor body, wherein the at least one second doped region overlaps with a second portion of the rear side, wherein the first doped region is disposed between the device region and the at least one second doped region; and an insulating layer that at least partially covers the rear side of the semiconductor body. The at least one second doped region differs from the first doped region in at least one of the following aspects: a doping concentration difference of at least 20%, and / or a different conductivity type. In other words, the at least one second doped region differs from the first doped region in doping concentration by at least 20%, and / or the conductivity type of the at least one second doped region is opposite to that of the first doped region. Both the first portion and the second portion of the rear side overlap laterally with the insulating layer.

[0006] This disclosure relates to a method for manufacturing a semiconductor device, the method comprising the steps of: providing a semiconductor body having a front side and a rear side opposite to the front side, a device region within the semiconductor body at the front side, and a first doped region having a second conductivity type between the device region and the rear side, wherein the device region includes at least one lateral semiconductor element, and wherein the first doped region overlaps with a first portion of the rear side; forming at least one second doped region within the semiconductor body, wherein the at least one second doped region overlaps with a second portion of the rear side, wherein the first doped region is disposed between the device region and the at least one second doped region; and forming an insulating layer that at least partially covers the rear side of the semiconductor body. The at least one second doped region differs from the first doped region in at least one of the following aspects: a doping concentration difference of at least 20%, and / or a different conductivity type. Both the first portion and the second portion of the rear side laterally overlap with the insulating layer.

[0007] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and viewing the accompanying drawings.

[0008] A first aspect of the present invention provides a semiconductor device comprising: a semiconductor body having a front side and a rear side opposite to the front side; a device region within the semiconductor body at the front side, wherein the device region includes at least one lateral semiconductor element; a first doped region having a second conductivity type between the device region and the rear side, wherein the first doped region overlaps with a first portion of the rear side; at least one second doped region within the semiconductor body, wherein the at least one second doped region overlaps with a second portion of the rear side, wherein the first doped region is disposed between the device region and the at least one second doped region; and an insulating layer at least partially covering the rear side of the semiconductor body; wherein the at least one second doped region differs from the first doped region in at least one of the following aspects: a difference in doping concentration of at least 20%, and / or a difference in conductivity type; wherein both the first portion and the second portion of the rear side overlap laterally with the insulating layer.

[0009] This topic describes semiconductor devices with specific structural and material properties. A “semiconductor device” is an electronic component that utilizes the electronic properties of a semiconductor material (e.g., silicon) to perform its function. A “semiconductor body” is the physical structure of the device, typically made of a semiconductor material, and the “semiconductor body” has a “front side” and a “back side,” which are opposing surfaces of the body. A “device region” is a specific area within the semiconductor body located on the front side, in which at least one “lateral semiconductor element” is formed. A lateral semiconductor element can refer to a component that operates with current flowing parallel to the surface of the semiconductor body, such as a transistor (e.g., a MOSFET, a junction transistor) or a diode.

[0010] A "first doped region" is a portion of the semiconductor body that has been intentionally implanted with impurities to produce a "second conductivity type". The doping of the first doped region can be the base doping of the semiconductor body. The first doped region is located between the device region and the back side, and overlaps with a specific region on the back side (referred to as the "first portion"). A "second doped region" is another doped region within the semiconductor body, overlapping with a different region on the back side (referred to as the "second portion"). The first doped region is partially located between the device region and the second doped region. The term "doping" refers to the process of adding impurities to a semiconductor to modify its electrical properties, and "doping concentration" indicates the amount of impurity added. "Conductivity type" refers to whether the doped region is n-type (negative charge carriers) or p-type (positive charge carriers).

[0011] This aspect specifies that the first doped region and the second doped region differ in at least one characteristic: the doping concentration difference between the first doped region and the second doped region is at least 20%, or the conductivity type between the first doped region and the second doped region is different. This distinction allows for customized electrical characteristics in different regions of the device.

[0012] An "insulating layer" is a material layer that electrically isolates a portion of the semiconductor body and at least partially covers the back side. Furthermore, the first and second portions on the back side, corresponding to the first and second doped regions, both laterally overlap with the insulating layer. This arrangement ensures that the insulating layer interacts with the two doped regions, achieving complete insulation between them.

[0013] The described structure offers advantages such as improved control over electrical characteristics, enhanced isolation between regions, and the ability to optimize the device for specific applications by varying the doping concentration or type. The lateral overlap of the insulating layer with the two doped regions can contribute to better thermal management, reduced leakage current, or improved device durability.

[0014] In a first implementation of the device according to the first aspect, the second doped region is of a second conductivity type.

[0015] This implementation introduces a second doped region that is defined to have a specific characteristic of having the same conductivity type as the first doped region, which is of the second conductivity type. This modification refines the structural and functional relationships between the first and second doped regions within the semiconductor body. By specifying that the second doped region shares the same conductivity type as the first doped region, this implementation narrows the scope of the invention to configurations where both regions contribute to similar types of charge carrier behavior, such as electron or hole conduction, depending on whether the second conductivity type is n-type or p-type. In this case, the doping concentrations of the first and second doped regions differ by at least 20%. An insulating layer ensures electrical isolation while allowing the doped regions to interact indirectly through their influence on the electric field distribution within the semiconductor body. A new feature resulting from this implementation is the uniformity of conductivity type between the first and second doped regions, which simplifies the manufacturing process by reducing the need for additional doping steps with different materials or concentrations. Furthermore, in applications where charge carrier type uniformity is critical (e.g., in power devices or high-frequency applications), this feature can improve device performance.

[0016] In other implementations of the device according to the first aspect, the doping concentration of at least one second doped region is at least one order of magnitude higher than the doping concentration of the first doped region. According to this implementation, both the first doped region and the second doped region may have the same or different conductivity types.

[0017] This implementation introduces a specific differentiation mechanism between the first doped region and at least one second doped region by specifying that the doping concentration of the second doped region is at least an order of magnitude higher than that of the first doped region. This feature enhances the functional distinction between the two regions within the semiconductor body, thereby affecting the electrical and operational characteristics of the device. This aspect establishes the existence of a first doped region and at least one second doped region, where the latter differs from the former in doping concentration or conductivity type. This implementation refines this distinction by quantifying the difference in doping concentration, ensuring that the second doped region exhibits a significantly higher doping level. This significant difference in doping concentration can enhance the control over electrical characteristics within the semiconductor device, such as carrier mobility, resistance, and breakdown voltage. Connectivity between components (particularly the first doped region, the second doped region, and the device region) is affected by this doping difference. The higher doping concentration in the second doped region can generate a stronger electric field or a more pronounced potential barrier, which can be used to optimize the performance of lateral semiconductor elements in the device region. Furthermore, the interaction between the insulating layer and the back side of the semiconductor body (which overlaps with both the first and second doped regions) is consistent with this aspect, but the new features introduced in this implementation ensure that the electrical behavior of the second doped region is significantly different from that of the first doped region.

[0018] In other implementations of the device according to the first aspect, the first doped region and / or at least one second doped region are adjacent to the rear side.

[0019] This implementation introduces a specific structural relationship between the first doped region and / or at least one second doped region and the back side of the semiconductor body, specifying that these doped regions are adjacent to the back side. This feature refines the spatial configuration of the semiconductor device by ensuring direct physical contact or close proximity between the doped regions and the back side. The connectivity mechanisms between components are primarily structural and electrical in this case. By being adjacent to the back side, the doped regions are positioned to facilitate efficient charge carrier movement or electrical interaction between the doped regions and the back side, which may be critical to device performance (e.g., in terms of conductivity, breakdown voltage, or heat dissipation). The new features introduced by this implementation enhance the design flexibility and functional optimization of semiconductor devices. This new feature allows for the precise design of the electrical and thermal characteristics of the device by controlling the interface between the doped regions and the back side. This can be particularly advantageous in applications where the back side is used as a contact surface, heat sink, or area for other processing. This feature also complements the insulating layer described in this aspect, as the direct proximity of the doped regions to the back side can affect how the insulating layer interacts with the underlying semiconductor material, potentially impacting the overall insulation and reliability of the device. By designating one or two doped regions to be adjacent to the rear, the two doped regions are completely isolated from the surrounding environment.

[0020] In other implementations of the device according to the first aspect, two distinct second portions in the rear second portion are completely separated from each other by one or more first portions in the first portion.

[0021] This implementation introduces structural refinement to semiconductor devices by specifying that two distinct portions corresponding to the second doped region on the back side are completely separated from each other by one or more portions corresponding to the first doped region on the back side. This feature establishes a spatial and electrical isolation mechanism between the second doped regions mediated by the intervening first doped region. Connectivity between components is primarily defined by the spatial arrangement and doping characteristics of the regions in this case. The first doped region, with a different conductivity type or doping concentration compared to the second doped region, acts as a barrier or separator, ensuring that the second doped regions do not directly interact or overlap. This separation can affect the electrical behavior of the device, such as reducing parasitic interactions, minimizing leakage current, or enhancing control over the operation of lateral semiconductor elements within the device region. A new feature brought about by this implementation is the explicit requirement for complete separation of the second doped region by the first doped region, which adds a layer of design specificity and functional differentiation to the semiconductor device. This structural arrangement is particularly advantageous in applications where precise control of the electrical characteristics of the back side is critical, such as in power devices, high-frequency applications, or devices requiring robust isolation between different functional regions. By requiring complete separation, this implementation ensures that the second doped region is not only different in its doping characteristics but also physically and electrically isolated, which helps improve device performance, reliability, and manufacturability. This feature also complements the insulating layer on the back side, as the overlap between the insulating layer and both the first and second portions on the back side further enhances the device's isolation and electrical integrity. Therefore, this implementation refines this aspect by introducing a specific spatial configuration that enhances the functionality and operating characteristics of the semiconductor device.

[0022] In other implementations of the device according to the first aspect, the rear first portion is completely covered by an insulating layer.

[0023] This implementation introduces a specific structural feature that enhances the insulation properties of the semiconductor device by specifying that the first portion of the rear side is completely covered by an insulating layer. This ensures that the first doped region located between the device region and the rear side is completely insulated at the rear side by the insulating layer. The connectivity mechanism between components in this case is primarily physical and electrical isolation, as the insulating layer acts as a barrier to prevent direct electrical interaction or leakage between the first doped region and any external environment or adjacent regions at the rear side. This feature significantly improves the operational reliability and performance of the device by minimizing the risk of unintended electrical conduction or interference that could arise from exposed doped regions. By completely encapsulating the first portion of the rear side with an insulating layer, this implementation ensures that the first doped region is effectively shielded, which is particularly advantageous in applications requiring high-voltage isolation or where the semiconductor device is exposed to harsh environmental conditions. Furthermore, the complete insulation of the first doped region at the rear side facilitates more precise control over the electrical characteristics of the device, as it eliminates the potential variability introduced by partial exposure of the doped region. This feature complements the broader structure of this aspect by refining the interaction between the insulating layer and the first doped region, thereby enhancing the design of the device for improved electrical isolation and stability. This implementation emphasizes the intentional design choices that focus on full coverage, aiming to optimize the performance and durability of semiconductor devices in demanding applications.

[0024] In other implementations of the device according to the first aspect, the rear second portion is completely covered by an insulating layer.

[0025] This implementation introduces a specific structural feature that enhances the insulation properties of the semiconductor device by specifying that the second portion on the rear side is completely covered by an insulating layer. This ensures that each of the second doped regions in at least one second doped region is completely insulated on the rear side by the insulating layer. By requiring complete coverage of the second portion on the rear side, this implementation effectively isolates the second doped regions from external electrical or environmental influences that might otherwise interact with the rear side.

[0026] In other implementations of the device according to the first aspect, one or more of the second doped regions are shaped into a closed loop.

[0027] This implementation introduces a specific geometric configuration for one or more second-doped regions, specifying that these regions are shaped as closed loops, such as circles or ellipses. This feature adds new structural properties to the semiconductor device, which can affect the interaction between the second-doped regions and other components of the device. The closed loops ensure complete insulation of the device regions in the lateral direction. For example, the closed-loop configuration can improve the distribution of the electric field within the semiconductor body, thereby reducing localized stress or hot spots that may occur in irregularly shaped regions. The closed-loop shape can also affect the lateral overlap with the insulating layer, ensuring a more stable and controlled interface. This feature can be particularly advantageous in applications where precise control over the electrical characteristics behind the semiconductor body is critical. By specifying the closed-loop shape, this implementation introduces design elements that can be tailored to optimize the device for specific operating requirements, such as increasing breakdown voltage, reducing leakage current, or improving heat dissipation.

[0028] In other implementations of the device according to the first aspect, in a top view, a plurality of at least one second doped regions are arranged according to a lattice.

[0029] This implementation introduces a specific arrangement for second doped regions within a semiconductor device, specifying that, in a top view, multiple such second doped regions are organized in a lattice pattern. This feature adds a geometric and spatial configuration to the second doped regions, which were previously defined only in terms of their overlap with the back side, their difference from the first doped region in doping concentration or conductivity type, and their lateral overlap with the insulating layer. The lattice arrangement implies a regular, repeating pattern of the second doped regions, which can improve the uniformity of electrical or thermal properties across the back side of the semiconductor body. This configuration can also facilitate improved control over the electrical characteristics of the device, such as breakdown voltage or current distribution, by ensuring a predictable and uniformly distributed doping profile.

[0030] In other implementations of the device according to the first aspect, wherein, in a top view, a first plurality of at least one second doped region is arranged according to a first lattice inside the closed loop; and / or a second plurality of at least one second doped region is arranged according to a second lattice outside the closed loop.

[0031] This implementation introduces a spatial arrangement of second doped regions within a semiconductor device, particularly a spatial arrangement associated with a closed-loop structure. The implementation specifies, for example, in a top view of the semiconductor device, a first plurality of second doped regions arranged in a first lattice pattern inside the closed loop, while a second plurality of second doped regions are arranged in a second lattice pattern outside the closed loop. This arrangement provides a structured and organized distribution of the second doped regions, which can improve the electrical performance of the device by optimizing the placement of these regions relative to the closed loop. Although not explicitly detailed in this implementation, the closed loop itself can serve as a boundary or functional feature within the semiconductor body, and the lattice patterns of the second doped regions inside and outside the loop indicate an intentional design for achieving specific operational benefits.

[0032] In other implementations of the device according to the first aspect, an insulating trench extending laterally from the front side to the rear side of the semiconductor body is also included.

[0033] This implementation introduces an insulating trench extending from the front to the back of the semiconductor body, which laterally confines the device region. This feature provides a specific connectivity mechanism between components by physically and electrically isolating the device region from other regions within the semiconductor body. These other regions may include another voltage domain, such as a high-voltage or low-voltage domain for the gate driver. The insulating trench can isolate the high-voltage or low-voltage domains of the gate driver from each other. The isolation voltage can be greater than 200 V, greater than 600 V, or even 1200 V. The insulating trench acts as a boundary to prevent lateral electrical interference or leakage between the device region and adjacent regions, such as a first doped region or at least one second doped region. This isolation mechanism enhances operational integrity by ensuring that the performance of lateral semiconductor elements within the device region is not adversely affected by parasitic effects or unintended interactions with other parts of the semiconductor body. A new feature introduced by this implementation is the introduction of structural and functional barriers that improve device reliability and efficiency. By extending from the front to the back, the insulating trench ensures comprehensive isolation across the entire thickness of the semiconductor body, which is particularly beneficial in applications requiring high precision and minimal crosstalk between different regions. This structural addition complements the existing backing insulation layer by providing an additional isolation layer, but this isolation layer is provided in a three-dimensional manner, rather than as a planar cover of the insulation layer. Furthermore, the trench's ability to laterally confine the device region allows for a more compact design because it reduces the need for additional spacing between regions to prevent interference. Therefore, this feature not only enhances the electrical performance of the semiconductor device but also contributes to its overall design flexibility and scalability. By integrating this insulating trench, the semiconductor device achieves a high level of functional isolation and structural integrity, which is particularly advantageous in complex integrated circuits or advanced semiconductor applications.

[0034] In other implementations of the device according to the first aspect, the insulating trench includes a trench dielectric adjacent to the insulating layer.

[0035] This implementation introduces specific structural enhancements to semiconductor devices by detailing the interaction between insulating trenches and insulating layers. The insulating trenches, a structural feature within the semiconductor body, are defined as including trench dielectrics adjacent to the insulating layers. This configuration establishes a direct physical and functional relationship between the trench dielectric and the insulating layers, ensuring insulation continuity and potentially improving the electrical isolation characteristics of the device. The trench dielectric serves as a medium that not only reinforces the insulating properties of the trenches but also seamlessly integrates with the insulating layers covering the back of the semiconductor body. This structural arrangement enhances the device's ability to manage leakage current and maintains electrical isolation between different regions of the semiconductor body. The novel features brought by this implementation include: clearly defining the role of the trench dielectric and its adjacency to the insulating layers, which can contribute to improved device reliability, reduced parasitic effects, and better thermal management.

[0036] In other implementations of the device according to the first aspect, the insulating trench is shaped as a closed loop, such as a circle or an ellipse, in a top view.

[0037] This implementation introduces a specific structural configuration for insulating trenches within semiconductor devices, specified in a top view, where the trenches are shaped as closed loops, such as circular or elliptical. This feature builds upon a broader framework in this area by refining the geometric arrangement of the insulating trenches, a critical component in the device architecture. The closed-loop configuration of the trenches provides a mechanism for enhancing electrical isolation between different regions of the semiconductor body, particularly between a first doped region and at least one second doped region. This isolation is achieved by creating a continuous barrier to prevent lateral electrical interference or leakage current, thereby improving the overall performance and reliability of the semiconductor device. The circular or elliptical shape of the trenches also contributes to the uniformity of the isolation effect, as these geometries lack sharp corners that could otherwise concentrate electric fields and lead to localized breakdown or inefficiency. This new feature also promotes a more predictable and stable distribution of the electric field within the semiconductor body, which is particularly advantageous in high-performance or high-voltage applications. Furthermore, by providing a consistent and repeatable pattern for trench formation, the closed-loop design simplifies the manufacturing process, which can be advantageous in terms of scalability and production yield. This geometric refinement also serves the same purpose as the portion covered by the insulating layer on the back side, ensuring seamless integration of the insulating trench with the overall device structure.

[0038] In other implementations of the device according to the first aspect, at least one second doped region laterally adjoins the entire interior of the insulating trench.

[0039] This implementation introduces a specific spatial relationship between the second doped region and the insulating trench, specifying that the second doped region laterally adjoins the entire internal surface of the insulating trench. This feature establishes a direct and continuous interface between the second doped region and the insulating trench, which can enhance the electrical isolation or interaction between the second doped region and other regions of the semiconductor device. The connectivity mechanism between components is primarily structural and spatial in this case, as the lateral adjoining of the second doped region to the insulating trench ensures that any electrical or physical effects, such as charge distribution, field modulation, or thermal conduction, are affected by this close proximity. This adjoining can also be used to confine or guide the electric field within the semiconductor body, potentially improving the performance or reliability of lateral semiconductor elements in the device region. A new feature brought about by this implementation is the explicit requirement that the second doped region laterally adjoin the entire interior of the insulating trench, which can provide enhanced control over the electrical characteristics of the device, such as leakage current, breakdown voltage, or parasitic capacitance. By ensuring that the insulating trench and the second doped region interact in a predictable and uniform manner across their entire interface, this structural arrangement can also facilitate more precise design of the behavior of the semiconductor device. Overall, this implementation refines the structural and functional aspects of the semiconductor device by emphasizing the full lateral adjacency of the second doped region with the insulating trench, thereby enhancing the device's operating characteristics and distinguishing it from less specific configurations.

[0040] In other implementations of the device according to the first aspect, at least one lateral semiconductor element includes a first load terminal and a second load terminal.

[0041] This implementation introduces a specific configuration for lateral semiconductor elements within a semiconductor device. This specific configuration specifies that the lateral semiconductor element includes a first load terminal and a second load terminal, both located on the front side of the semiconductor body. This arrangement establishes a communication mechanism between the lateral semiconductor element and the external circuitry or system to which the device is connected. The first and second load terminals serve as electrical contacts through which load current is conducted. This implementation also defines the function of the lateral semiconductor element, specifying that it is designed to conduct load current between the first and second load terminals. This feature gives the lateral semiconductor element a clear operational purpose, emphasizing its role in facilitating current flow within the device. By specifying that the two terminals are located on the front side, this implementation highlights a structural and functional design choice that simplifies integration with other components or systems by avoiding the need for electrical connections on the rear side of the semiconductor body. This configuration can also help improve thermal management or reduce manufacturing complexity, as the rear side of the semiconductor body has been described in this regard as being at least partially covered by an insulating layer and including doped regions with specific characteristics. Therefore, this implementation complements this aspect by detailing how the lateral semiconductor element interacts with the rest of the device and external systems, while also potentially offering advantages in terms of design efficiency and functionality.

[0042] In other implementations of the device according to the first aspect, at least one lateral semiconductor element includes a first doped element region ohmically connected to a first load terminal, and one or more of at least one second doped region encompasses the vertical projection of the first doped element region on the rear side.

[0043] This implementation introduces a specific connectivity mechanism between the lateral semiconductor element and the second doped region by defining spatial and electrical relationships. The lateral semiconductor element includes a first doped element region ohmically connected to a first load terminal, thereby ensuring a low-resistance electrical path for current flow. This establishes a direct functional link between the lateral semiconductor element and external circuitry connected to the first load terminal. A novel feature of this implementation is that one or more second doped regions are spatially aligned with the vertical projection of the first doped element region on the rear side of the semiconductor body. This alignment implies that the second doped region is strategically positioned to correspond to the position of the first doped element region when viewed along the vertical axis. This spatial relationship enhances the structural and functional integration of the device by potentially optimizing the electric field distribution, improving current flow, or promoting heat dissipation. Furthermore, this implementation implicitly suggests that second doped regions, differing from the first doped region in doping concentration or conductivity type, can play a role in modulating the electrical characteristics of the device, such as breakdown voltage, leakage current, or switching performance. By incorporating the vertical projection of the first doped element region, the second doped region can also contribute to the robustness of the device by providing additional current paths or by influencing the behavior of the lateral semiconductor element under specific operating conditions. Therefore, this implementation refines the structural and functional interaction between the lateral semiconductor element and the second doped region, building upon the fundamental elements in this regard to introduce a more precise and potentially advantageous configuration.

[0044] In other implementations of the device according to the first aspect, at least one lateral semiconductor element is a diode.

[0045] This implementation introduces a specific implementation of at least one lateral semiconductor element within a semiconductor device, specifying that it can be a diode, bipolar transistor, field-effect transistor, junction transistor, or insulated-gate bipolar transistor (IGBT). This implementation refines the broader scope of this aspect by identifying the specific type of lateral semiconductor element that can be incorporated into the device region of the semiconductor body. The interconnection mechanism between components inherently relies on the electrical and physical interactions facilitated by the specified lateral semiconductor element. For example, if the lateral semiconductor element is a diode, the interconnection mechanism involves unidirectional current flow, which can be used for rectification or signal demodulation. If the element is a bipolar transistor, the interconnection mechanism involves current amplification through the interaction of the emitter, base, and collector regions, thereby enabling signal processing or switching functions. On the other hand, field-effect transistors rely on the modulation of the current flowing through the channel by an electric field applied to the gate, which is crucial for digital logic and analog signal amplification. Junction transistors would similarly involve current control through junction-based interactions, while IGBTs combine the high input impedance and fast switching characteristics of field-effect transistors with the high current-carrying capacity of bipolar transistors, making them suitable for power applications.

[0046] In other implementations of the device according to the first aspect, it further includes: one or more adhesion-promoting layers beneath the insulating layer; and a carrier wafer disposed to the semiconductor body via one or more adhesion-promoting layers.

[0047] This implementation introduces additional structural and functional features into the semiconductor device by specifying one or more adhesion-enhancing layers located beneath the insulating layer and a carrier wafer disposed to the semiconductor body through these adhesion-enhancing layers. A connectivity mechanism between components is established through the physical and functional interactions of the adhesion-enhancing layers with both the insulating layer and the carrier wafer. The adhesion-enhancing layer acts as an intermediary to enhance the bonding strength and stability between the semiconductor body and the carrier wafer, ensuring robust mechanical and thermal interfaces. This layer can promote improved adhesion by altering surface properties (e.g., surface energy or chemical compatibility), thereby addressing potential problems that may arise during manufacturing or operation, such as delamination or mechanical stress. The carrier wafer, in turn, provides structural support for the semiconductor body, which is particularly critical in applications where the semiconductor body may be thinned or subjected to mechanical processing during manufacturing. The introduction of these features brings several advantages to the semiconductor device. The adhesion-enhancing layer contributes to the reliability and durability of the device by mitigating the risks associated with weak bonding interfaces, such as cracking or delamination under thermal cycling or mechanical stress. This is especially important in high-performance or high-reliability applications where the device may be exposed to extreme conditions. The carrier wafer, by providing additional mechanical support, enables the use of a thinner semiconductor body, which can facilitate reduced overall device thickness, improved heat dissipation, or the achievement of specific electrical characteristics. Furthermore, the combination of the adhesion-promoting layer and the carrier wafer can facilitate advanced manufacturing techniques, such as wafer-level packaging or 3D integration, by providing a stable platform for further processing. Therefore, these new features enhance the structural integrity, manufacturing versatility, and operational reliability of semiconductor devices, while maintaining compatibility with the core components and functions described in this section.

[0048] A second aspect of the present invention provides a method for manufacturing a semiconductor device, the method comprising the steps of: providing: a semiconductor body having a front side and a rear side opposite to the front side; a device region within the semiconductor body at the front side, wherein the device region includes at least one lateral semiconductor element; and a first doped region having a second conductivity type between the device region and the rear side, wherein the first doped region overlaps with a first portion of the rear side; forming at least one second doped region within the semiconductor body, wherein the at least one second doped region overlaps with a second portion of the rear side, wherein the first doped region is disposed between the device region and the at least one second doped region; and forming an insulating layer that at least partially covers the rear side of the semiconductor body; wherein the at least one second doped region differs from the first doped region in at least one of the following aspects: a difference in doping concentration of at least 20%, and / or a difference in conductivity type; wherein both the first portion and the second portion of the rear side overlap laterally with the insulating layer.

[0049] This topic describes methods for manufacturing semiconductor devices, involving specific steps and structural features. The terminology used in this area is explained below:

[0050] A "semiconductor body" refers to the base material used to construct a device, typically silicon or another semiconductor material. A "semiconductor body" has a "front side" and a "back side," which are opposite surfaces of the body. The "front side" is where the active components of the device are typically formed, while the "back side" is the opposite surface.

[0051] A “device region” is a defined area located on the front side within a semiconductor body, in which at least one “lateral semiconductor element” is formed. A lateral semiconductor element may refer to a component such as a transistor or diode, in which current flows or operates in a direction parallel to the surface of the semiconductor body.

[0052] The "first doped region" is a region within the semiconductor body that has been intentionally implanted with impurities to achieve a specific "second conductivity type." The conductivity type refers to whether the region is doped as n-type (electron carriers) or p-type (hole carriers). This first doped region is located between the device region and the back side and overlaps with the "first portion" of the back side.

[0053] The “second doped region” is another doped region within the semiconductor body that overlaps with the “second portion” on the back. The second doped region differs from the first doped region in at least one characteristic, such as a difference of at least 20% in “doping concentration” (density of dopant atoms) or a difference in “conductivity type” (e.g., n-type versus p-type).

[0054] The "insulating layer" is a layer of material such as silicon dioxide that provides electrical isolation to a portion of the semiconductor body. This layer is formed to at least partially cover the back side of the semiconductor body. The first and second portions on the back side, corresponding to the first and second doped regions respectively, both laterally overlap with the insulating layer.

[0055] The described method offers advantages such as improved control over the electrical characteristics of semiconductor devices by introducing different doping profiles and conductivity types. The arrangement of doped regions and insulating layers enhances device performance, reliability, and isolation characteristics, which are crucial for advanced semiconductor applications. Attached Figure Description

[0056] The disclosure is shown by way of example and not by way of limitation in the accompanying drawings, in which the same reference numerals refer to similar or identical elements. The elements in the drawings are not necessarily to scale relative to each other. Features of the various examples shown can be combined unless they are mutually exclusive.

[0057] Figure 1 The top view shows the vertical projection of the semiconductor device;

[0058] Figure 2 It shows Figure 1 A schematic cross-section of a semiconductor device;

[0059] Figure 3 A top view shows a vertical projection of a semiconductor device according to another embodiment. Detailed Implementation

[0060] Although specific examples have been shown and described herein, those skilled in the art will understand that various alternative and / or equivalent implementations can be used instead of the specific examples shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

[0061] It should be noted that the methods and devices, including their preferred embodiments as outlined in this document, can be used alone or in combination with other methods and devices disclosed in this document. Furthermore, the features outlined in the context of the device also apply to the corresponding method, and vice versa. Moreover, all aspects of the methods and devices outlined in this document can be combined arbitrarily. In particular, the features of the claims can be combined with each other in any manner.

[0062] It should be noted that the specification and accompanying drawings only illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements, which, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiments outlined in this document are primarily and explicitly intended for illustrative purposes only to aid the reader in understanding the principles of the proposed methods and systems. Moreover, all statements herein providing the principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to cover their equivalents.

[0063] Figure 1 A top view of semiconductor device 1 is shown, including a concentric arrangement of various regions and structures. Semiconductor device 1 includes device region 50 configured as an exemplary MOSFET. The MOSFET includes an emitter region 61 located at the center and surrounded by a collector region 62. Insulating trenches 21 are depicted as concentric rings surrounding the emitter region 61 and the collector region 62, thereby providing electrical isolation between these regions and other components of semiconductor device 1. The arrangement of insulating trenches 21 demonstrates a design that ensures effective isolation and structural integrity within device region 50.

[0064] Figure 2 A cross-sectional view of semiconductor device 1 is provided, detailing the device's structure and material composition. The semiconductor body 10 is shown as a main substrate having a front side 11 and a rear side 12. The rear side 12 is divided into a first portion 12-1 and a second portion 12-2. A first doped region 31 overlaps with the rear side 12 in the first portion 12-1, while a second doped region 32 overlaps with the rear side 12 in the second portion 12-2. An insulating layer 20 is located on the rear side 12 and can completely overlap with both the first portion 12-1 and the second portion 12-2, thereby covering the first doped region 31 and the second doped region 32.

[0065] Insulating trenches 21 extend from the front side 11 into the semiconductor body 10 and terminate at the insulating layer 20. Each insulating trench 21 includes a trench oxide 22 lined with an inner wall and a trench filler 23 occupying a central volume. The trench filler 23 may be composed of doped or undoped polysilicon or an insulating material (e.g., silicon oxide (CVD oxide)). The insulating trenches 21 provide electrical isolation between adjacent regions within the semiconductor body 10.

[0066] Device region 50 is located near the front side 11 and includes an emitter region 61, a body region 63, an extension region 64, and a collector region 62. The emitter region 61 is located above the body region 63, which is adjacent to the extension region 64. The collector region 62 is positioned laterally to the emitter region 61 and is separated by an insulating trench 21. Trench oxide 22 and trench filler 23 within the insulating trench 21 ensure electrical isolation between the emitter region 61 and the collector region 62.

[0067] An insulating layer 20, which may include thermally grown oxides and / or CVD oxides, may be located beneath the semiconductor body 10 and provide additional electrical isolation. The insulating layer 20 may completely cover the first doped region 31 and the second doped region 32, thereby ensuring that the rear side 12 is electrically insulated from the active region of the semiconductor device 1.

[0068] The front side 11 of the semiconductor body 10 includes contact structures 51 and 53, respectively connected to the emitter region 61 and the collector region 62. These contact structures facilitate electrical connection with external circuits or systems. The arrangement of contact structures 51 and 53 ensures effective electrical connection with the emitter region 61 and the collector region 62 while maintaining the structural integrity of the semiconductor device 1.

[0069] A gate structure is also present on the front side 11 of the semiconductor body 10, which includes an insulated gate electrode 53.

[0070] Figure 3 A top view of semiconductor device 1 is shown, detailing the arrangement of various doped regions and insulating trenches within the semiconductor body 10. The figure prominently displays the insulating trench 21 forming a closed-loop structure. As described below, this insulating trench 21 is surrounded by and interacts with multiple doped regions.

[0071] A first doped region 31 is distributed across the semiconductor body 10 and is depicted as a uniform pattern of circular elements. This first doped region 31 extends across a large portion of the rear-side region, providing a base layer for the device. Furthermore, second doped regions 32 are present. These second doped regions 32 are further subdivided into specific portions based on their spatial relationship with the insulating trench 21.

[0072] The interior of the ring formed by the insulating trench 21 includes second doped regions 32-2. These regions are entirely within the enclosed area defined by the insulating trench 21 and are distinct from the surrounding areas. Outside the ring formed by the insulating trench 21, there are second doped regions 32-3. These regions are located outside the insulating trench 21 and are distributed in a manner similar to the second doped regions 32-2. Near the insulating trench 21, as indicated by reference numeral 32-1, the second doped regions 32-1 are arranged adjacent to the trench 21. These second doped regions 32-1 create a buffer region immediately adjacent to the insulating trench 21.

[0073] The insulating trench 21 is depicted as a continuous closed-loop structure, which may include an insulating layer 20, trench oxide 22, and trench filler 23 (not explicitly labeled in the figure, but inferred from the context of the reference numerals). The trench serves to electrically isolate the area within its boundaries from the external area, thereby defining distinct operating regions within the semiconductor device 1.

[0074] The spatial configuration ensures that the device functions as intended, with the insulating trench 21 providing the necessary isolation and the doped regions achieving specific electrical characteristics. A second doped region 32-1 near the insulating trench 21 further enhances the isolation characteristics, thereby preventing unintended electrical interactions between the inner and outer regions of the ring and reducing the field strength around the trench 21.

[0075] The accompanying drawings provide a detailed schematic representation of the spatial relationship and functional integration of the insulating trenches 21 and doped regions within the semiconductor body 10, forming a key aspect of the semiconductor device 1.

Claims

1. A semiconductor device, comprising: a semiconductor body having a front side and a back side opposite to the front side; a device region within the semiconductor body at the front side, wherein the device region comprises at least one lateral semiconductor element; a first doped region of a second conductivity type between the device region and the back side, wherein the first doped region overlaps a first portion of the back side; at least one second doped region within the semiconductor body, wherein the at least one second doped region overlaps a second portion of the back side, wherein the first doped region is arranged between the device region and the at least one second doped region; and an insulating layer at least partially covering the back side of the semiconductor body; wherein the at least one second doped region differs from the first doped region in at least one of: a doping concentration by at least 20%, and / or a doped conductivity type; wherein the first portion of the back side and the second portion of the back side both laterally overlap the insulating layer.

2. The semiconductor device of claim 1, wherein, The at least one second doped region is of the second conductivity type.

3. The semiconductor device according to any one of the preceding claims, wherein, The doping concentration of the at least one second doped region is at least one order of magnitude higher than the doping concentration of the first doped region.

4. The semiconductor device according to any one of the preceding claims, wherein, The first doped region and / or the at least one second doped region is / are contiguous to the back side.

5. The semiconductor device according to any one of the preceding claims, wherein, Two different second portions of the second portion of the back side are completely separated from each other by one or more of the first portions.

6. The semiconductor device according to any one of the preceding claims, wherein, The first portion of the back side is completely covered by the insulating layer, such that the first doped region is completely insulated at the back side by the insulating layer.

7. The semiconductor device according to any one of the preceding claims, wherein, The second portion of the back side is completely covered by the insulating layer, such that each of the at least one second doped region is completely insulated at the back side by the insulating layer.

8. The semiconductor device according to any one of the preceding claims, wherein, One or more of the at least one second doped region is / are shaped as a closed loop.

9. The semiconductor device of claim 8, wherein, One or more of the at least one second doped region is / are shaped as a circle or an ellipse.

10. The semiconductor device according to any one of the preceding claims, wherein, In a top view, a plurality of the at least one second doped region is arranged according to a lattice.

11. The semiconductor device according to any one of Claims 8 to 10, wherein In a top view, a first plurality of the at least one second doped region is arranged according to a first lattice inside the closed loop; and / or a second plurality of the at least one second doped region is arranged according to a second lattice outside the closed loop.

12. The semiconductor device according to any one of the preceding claims, further comprising: an insulating trench extending from the front side to the back side of the semiconductor body, laterally limiting the device region.

13. The semiconductor device of claim 12, wherein, The insulating trench comprises a trench dielectric contiguous to the insulating layer.

14. The semiconductor device of any one of claims 12 or 13, wherein, In a top view, the insulating trench is shaped as a closed loop.

15. The semiconductor device of claim 14, wherein, In a top view, the insulating trench is shaped as a circle or an ellipse.

16. The semiconductor device of any one of claims 12 to 15, wherein, The at least one second doped region is laterally contiguous to an entire interior of the insulating trench.

17. The semiconductor device of any one of the preceding claims, wherein, The at least one lateral semiconductor element comprises a first load terminal and a second load terminal, both arranged at the front side of the semiconductor body, wherein the at least one lateral semiconductor element is configured to conduct a load current between the first load terminal and the second load terminal.

18. The semiconductor device of claim 17, wherein, The at least one lateral semiconductor element comprises a first doped element region ohmically connected with the first load terminal, wherein one or more of the at least one second doped region comprises a vertical projection of the first doped element region on the back side.

19. The semiconductor device of any one of claims 17 or 18, wherein, The at least one lateral semiconductor element is a diode, a bipolar transistor, a field effect transistor, a junction transistor, or an IGBT.

20. The semiconductor device according to any one of the preceding claims, further comprising: one or more adhesion promoting layers below the insulating layer; and a carrier wafer arranged to the semiconductor body via the one or more adhesion promoting layers.

21. A method for manufacturing a semiconductor device, the method comprising the steps of: providing: a semiconductor body having a front side and a back side opposite to the front side; a device region within the semiconductor body at the front side, wherein the device region comprises at least one lateral semiconductor element; and a first doped region of a second conductivity type between the device region and the back side, wherein the first doped region overlaps a first portion of the back side; forming at least one second doped region within the semiconductor body, wherein the at least one second doped region overlaps a second portion of the back side, wherein the first doped region is arranged between the device region and the at least one second doped region; and forming an insulating layer at least partially covering the back side of the semiconductor body; wherein the at least one second doped region differs from the first doped region in at least one of the following: a doping concentration differs by at least 20%, and / or a doped conductivity type is different; wherein the first portion of the back side and the second portion of the back side both laterally overlap the insulating layer.

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