Semiconductor device, preparation method and integrated circuit
By introducing a second doped region into the semiconductor device to form a field-effect transistor structure, the potential transfer path is blocked, and the breakdown voltage is improved by utilizing the channel depletion effect. This solves the problem of limited breakdown voltage of transistor devices in the BCD process and achieves a significant improvement in breakdown voltage and process compatibility.
Patent Information
- Application Number
- CN202512032170.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-03-31
AI Technical Summary
In the BCD process, the breakdown voltage of parasitic transistor devices is limited by the high-voltage ion implantation layer, resulting in a breakdown voltage Bvceo that is much lower than expected, thus limiting the application of the BCD process platform.
Introducing a second doped region into a semiconductor device forms a field-effect transistor structure, which blocks the potential transfer path between the second well region and the substrate in the vertical direction. The depletion effect of the channel is used to reduce the actual voltage difference between the collector and the base junction, thereby increasing the breakdown voltage.
It significantly improves the breakdown voltage Bvceo of transistor devices by nearly 100%, and is compatible with existing BCD processes with low process difficulty and no additional cost.
Smart Images
Figure CN121772304A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, specifically relating to a semiconductor device, a fabrication method, and an integrated circuit. Background Technology
[0002] Bipolar-CMOS-DMOS (BCD) technology enables the simultaneous implementation of high-performance analog circuits, digital logic circuits, and power control circuits on a single chip, helping to reduce system costs, decrease size, and improve overall system performance and reliability. In BCD technology, existing high-voltage ion implantation layers are typically used to fabricate parasitic high-voltage transistor devices. Since the high-voltage ion implantation layer conditions on mature BCD technology platforms are usually fixed and not modified individually for parasitic transistor devices, the breakdown voltage (Bvceo) of the parasitic high-voltage transistor device is limited by the high-voltage ion implantation layer. If the high-voltage ion implantation layer conditions are unsuitable, the breakdown voltage (Bvceo) of the parasitic transistor device will be far lower than expected, thus limiting the application of the BCD technology platform. Summary of the Invention
[0003] The purpose of this application is to provide a semiconductor device, fabrication method, and integrated circuit to solve the problem that in the prior art, the breakdown voltage of parasitic transistor devices in the BCD process is limited by the high-voltage ion implantation layer. Inappropriate high-voltage ion implantation layer conditions can cause the breakdown voltage Bvceo of parasitic transistor devices to be much lower than expected, thus limiting the application of the BCD process platform.
[0004] To achieve the above objectives, a first aspect of this application provides a semiconductor device, comprising:
[0005] A substrate having a first doping type, the substrate having a first surface and a second surface disposed opposite to each other.
[0006] A first well region is located on the first surface of the substrate and has a first doping type;
[0007] A first doped region is located in the substrate and surrounds and contacts the first well region, the first doped region having a second doping type;
[0008] The second well region is located on the first surface of the substrate and has a first doping type, and the second well region is disposed at a distance from the first doped region;
[0009] A second doped region is located in the substrate and partially surrounds and contacts the second well region, the second doped region having a second doping type;
[0010] Wherein, at least a portion of the side of the second well region facing the second surface is surrounded by the second doped region, and at least a portion of at least one side of the second well region is in contact with the substrate.
[0011] In one or more embodiments, at least a portion of the side of the second well region facing the first doped region is in contact with the substrate.
[0012] In one or more embodiments, the entire region of the second well region facing the side of the first doped region is in contact with the substrate.
[0013] In one or more embodiments, the second doped region surrounds and contacts the side of the second well region facing the second surface and the side of the second well region facing away from the first doped region.
[0014] In one or more embodiments, the second well region has a protruding segment and an enclosing segment arranged sequentially in a direction away from the first doped region on the side facing the second surface, the second doped region surrounding and contacting the enclosing segment and the side of the second well region away from the first doped region.
[0015] In one or more embodiments, the extension length of the protruding section is 0.2~0.5 μm in the direction from the second well region to the first doped region.
[0016] In one or more embodiments, the second doped region surrounds and contacts the side of the second well region facing the second surface.
[0017] In one or more embodiments, the first doped region and the second doped region have the same doping concentration.
[0018] In one or more embodiments, the first doping type is p-type and the second doping type is n-type.
[0019] To achieve the above objectives, a second aspect of this application provides a method for fabricating a semiconductor device, comprising:
[0020] Forming a substrate having a first type of doping;
[0021] A second type of doping is implanted on one side of the substrate using a first mask to form a spaced first doped region and a second doped region.
[0022] Implantation of a first doping type is performed in the first doped region and the second doped region using a second mask to form a first well region and a second well region, wherein the first doped region surrounds the first well region, at least a portion of the bottom surface of the second well region is surrounded by the second doped region, and at least a portion of at least one side of the second well region is in contact with the substrate.
[0023] To achieve the above objectives, a third aspect of this application provides an integrated circuit, including the semiconductor device described in any of the above embodiments or the semiconductor device prepared by the preparation method described in any of the above embodiments.
[0024] The advantages of this application, which differ from existing technologies, are:
[0025] The semiconductor device of this application has a second doped region arranged outside the second well region. The second doped region can completely or partially block the potential transfer path between the second well region and the substrate in the vertical direction y. The second well region can only conduct potential with the substrate in the horizontal direction x. At the same time, the first doped region, the second doped region and the substrate located between them form a field-effect transistor structure. As the voltage difference gradually increases, the channel of the field-effect transistor is gradually depleted, causing the second well region to lose its clamping effect on the substrate below the second doped region, so as to reduce the actual voltage difference between the collector and the base junction and significantly improve the breakdown voltage.
[0026] The semiconductor device proposed in this application is fully compatible with existing BCD process platforms, has low technical difficulty in process implementation, no additional process costs, and is highly feasible and widely applicable. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 This is a schematic diagram of the structure of one embodiment of the semiconductor device of this application;
[0029] Figure 2 This is a schematic diagram of another embodiment of the semiconductor device of this application;
[0030] Figure 3 This is a schematic diagram of another embodiment of the semiconductor device of this application;
[0031] Figure 4 This is a schematic diagram of another embodiment of the semiconductor device of this application;
[0032] Figure 5 This is a graph showing the breakdown voltage test data of the semiconductor device of this application and conventional semiconductor devices;
[0033] Figure 6 This is a schematic flowchart of one embodiment of the method for fabricating the semiconductor device of this application.
[0034] Explanation of key figure labels:
[0035] Substrate 100; First surface 101; Second surface 102;
[0036] First pit region 200;
[0037] Second trap area 300; Extending section 301; Enclosing section 302;
[0038] First doped region 400;
[0039] Second doped region 500;
[0040] Field-effect transistor structure 600; channel 601. Detailed Implementation
[0041] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.
[0042] In the BCD process, parasitic transistor devices are typically fabricated using the existing high-voltage ion implantation conditions of the BCD platform. These ion implantation conditions are not modified specifically for parasitic transistor devices. This results in the transistor's breakdown voltage (BVceo) often being limited by the conditions of the high-voltage ion implantation layer. Inappropriate conditions in the high-voltage ion implantation layer can easily lead to a BVceo value for parasitic transistor devices that is far lower than expected.
[0043] To address the aforementioned issues, the applicant has developed a novel semiconductor device that utilizes the principle of a junction field-effect transistor (JFET). When the reverse bias voltage of the collector-base junction of the transistor is too high, the collector loses its clamping effect on the substrate potential, thereby significantly reducing the actual voltage difference between the collector and base junction and achieving the goal of increasing the breakdown voltage BVceo.
[0044] Specifically, please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of one embodiment of the semiconductor device of this application.
[0045] like Figure 1 As shown, the semiconductor device includes a substrate 100, which has a first doping type and has a first surface 101 and a second surface 102 disposed opposite to each other.
[0046] The first surface 101 of the substrate 100 is provided with a first well region 200 and a second well region 300, both of which have a first doping type.
[0047] The substrate 100 also has a first doped region 400 and a second doped region 500, which have a second doping type.
[0048] The first doped region 400 surrounds and contacts the first well region 200, and the second doped region 500 partially surrounds and contacts the second well region 300.
[0049] Specifically, in this embodiment, the second doped region 500 surrounds and contacts the side of the second well region 300 facing the second surface 102 and the side of the second well region 300 away from the first doped region 400.
[0050] The working principle of the semiconductor device of this application is described in detail below. In the semiconductor device of this embodiment, a substrate 100 having a first doping type, a first doped region 400 having a second doping type, and a first well region 200 having a first doping type can be constructed to form a transistor structure. The first well region 200 can serve as the emitter, the second well region 300 in contact with the substrate 100 can serve as the collector, and the first doped region 400 can serve as the base.
[0051] In this embodiment, the second well region 300 only contacts the substrate 100 on the side facing the first doped region 400. Therefore, the potential of the second well region 300 can only be transferred to the substrate 100 in the horizontal direction x. The transfer path in the vertical direction y is blocked by the second doped region 500. The specific conduction path is as follows: Figure 1 As indicated by the middle arrow.
[0052] Furthermore, the second doped region 500, the substrate 100, and the first doped region 400 form a field-effect transistor structure 600, wherein the portion of the substrate 100 located between the first doped region 400 and the second doped region 500 forms a channel 601, and depletion regions are formed between the second doped region 500 and the substrate 100, and between the first doped region 400 and the substrate 100.
[0053] Under normal voltage, the potential of the second well region 300 can be transferred to the substrate 100 below the base through the channel 601. At this time, the second well region 300 has a clamping effect on the substrate 100.
[0054] However, as the voltage of the second well region 300 gradually becomes negatively biased, the depletion region of the field-effect transistor structure 600 will continue to expand, causing the channel 601 to be gradually depleted. At this time, the clamping effect of the second well region 300 on the substrate 100 below the second doped region 500 gradually weakens until the channel 601 is completely depleted. Then, the second well region 300 completely loses its clamping effect on the substrate 100 below the second doped region 500. The potential of the substrate 100 below the second doped region 500 will not continue to be negatively biased with the second well region 300. Therefore, the actual voltage difference between the collector and the base junction will be much smaller than the input voltage difference between the collector and the base, thus significantly improving the breakdown voltage BVceo of the transistor device.
[0055] In summary, in this embodiment, by arranging a second doped region 500 outside the second well region 300, the second doped region 500 blocks the potential transfer path between the second well region 300 and the substrate 100 in the vertical direction y. The second well region 300 can conduct potential with the substrate 100 in the horizontal direction x. At the same time, a channel 601 is formed on the potential transfer path of the second well region 300. By utilizing the principle that the channel 601 is gradually depleted as the voltage difference gradually increases, the second well region 300 loses its clamping effect on the substrate 100 below the second doped region 500, thereby reducing the actual voltage difference between the collector and base junction and significantly improving the breakdown voltage.
[0056] In one embodiment, the doping concentration of the second doped region 500 can be the same as that of the first doped region 400, so that both the first doped region 400 and the second doped region 500 can be prepared using the existing high-pressure ion implantation conditions of the BCD process, which is fully compatible with the existing BCD process and does not require additional layering processes, thus simplifying the preparation steps.
[0057] Currently, in other embodiments, the doping concentration of the second doped region 500 can also be different from that of the first doped region 400, and the effect of this embodiment can also be achieved.
[0058] In one embodiment, the first doping type can be p-type, which can be prepared by doping with p-type dopants such as boron, aluminum, gallium, and indium; the second doping type can be specifically n-type, which can be prepared by doping with n-type dopants such as phosphorus, arsenic, and antimony. Accordingly, the semiconductor device of this application can be a PNP transistor.
[0059] In another embodiment, the first doping type can also be n-type and the second doping type can also be p-type, which can also achieve the effect of this embodiment.
[0060] In the above embodiments, the second doped region 500 surrounds the side of the second well region 300 facing the second surface 102 and the side of the second well region 300 away from the first doped region 400. In other embodiments, the second doped region 500 may also surround other areas of the second well region 300. Specifically, it is ensured that the second doped region 500 can include at least a portion of the side of the second well region 300 facing the second surface 102, and at least a portion of the side of the second well region 300 can contact the substrate 100. Both can block the potential transfer path between the second well region 300 and the substrate 100 in the vertical direction y to a certain extent, and achieve the effects of the above embodiments to a certain extent.
[0061] Specifically, in another embodiment, the second doped region 500 may only surround a portion of the bottom surface of the second well region 300. (See [link to relevant documentation]). Figure 2 , Figure 2 This is a schematic diagram of another embodiment of the semiconductor device of this application.
[0062] like Figure 2 As shown, in the direction from the first well region 200 to the second well region 300, in this embodiment, the side of the second well region 300 facing the second surface 102 includes a protruding section 301 and a surrounding section 302 arranged in sequence, wherein the second doped region 500 surrounds and contacts the surrounding section 302 and the side of the second well region 300 away from the first doped region 400.
[0063] Based on this structure, although there is still a partial potential transfer path in the vertical y direction at the protruding section 301, it can effectively ensure that the side of the second well region 300 facing the first doped region 400 is in complete contact with the substrate 100, without affecting the potential conduction of the second well region 300.
[0064] Due to process errors, in the preparation Figure 1 When manufacturing semiconductor devices, a problem can easily occur where the second doped region 500 completely surrounds the second well region 300 due to manufacturing errors, at which point the second well region 300 becomes completely ineffective. Therefore, in this embodiment, the problem is effectively avoided by reserving an extension section 301.
[0065] In one embodiment, the extension length of the protruding segment 301 in the horizontal direction x can be 0.2~0.5 μm to maximize the blocking of the potential transfer path of the second well region 300 in the vertical direction y.
[0066] Furthermore, in yet another implementation, please refer to Figure 3 , Figure 3 This is a schematic diagram of another embodiment of the semiconductor device of this application.
[0067] like Figure 3As shown, in this embodiment, the second doped region 500 only surrounds the bottom surface of the second well region 300, and both sides of the second well region 300 are in contact with the substrate 100. At this time, there are potential transfer paths on both sides of the second well region 300 in the horizontal direction x, such as... Figure 3 As shown in the image.
[0068] Since the potential transfer path of the second well region 300 facing the first well region 200 can be blocked by the channel 601 when the voltage difference between the collector and the base is too large, the clamping effect of the second well region 300 on the substrate 100 located below the first doped region 400 is limited, and thus the effects of the above embodiments can be achieved to a certain extent.
[0069] Furthermore, in yet another implementation, please refer to Figure 4 , Figure 4 This is a schematic diagram of another embodiment of the semiconductor device of this application.
[0070] like Figure 4 As shown, in this embodiment, the second doped region 500 also surrounds a portion of the second well region 300 facing the first well region 200. In this case, the potential transfer path of the second well region 300 in the x direction can be blocked by the channel 601, which can also achieve the effects of the above embodiments to a certain extent. However, since the second doped region 500 blocks part of the potential transfer path of the second well region 300 in the x direction, it may increase the resistance of the second well region 300 and affect the device performance.
[0071] Based on the semiconductor devices of the above embodiments, by arranging a second doped region 500 outside the second well region 300, the potential transfer path between the second well region 300 and the substrate 100 in the vertical direction y can be completely or partially blocked. The second well region 300 can only conduct potential with the substrate 100 in the horizontal direction x. At the same time, the first doped region 400, the second doped region 500 and the substrate 100 located between them form a field-effect transistor structure 600. As the voltage difference gradually increases, the channel 601 of the field-effect transistor is gradually depleted, causing the second well region 300 to lose its clamping effect on the substrate 100 below the second doped region 500, thereby reducing the actual voltage difference between the collector and base junction and significantly improving the breakdown voltage.
[0072] In addition, the semiconductor devices of the above embodiments are fully compatible with existing BCD process platforms, have low technical difficulty in process implementation, no additional process costs, and are highly feasible and widely applicable.
[0073] Furthermore, the applicant tested Figure 2 The breakdown voltage BVceo of the semiconductor device shown is compared with that of a conventional semiconductor device, where, Figure 2The semiconductor devices shown are both PNP transistors, and their doping concentrations and specifications are exactly the same. Conventional semiconductor devices, relative to... Figure 2 The semiconductor device shown is missing only the second doped region 500.
[0074] Please refer to the test results. Figure 5 , Figure 5 This is a graph showing the breakdown voltage test data of the semiconductor device of this application and conventional semiconductor devices. For example... Figure 5 As shown, the BVceo of the semiconductor device in this application is increased by nearly 28V compared to conventional semiconductor devices, an increase of nearly 100%.
[0075] Furthermore, this application also provides a method for fabricating the semiconductor device according to the above embodiments. Please refer to [link to relevant documentation]. Figure 6 , Figure 6 This is a schematic flowchart of one embodiment of the method for fabricating the semiconductor device of this application.
[0076] like Figure 6 As shown, the preparation method includes:
[0077] S101, Form a substrate having a first doping type.
[0078] S102. Using a first mask, a second type of doping is implanted on one side of the substrate to form a spaced first doped region and a second doped region.
[0079] S103. Using a second mask, implantation of a first type of doping is performed in the first doped region and the second doped region to form a first well region and a second well region.
[0080] In this configuration, a first doped region surrounds a first well region, at least a portion of the bottom surface of a second well region is surrounded by a second doped region, and at least a portion of at least one side of the second well region is in contact with the substrate.
[0081] This application also provides an integrated circuit that includes the semiconductor device of any of the above embodiments.
[0082] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0083] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate having a first doping type, the substrate having a first surface and a second surface oppositely arranged; a first well region on the first surface of the substrate and having the first doping type; a first doped region in the substrate and surrounding and contacting the first well region, the first doped region having a second doping type; a second well region on the first surface of the substrate and having the first doping type, the second well region being spaced apart from the first doped region; a second doped region in the substrate and partially surrounding and contacting the second well region, the second doped region having the second doping type; wherein at least a part of an area of a surface of the second well region facing the second surface is surrounded by the second doped region, and at least a part of a side surface of the second well region is in contact with the substrate.
2. The semiconductor device according to claim 1, wherein at least a part of a side surface of the second well region facing the first doped region is in contact with the substrate.
3. The semiconductor device of claim 2, wherein, all of a side surface of the second well region facing the first doped region is in contact with the substrate.
4. The semiconductor device according to claim 3, wherein the second doped region surrounds and contacts a surface of the second well region facing the second surface and a side surface of the second well region facing away from the first doped region.
5. The semiconductor device of claim 3, wherein the surface of the second well region facing the second surface has, in sequence in a direction facing away from the first doped region, a protruding section and a surrounding section, and the second doped region surrounds and contacts the surrounding section and a side surface of the second well region facing away from the first doped region.
6. The semiconductor device of claim 5, wherein, an extension length of the protruding section in the direction facing away from the first doped region is 0.2-0.5 μm.
7. The semiconductor device of claim 3, wherein the second doped region surrounds and contacts the surface of the second well region facing the second surface.
8. The semiconductor device of claim 1, wherein the doping concentration of the first doped region and the second doped region is the same; and / or the first doping type is p-type and the second doping type is n-type.
9. A method of manufacturing a semiconductor device, characterized by, The semiconductor device comprises: forming a substrate having a first doping type; performing implantation of a second doping type on a surface of the substrate using a first mask to form spaced-apart first doped regions and second doped regions; performing implantation of the first doping type on the first doped regions and the second doped regions using a second mask to form first well regions and second well regions, wherein the first doped regions surround the first well regions, at least a part of a bottom surface of the second well regions is surrounded by the second doped regions, and at least a part of a side surface of the second well regions is in contact with the substrate.
10. An integrated circuit, characterized by The semiconductor device is prepared by the method of any one of claims 1-8 or the method of claim 9.