Etching method

Abstract

The invention provides an etching method, which comprises the following steps of: providing a semiconductor structure which comprises a first wiring layer, and a first etching stop layer, an interlayer dielectric layer and a hard mask layer which are sequentially stacked on the first wiring layer from bottom to top, and a first opening is formed in the hard mask layer, at least two grooves are formed in the interlayer dielectric layer, are positioned below the first opening and are communicated with the first opening; the semiconductor structure is etched based on the hard mask layer, a second opening and at least two through holes for exposing a metal wire layer in the first wiring layer are formed, the through holes are located below the second opening and communicated with the second opening, an isolation structure is formed between any two adjacent through holes, the pressure range of the reaction chamber in the etching process is 105-115 mT, and the metal wire layer in the first wiring layer is exposed. The low-frequency power range is 105-150 W, and the etching gas comprises CF4, O2 and Ar. The etching method provided by the invention can reduce the difference of section morphologies among the through holes and avoid the problems of copper bridging and the like, thereby improving the mass production yield of the device and the reliability of the chip.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology and relates to an etching method. Background Technology

[0002] As integrated circuit manufacturing processes evolve towards advanced nodes, the etching quality of the dual damascene process directly determines chip yield and reliability. High-density vias (DVs) serve as the core interconnect structure, with a spacing of only 20-50 nm between two adjacent vias. This density is 3-5 times higher than that of previous generations of processes, making them a key hub for signal and energy transmission.

[0003] However, during the back-end etching process, the low-k dielectric (e.g., Black Diamond II, BDII) between adjacent vias forms a via-Via facet morphology, the uniformity of which depends on etching stability. In existing etching methods, the low-k dielectric is sensitive to process parameters, and vias are prone to shrinkage, leading to an exacerbation of the micro-load effect. This results in significant differences in the Via-Via facet morphology (e.g., excessively large local upward tilt angles, uneven downward tilt angles, and tilt angle differences exceeding 15° between adjacent facets). These differences directly compress the via-Via bridge window in Wafer Acceptance Test (WAT), causing problems such as copper bridging, contact resistance dispersion, and a sharp drop in process tolerance, reducing device mass production yield and chip reliability and lifespan.

[0004] Therefore, how to provide an etching method to reduce the difference in cross-sectional morphology between vias, ensure the bridging window between adjacent vias, and thus avoid problems such as copper bridging, contact resistance dispersion and a sharp drop in process tolerance, thereby improving the mass production yield of devices and the reliability and lifespan of chips, has become an important problem that needs to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an etching method to solve the problems of excessive differences in the cross-sectional morphology between vias, which easily lead to copper bridging, contact resistance dispersion, and a sharp drop in process tolerance, resulting in low mass production yield of devices and short reliability and lifespan of chips.

[0007] To achieve the above and other related objectives, the present invention provides an etching method comprising the following steps:

[0008] A semiconductor structure is provided, the semiconductor structure including a first wiring layer and a first etch stop layer, an interlayer dielectric layer and a hard mask layer stacked sequentially from bottom to top on the first wiring layer, wherein the hard mask layer has a first opening and the interlayer dielectric layer has at least two trenches, the trenches being located below the first opening and communicating with the first opening;

[0009] The semiconductor structure is etched based on the hard mask layer to extend the sidewall of the first opening into the interlayer dielectric layer and extend the bottom of the trench to the side of the first etch stop layer away from the hard mask layer, forming a second opening and at least two vias exposing the metal lines in the first wiring layer. The vias are located below the second opening and communicate with the second opening. An isolation structure is formed between any two adjacent vias. The pressure range of the reaction chamber during the etching process is 105~115 mT. The RF power supply includes high-frequency power and low-frequency power, with the low-frequency power range being 105~150 W. The etching gas includes CF4, O2, and Ar.

[0010] Optionally, in the XY plane, the width of the longitudinal section of the isolation structure gradually increases and decreases from bottom to top.

[0011] Optionally, the tangent at the top of the longitudinal section of the isolation structure has a first angle relative to the horizontal plane, and the tangent at the bottom of the longitudinal section of the isolation structure has a second angle relative to the horizontal plane. The first angle is located outside the isolation structure, and the second angle is located inside the isolation structure. The first angle is smaller than the second angle.

[0012] Optionally, forming the semiconductor structure includes the following steps:

[0013] A first wiring layer is provided, the first wiring layer including the metal wire layer and a first dielectric layer enclosing the metal wire layer;

[0014] The etching stop layer, the interlayer dielectric layer, and the hard mask layer are sequentially formed on the first dielectric layer;

[0015] A patterned first photoresist layer is formed on the hard mask layer, and a first window is formed in the first photoresist layer to expose the hard mask layer;

[0016] Photolithography is performed on the hard mask layer based on the first photoresist layer to form the first opening in the hard mask layer, the first opening exposing the interlayer dielectric layer, and then the first photoresist layer is removed.

[0017] A patterned second photoresist layer is formed on the hard mask layer, and a second window is formed in the first photoresist layer to expose the interlayer dielectric layer;

[0018] The hard mask layer is photolithographically etched based on the second photoresist layer to form the trench in the interlayer dielectric layer, and the second photoresist layer is removed to obtain the semiconductor structure.

[0019] Optionally, a second etch stop layer is further provided between the hard mask layer and the interlayer dielectric layer. During the photolithography process of the hard mask layer based on the first photoresist layer, the first opening is located in the hard mask layer, the second window exposes a portion of the hard mask layer at the bottom of the first opening, and the trench penetrates the hard mask layer below the first opening and the second etch stop layer and extends into the interlayer dielectric layer.

[0020] Optionally, the hard mask layer includes a first hard mask layer and a metal hard mask layer stacked sequentially from bottom to top, the first opening penetrates the metal hard mask layer and extends to the first hard mask layer, the second window exposes a portion of the first hard mask layer at the bottom of the first opening, and the trench penetrates the first hard mask layer below the first opening and the second etch stop layer and extends into the interlayer dielectric layer.

[0021] Optionally, the material of the first hard mask layer includes a nitrogen-free anti-reflective coating, and the material of the metal hard mask layer includes titanium nitride.

[0022] Optionally, the first etch stop layer includes a SiCN layer and a silicon dioxide layer covering the SiCN layer.

[0023] Optionally, during the etching process, the high-frequency power range is 1000~1200 W.

[0024] Optionally, in the etching gas, the flow rate of CF4 is in the range of 100~300 sccm, the flow rate of O2 is in the range of 20~30 sccm, and the flow rate of Ar is in the range of 200~500 sccm.

[0025] As described above, the etching method of the present invention includes the following steps: providing a semiconductor structure, the semiconductor structure including a first wiring layer and a first etch stop layer, an interlayer dielectric layer and a hard mask layer stacked sequentially from bottom to top on the first wiring layer, wherein a first opening is formed in the hard mask layer and at least two trenches are formed in the interlayer dielectric layer, the trenches being located below the first opening and communicating with the first opening; etching the semiconductor structure based on the hard mask layer to extend the sidewall of the first opening into the interlayer dielectric layer and extend the bottom of the trenches to the side of the first etch stop layer away from the hard mask layer, forming a second opening and at least two vias exposing the metal wire layers in the first wiring layer, the vias being located below the second opening and communicating with the second opening, such that an isolation structure is formed between any two adjacent vias, and the pressure range of the reaction chamber during the etching process is 105~115 mT, the radio frequency power supply includes high frequency power and low frequency power, the low frequency power range is 105~150 W, and the etching gas includes CF4, O2 and Ar. The etching method of the present invention can reduce the difference in cross-sectional morphology between vias by selecting the etching gas and setting the etching parameters, and ensure the bridging window between adjacent vias. This avoids problems such as copper bridging, contact resistance dispersion and a sharp drop in process tolerance, thereby improving the mass production yield of devices and the reliability and lifespan of chips. Attached Figure Description

[0026] Figure 1 This diagram illustrates a semiconductor structure in a back-end etching process.

[0027] Figure 2 This diagram illustrates the structure obtained after forming a photoresist layer in a back-end etching process.

[0028] Figure 3 This is a schematic diagram of the structure obtained after forming trenches in a back-end etching process.

[0029] Figure 4 This diagram illustrates the structure obtained after forming a through-hole in a back-end etching process.

[0030] Figure 5 This is a diagram showing a working state in a back-end etching process.

[0031] Figure 6 Displayed as Figure 4 A magnified view of region I in the middle.

[0032] Figure 7 The diagram shown is a process flow chart of the etching method of the present invention.

[0033] Figure 8 The diagram shown is a schematic representation of the semiconductor structure in the etching method of the present invention.

[0034] Figure 9The diagram shown is a schematic of the first wiring layer structure in the etching method of the present invention.

[0035] Figure 10 The diagram shows the structure obtained after forming the etching stop layer, the interlayer dielectric layer and the hard mask layer in the etching method of the present invention.

[0036] Figure 11 This is a schematic diagram of the structure obtained after forming the first photoresist layer in the etching method of the present invention.

[0037] Figure 12 This is a schematic diagram of the structure obtained after forming the first opening in the etching method of the present invention.

[0038] Figure 13 The diagram shows the structure obtained after forming the second photoresist layer in the etching method of the present invention.

[0039] Figure 14 This is another schematic diagram showing the structure obtained after forming an opening in the etching method of the present invention.

[0040] Figure 15 This diagram shows the structure obtained after forming the second opening, through-hole, and isolation structure in the etching method of the present invention.

[0041] Figure 16 Displayed as Figure 15 Enlarged view of region II.

[0042] Figure 17 This diagram illustrates one working state of the etching method of the present invention.

[0043] Explanation of reference numerals in the attached figures

[0044] 101 Rerouting layer 102、202 Etching stop layer 2021 SiCN layer 2022 Silicon dioxide layer 103、203 Interlayer dielectric layer 104、204 Hard mask layer 2041 First hard mask layer 2042 Metal hard mask layer 105、205 First opening 106 Photoresist layer 107、212 Second opening 108、206 trench 109、213 Through hole 110、214 isolation structure 201 First wiring layer 2011 Metal wire layer 2012 First dielectric layer 207 First photoresist layer 208 First Window 209 Second photoresist layer 210 Second window 211 Second etch stop layer C First included angle D Second angle S1~S2 step Detailed Implementation

[0045] Please see Figures 1 to 4 This is shown as a post-etching process, including the following steps:

[0046] (1) Please refer to Figure 1 A semiconductor structure is provided, the semiconductor structure including a redistribution layer 101 and an etch stop layer 102, an interlayer dielectric layer 103, and a hard mask layer 104 stacked sequentially from bottom to top on the redistribution layer 101, wherein the hard mask layer 104 has a first opening 105 that exposes the interlayer dielectric layer 103.

[0047] (2) Please refer to the following: Figure 2A patterned photoresist layer 106 is formed on the semiconductor structure, the photoresist layer 106 covers the hard mask layer 104 and the interlayer dielectric layer 103, and at least two second openings 107 are formed in the photoresist layer 106 to expose the interlayer dielectric layer 103.

[0048] (3) Please refer to the following: Figure 3 Based on the photoresist layer 106, the interlayer dielectric layer 103 is etched to form at least two trenches 108 in the interlayer dielectric layer 103. The trenches 108 are located below the corresponding first opening 105 and are connected to the first opening 105.

[0049] (4) Please refer to the following: Figure 4 The photoresist layer 106 is removed, and the interlayer dielectric layer 103 is etched based on the hard mask layer 104 to extend the sidewall of the first opening 105 into the interlayer dielectric layer 103. The bottom of the trench 107 extends to the side of the first etching stop layer 102 away from the hard mask layer 104, forming a through-hole 109 penetrating the dielectric layer. An isolation structure 110 is formed between any two adjacent through-holes 109. During the etching process, the pressure in the reaction chamber is 50 mT, the high-frequency power is 1200 W, the low-frequency power is 200 W, and the etching gas includes CF4, O2, and Ar.

[0050] Please see Figure 5 Because the low-frequency power is 200 W, and the Ar atoms are all oriented vertically downwards, the bridging morphology between the vias 109 obtained through the above steps varies too much. Please refer to [link / reference needed]. Figure 6 The angle A between the tangent at the top of the longitudinal section of the isolation structure 110 and the horizontal plane is greater than the angle B between the tangent at the bottom and the horizontal plane. This causes the isolation structure 110 to lose its isolation function. In other words, during subsequent metal plating, the plated metal can easily cross the isolation structure 110, and even slight fluctuations in process parameters can lead to metal bridging. Furthermore, in the XY plane, the width of the longitudinal section of the isolation structure 110 increases sequentially from top to bottom, which can also result in insufficient etching of some of the vias 109, ultimately leading to extremely small bridging windows and poor connectivity between chips.

[0051] Through extensive analysis and research, the inventors of this application have improved the back-end etching process and provided an etching method that can avoid the above problems and improve the reliability and lifespan of the chip.

[0052] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0054] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0055] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0056] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0057] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0058] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0059] Please see Figure 7 The diagram shows a process flow chart of the preparation method of the etching method of the present invention, which includes at least the following steps:

[0060] S1: A semiconductor structure is provided, the semiconductor structure including a first wiring layer and a first etch stop layer, an interlayer dielectric layer and a hard mask layer stacked sequentially on the first wiring layer from bottom to top, wherein a first opening is formed in the hard mask layer, and at least two trenches are formed in the interlayer dielectric layer, the trenches being located below the first opening and communicating with the first opening.

[0061] S2: Based on the hard mask layer, the semiconductor structure is etched to extend the sidewall of the first opening into the interlayer dielectric layer, and extend the bottom of the trench to the side of the first etch stop layer away from the hard mask layer, forming a second opening and at least two vias exposing the metal lines in the first wiring layer. The vias are located below the second opening and communicate with the second opening. An isolation structure is formed between any two adjacent vias. The pressure range of the reaction chamber during the etching process is 105~115 mT. The RF power supply includes high-frequency power and low-frequency power. The low-frequency power range is 105~150 W. The etching gas includes CF4, O2 and Ar.

[0062] The following section, using a structural diagram, details the specific implementation methods of each of the above steps.

[0063] Please refer to the following first. Figure 8 Step S1: Provide a semiconductor structure, the semiconductor structure including a first wiring layer 201 and a first etch stop layer 202, an interlayer dielectric layer 203 and a hard mask layer 204 stacked sequentially from bottom to top on the first wiring layer 201, and the hard mask layer 204 having a first opening 205, the interlayer dielectric layer 203 having at least two trenches 206, the trenches 206 being located below the first opening 205 and communicating with the first opening 205.

[0064] As an example, forming the semiconductor structure includes the following steps:

[0065] (1) Please refer to Figure 9 The first wiring layer 201 is provided, which includes the metal wire layer 2011 and a first dielectric layer 2012 that encloses the metal wire layer 2011.

[0066] (2) Please refer to Figure 10 The etching stop layer 202, the interlayer dielectric layer 203 and the hard mask layer 204 are sequentially formed on the first dielectric layer 2012;

[0067] (3) Please refer to Figure 11A patterned first photoresist layer 207 is formed on the hard mask layer 204, and a first window 208 is formed in the first photoresist layer 207 to expose the hard mask layer 204.

[0068] (4) Please refer to Figure 12 The hard mask layer 204 is photolithographically ...

[0069] (5) Please refer to Figure 13 A patterned second photoresist layer 209 is formed on the hard mask layer 204, and a second window 210 is formed in the second photoresist layer 209 to expose the interlayer dielectric layer 203.

[0070] (6) Please refer to the following: Figure 8 The hard mask layer 204 is photolithographically lithographically formed on the second photoresist layer 209 to form the trench 206 in the interlayer dielectric layer 203, and the second photoresist layer 209 is removed to obtain the semiconductor structure.

[0071] As an example, the first etch stop layer 202 includes a SiCN layer (Silicon Carbonitride Layer, nitrogen-doped silicon carbide layer) 2021 and a silicon dioxide layer 2022 covering the SiCN layer 2021. In this embodiment, the material of the silicon dioxide layer 2022 is tetraethyl orthosilicate (TEOS).

[0072] For example, please refer to Figure 14 A second etch stop layer 211 is further provided between the hard mask layer 204 and the interlayer dielectric layer 203. During photolithography of the hard mask layer 204 based on the first photoresist layer 207, the first opening 205 is located in the hard mask layer 204, and the second window 210 exposes a portion of the hard mask layer 204 at the bottom of the first opening 205. Please refer to [further details omitted]. Figure 8 The trench 206 penetrates the hard mask layer 204 and the second etch stop layer 211 below the first opening 205 and extends into the interlayer dielectric layer 203.

[0073] For example, please refer to Figure 14The hard mask layer 204 includes a first hard mask layer 2041 and a metal hard mask layer 2042 stacked sequentially from bottom to top. The first opening 205 penetrates the metal hard mask layer 2042 and extends to the first hard mask layer 2041. The second window 210 exposes a portion of the first hard mask layer 2041 at the bottom 205 of the first opening. See also... Figure 8 The trench 206 penetrates the first hard mask layer 2041 and the second etch stop layer 211 below the first opening 205 and extends into the interlayer dielectric layer 203.

[0074] As an example, the material of the first hard mask layer 2041 includes a nitrogen-free anti-reflective coating, and the material of the metal hard mask layer 2042 includes titanium nitride.

[0075] Please see again Figure 15 Step S2: Based on the hard mask layer 204, the semiconductor structure is etched to extend the sidewall of the first opening 205 into the interlayer dielectric layer 203, and extend the bottom of the trench 206 to the side of the first etch stop layer 202 away from the hard mask layer 204, forming a second opening 212 and at least two vias 213 exposing the metal line layer 2011 in the first wiring layer 201. The vias 213 are located below the second opening 212 and communicate with the second opening 212, so that an isolation structure 214 is formed between any two adjacent vias 213. The pressure range of the reaction chamber during the etching process is 105~115 mT, the RF power supply includes high frequency power and low frequency power, the low frequency power range is 105~150 W, and the etching gas includes CF4, O2 and Ar.

[0076] Specifically, with Figure 4 Compared to the etching process of the structure shown, the pressure range of the reaction chamber and the range of the low-frequency power mentioned above increase the pressure of the reaction chamber and reduce the low-frequency power (i.e., the bias RF power). Through the synergistic effect of the above two, the bombardment of Ar atoms on the sidewalls of the via 213 and the isolation structure 214 during the etching process is suppressed, thereby reducing the difference in the morphology of the cross-section (Via-Via facet) between vias 213, maintaining the isolation function of the isolation structure 214, and ensuring the bridging window between adjacent vias 213. This avoids problems such as copper bridging, contact resistance dispersion, and a sharp drop in process tolerance, thereby improving the mass production yield of the device and the reliability and lifespan of the chip.

[0077] For example, please refer to [link / reference]. Figure 15 In the XY plane, the width of the longitudinal section of the isolation structure 214 gradually decreases from bottom to top, compared to Figure 6The width of the longitudinal section of the isolation structure 110 decreases gradually from bottom to top at a relatively small rate, which is fast at first and then slows down. In this embodiment, the width of the longitudinal section of the isolation structure 214 decreases at a stable rate to widen the top of the isolation structure 214, thereby preventing metal from crossing the bridging.

[0078] For example, please refer to Figure 16 The tangent at the top of the longitudinal section of the isolation structure 214 has a first angle C relative to the horizontal plane, and the tangent at the bottom of the longitudinal section of the isolation structure 214 has a second angle D relative to the horizontal plane. The first angle C is located outside the isolation structure 214, and the second angle D is located inside the isolation structure 214. The first angle C is smaller than the second angle D, so that the isolation structure 214 can prevent the electroplated metal from crossing, ensuring electrical isolation between adjacent vias 213 to ensure device yield. Specifically, the facet morphology (especially the angle uniformity) of the isolation structure 214 is key to the size of the Via-Via bridge window. Please refer to [further details]. Figure 6 The isolation structure 110 has a steep facet angle (i.e., the included angle A at the top is greater than the second included angle B at the bottom, steeper at the top and gentler at the bottom). During metal filling, it tends to grow laterally along the steep facet, leading to bridging and short circuits. This reduces the bridging window and lowers the device yield. Specifically, the top sidewall of the isolation structure 110 is even steeper, resulting in a shorter distance between the through holes 109 on both sides of the isolation structure 110, making it easier for metal to cross the isolation structure 110 and thus causing bridging. In this embodiment, please refer to... Figure 16 The facet tilt angle of the isolation structure 214 is gentle (i.e., the first included angle C is smaller than the second included angle D, with a gentle top and a steep bottom). When filling with metal, it is deposited only along the interior of the through hole 213. The bridging window is large, which can avoid problems such as copper bridging, contact resistance dispersion and sudden drop in process tolerance, and improve the yield of the device. Specifically, the top of the isolation structure 214 is widened, which increases the distance between the through holes 213 located on both sides of the isolation structure 214, making it less likely for metal to cross the bridging.

[0079] For details, please refer to Figure 17The diagram shows a working state of the etching method of the present invention. By setting the pressure of the reaction chamber to 105~115 mT (i.e., increasing the pressure of the reaction chamber), setting the high-frequency power to 1000-1200W, and setting the low-frequency power to 105~150 W (i.e., reducing the bias power), the bombardment direction of Ar atoms is dispersed, and the etching gas in the through hole 213 is uniformly distributed, thereby reducing the difference in Via-Via facet morphology. This, in turn, ensures that the reduction rate of the width of the longitudinal section of the isolation structure 214 from bottom to top remains stable, thus achieving the regularization of the inclined facet morphology.

[0080] To better showcase it across an entire wafer, Figure 4 The morphologies of the isolation structure 110 shown and the isolation structure 214 obtained by the etching method of the present invention were compared using the measured angle ratios, resulting in Table 1:

[0081] Table 1 Comparison of Angle Ratios

[0082]

[0083] Where A / B represents Figure 6 The ratio between included angle A and included angle B, where C / B represents the ratio between the first included angle C and the second included angle D. As can be seen from Table 1, the included angle ratio of the isolation structure 214 obtained by the etching method of the present invention is more stable throughout the entire wafer, indicating that the etching method of the present invention can improve the yield of the device.

[0084] As an example, during the etching process, the high-frequency power range is 1000~1200 W.

[0085] As an example, in the etching gas, the flow rate of CF4 is in the range of 100~300 sccm, the flow rate of O2 is in the range of 20~30 sccm, and the flow rate of Ar is in the range of 200~500 sccm.

[0086] In summary, the etching method of the present invention includes the following steps: providing a semiconductor structure, the semiconductor structure including a first wiring layer and a first etch stop layer, an interlayer dielectric layer and a hard mask layer stacked sequentially from bottom to top on the first wiring layer, wherein the hard mask layer has a first opening and the interlayer dielectric layer has at least two trenches, the trenches being located below the first opening and communicating with the first opening; etching the semiconductor structure based on the hard mask layer to extend the sidewall of the first opening into the interlayer dielectric layer and extend the bottom of the trenches to the side of the first etch stop layer away from the hard mask layer, forming a second opening and at least two vias exposing the metal wire layers in the first wiring layer, the vias being located below the second opening and communicating with the second opening, such that an isolation structure is formed between any two adjacent vias, and the pressure range of the reaction chamber during the etching process is 105~115 mT, the radio frequency power supply includes high frequency power and low frequency power, the low frequency power range is 105~150 W, and the etching gas includes CF4, O2 and Ar. The etching method of this invention, through the selection of etching gas and the setting of etching parameters, can reduce the difference in cross-sectional morphology between vias, ensure bridging between adjacent vias, and thus avoid problems such as copper bridging, contact resistance dispersion, and a sharp drop in process tolerance, thereby improving the mass production yield of devices and the reliability and lifespan of chips. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0087] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An etching method, characterized by, The method comprises the following steps: providing a semiconductor structure, the semiconductor structure comprising a first wiring layer and, stacked on the first wiring layer from bottom to top, a first etching stop layer, an interlayer dielectric layer and a hard mask layer, wherein a first opening is formed in the hard mask layer, and at least two grooves are formed in the interlayer dielectric layer, the grooves being located below the first opening and communicating with the first opening; etching the semiconductor structure based on the hard mask layer to extend the sidewall of the first opening into the interlayer dielectric layer, and to extend the groove bottom of the grooves to the side of the first etching stop layer away from the hard mask layer, thereby forming a second opening and at least two through holes exposing the metal wire layer in the first wiring layer, the through holes being located below the second opening and communicating with the second opening, and an isolation structure being formed between any two adjacent through holes, and the pressure range of the reaction chamber during the etching process being 105-115 mT, the radio frequency power source power including high frequency power and low frequency power, the low frequency power range being 105-150 W, and the etching gas including CF4, O2 and Ar.

2. The etching method of claim 1, wherein: In the XY plane, the width of the longitudinal section of the isolation structure gradually increases from bottom to top.

3. The etching method of claim 1, wherein: The tangent line at the top end of the longitudinal section of the isolation structure has a first included angle with the horizontal plane, and the tangent line at the bottom end of the longitudinal section of the isolation structure has a second included angle with the horizontal plane, the first included angle being on the outside of the isolation structure, the second included angle being on the inside of the isolation structure, and the first included angle being smaller than the second included angle.

4. The etching method according to claim 1, wherein The formation of the semiconductor structure comprises the following steps: providing the first wiring layer, the first wiring layer comprising the metal wire layer and a first dielectric layer wrapping the metal wire layer; forming the etching stop layer, the interlayer dielectric layer and the hard mask layer on the first dielectric layer in sequence; forming a patterned first photoresist layer on the hard mask layer, the first photoresist layer having a first window exposing the hard mask layer formed therein; performing photolithography on the hard mask layer based on the first photoresist layer to form the first opening in the hard mask layer, the first opening exposing the interlayer dielectric layer, and then removing the first photoresist layer; forming a patterned second photoresist layer on the hard mask layer, the first photoresist layer having a second window exposing the interlayer dielectric layer formed therein; performing photolithography on the hard mask layer based on the second photoresist layer to form the grooves in the interlayer dielectric layer, and then removing the second photoresist layer, thereby obtaining the semiconductor structure.

5. The etching method of claim 4, wherein: A second etching stop layer is further provided between the hard mask layer and the interlayer dielectric layer, during the photolithography on the hard mask layer based on the first photoresist layer, the first opening is formed in the hard mask layer, the second window exposes part of the hard mask layer at the bottom of the first opening, and the grooves extend through the hard mask layer and the second etching stop layer below the first opening and into the interlayer dielectric layer.

6. The etching method of claim 5, wherein: The hard mask layer comprises a first hard mask layer and a metal hard mask layer stacked in turn from bottom to top, the first opening penetrates the metal hard mask layer and extends to the first hard mask layer, the second window exposes part of the first hard mask layer at the bottom of the first opening, and the trench penetrates the first hard mask layer and the second etching stop layer below the first opening and extends to the interlayer dielectric layer.

7. The etching method of claim 5, wherein: The material of the first hard mask layer comprises a nitrogen-free anti-reflective coating, and the material of the metal hard mask layer comprises titanium nitride.

8. The etching method of claim 1, wherein: The first etching stop layer comprises a SiCN layer and a silicon dioxide layer covering the SiCN layer.

9. The etching method of claim 1, wherein: In the etching process, the high-frequency power range is 1000-1200 W.

10. The etching method of claim 1, wherein: In the etching gas, the flow rate of CF4 is 100-300 sccm, the flow rate of O2 is 20-30 sccm, and the flow rate of Ar is 200-500 sccm.

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