Power circuit package

Abstract

The power circuit package includes a patterned conductive layer disposed on the first side of the semiconductor substrate. The patterned conductive layer is configured to be electrically coupled to a first die disposed on the substrate, a heat sink disposed on the substrate, and a second die embedded in the substrate. The terminals, the via holes and the bonding pads of the patterned conductive layer form different conductive networks of the package. The radiator is arranged on the most busy network, so that the overall on-resistance of the circuit can be reduced.

Description

Technical Field

[0001] This application relates to a power supply circuit package. Background Technology

[0002] The development trend of power circuit packaging is driven by the demand from various industries, including consumer electronics and automotive, for more efficient and compact packages. Reducing the thermal resistance (TDR) of such packages is significant because lower TDR reduces power loss as heat during operation, which is crucial for maintaining the efficiency of electronic components and extending their lifespan. Furthermore, enhancing the thermal performance of power circuit packages is essential for effective heat dissipation, thereby ensuring system reliability and stability. Therefore, power circuit package design increasingly focuses on striking a balance between miniaturization, high power output, low TDR, and excellent thermal management. Summary of the Invention

[0003] According to some embodiments of this disclosure, a power circuit package includes a substrate, a first die, a second die, and a heat sink. The substrate has a first side and a second side opposite to the first side. The substrate includes a first patterned conductive layer located on the second side and a second patterned conductive layer located on the first side, wherein the first patterned conductive layer includes a first terminal, a second terminal, and a third terminal. The first die is disposed on the first side of the substrate and electrically coupled to the second patterned conductive layer. The second die is embedded in the substrate and electrically coupled to the second patterned conductive layer. The heat sink is disposed on the first side of the substrate and electrically coupled to the second patterned conductive layer, wherein the first terminal is electrically coupled to the first die, the third terminal is electrically coupled to the second die, and the second terminal is electrically coupled to both the first die and the second die.

[0004] In some embodiments, the substrate includes a first conductive via embedded therein, the first conductive via being configured to be electrically connected at one end to the second patterned conductive layer and at the other end to the first terminal, and wherein the substrate includes a second conductive via embedded therein, the second conductive via being configured to be electrically connected at one end to the second patterned conductive layer and at the other end to the second terminal.

[0005] In some embodiments, the substrate includes a third conductive via embedded therein, the third conductive via being configured to be electrically connected at one end to the second patterned conductive layer and at the other end to the second die.

[0006] In some embodiments, the substrate includes a third conductive via embedded therein, the third conductive via being configured to be electrically connected at one end to the third terminal and at the other end to the second die.

[0007] In some embodiments, the substrate further includes a fourth conductive via embedded therein, the fourth conductive via being configured to electrically connect the first die and the second die.

[0008] In some embodiments, the substrate further includes a first conductive via, a second conductive via, and a third conductive via embedded in the substrate, wherein the second patterned conductive layer includes a first pad and a second pad. The first pad, the first conductive via, and the first terminal are electrically connected to form a first conductive network of the power circuit package. The second pad, the second conductive via, and the second terminal are electrically connected to form a second conductive network of the power circuit package. The third conductive via, the third terminal, and the second die are electrically connected to form a third conductive network of the power circuit package. The first die is soldered to the first pad and the second pad. The heat sink is soldered to the second pad.

[0009] In some embodiments, the second patterned conductive layer further includes a third pad, the first patterned conductive layer further includes a fourth terminal, and the substrate further includes a fourth conductive via, wherein the third pad, the fourth conductive via, and the fourth terminal are electrically connected to form a fourth conductive network of the power circuit package.

[0010] According to some embodiments of this disclosure, a power supply circuit package includes a substrate, a first die, a second die, and a heat sink. The substrate has a first side and a second side opposite to the first side. The substrate includes a first patterned conductive layer on its second side and a second patterned conductive layer on its first side. The first die has a lateral field-effect transistor device internally therein, wherein the first die is electrically coupled to the second patterned conductive layer. The second die has a vertical field-effect transistor device internally therein, wherein the second die is embedded in the substrate and electrically coupled to the second patterned conductive layer. The heat sink is electrically coupled to the second patterned conductive layer, wherein the first patterned conductive layer includes a VIN terminal, an SW terminal, and a GND terminal. The VIN terminal is configured to be coupled to the input voltage of the buck converter, and the VIN terminal is electrically coupled to the first die. The GND terminal is configured to be coupled to the ground voltage of the buck converter, and the GND terminal is electrically coupled to the second die. The SW terminal is configured to be coupled to a switching node of the buck converter, and is electrically coupled to both the first die and the second die.

[0011] In some embodiments, the first die or the second die further includes a controller, and the first patterned conductive layer further includes a fourth terminal, wherein the fourth terminal is configured to connect to the controller and a die in the first die or the second die that does not include the controller.

[0012] According to a partial embodiment of this disclosure, a power supply circuit package includes a substrate, a first die, a second die, and a heat sink. The substrate has a first side and a second side opposite to the first side. The substrate includes a first patterned conductive layer on its second side and a second patterned conductive layer on its first side. The first die has a lateral field-effect transistor device internally therein, wherein the first die is electrically coupled to the second patterned conductive layer. The second die has a vertical field-effect transistor device internally therein, wherein the second die is embedded in the substrate and electrically coupled to the second patterned conductive layer. The heat sink is electrically coupled to the second patterned conductive layer. The first patterned conductive layer includes a VOUT terminal, an SW terminal, and a GND terminal. The VOUT terminal is configured to be coupled to the output voltage of the boost converter and is electrically coupled to the first die. The GND terminal is configured to be coupled to the ground voltage of the boost converter and is electrically coupled to the second die. The SW terminal is configured to be coupled to a switching node of the boost converter and is electrically coupled to both the first die and the second die.

[0013] In some embodiments, the first die or the second die further includes a controller, and the first patterned conductive layer further includes a fourth terminal, wherein the fourth terminal is configured to couple to the controller and to dies in the first die and the second die that do not include the controller. Attached Figure Description

[0014] Figure 1 This is a cross-sectional view showing a power supply circuit package according to an exemplary embodiment of the present disclosure.

[0015] Figure 2 This is a cross-sectional view showing a power supply circuit package according to an exemplary embodiment of the present disclosure.

[0016] Figure 3 This is a diagram illustrating the outline of a power circuit package according to an exemplary embodiment of the present disclosure.

[0017] Figure 4A This is a schematic diagram of a buck converter during the charging phase.

[0018] Figure 4B This is a schematic diagram of a buck converter during the discharge phase.

[0019] Figure 5A This is a cross-sectional view of the power supply circuit package used in a buck converter, showing the current direction of the buck converter during the charging phase.

[0020] Figure 5B This is a cross-sectional view of the power supply circuit package used in a buck converter, showing the current direction of the buck converter during the discharge phase.

[0021] Figure 6AThis is a schematic diagram of a boost converter during the charging phase.

[0022] Figure 6B This is a schematic diagram of a boost converter during the discharge phase.

[0023] Figure 7A This is a cross-sectional view of the power supply circuit package used in a boost converter, showing the current direction of the boost converter during the charging phase.

[0024] Figure 7B This is a cross-sectional view of the power supply circuit package used in a boost converter, showing the current direction of the boost converter during the discharge phase.

[0025] Figure 8 This is a cross-sectional view showing a power supply circuit package according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0026] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known materials or methods have not been specifically described to avoid obscuring the invention.

[0027] Throughout the specification and claims, unless the context clearly indicates otherwise, the articles “a,” “an,” and “the” all include the plural form. Phrases such as “an embodiment,” “a particular embodiment,” “an example,” and “an example” do not necessarily refer to the same embodiment or example. Furthermore, features, structures, or characteristics may be combined in one or more embodiments or examples. Throughout the specification and claims, the ordinal numbers “first,” “second,” and “third” are intended to indicate distinct features, not an order. For example, “second conductive network” is a conductive network different from “first conductive network.”

[0028] According to some embodiments disclosed herein Figure 1 , Figure 2 and Figure 3 An exemplary power supply circuit package structure is shown. Figure 1 This is a schematic diagram of a power supply circuit package 100. Figure 2 This is a schematic diagram of another proposed power supply circuit package 200. Figure 3 This is a outline view of an exemplary power supply circuit package 100. The following description will consistently refer to... Figure 1 , Figure 2 and Figure 3 .

[0029] Figure 1A power circuit package 100 according to an embodiment of the present disclosure is shown. The power circuit package 100 includes a first die 101, a second die 102, a substrate 103, and a heat sink 104. The substrate 103 may include a first side 103a and a second side 103b opposite to the first side 103a. The first side 103a is the side facing the first die 101 when the first die 101 is mounted to the substrate 103, while the second side 103b is the side facing away from the first die 101. The first die 101 and the heat sink 104 are both formed on the first side 103a, while the second die 102 is embedded in the substrate 103. The second side 104b of the heat sink can be exposed from the packaging material 110 to ensure that in a direction perpendicular to the substrate 103 (i.e., Figure 1 Better heat dissipation in the Z-axis direction. The first patterned conductive layer 120 may be exposed on the second side 103b of the substrate 103. The first patterned conductive layer 120 may include a first terminal 111, a second terminal 112, and a third terminal 113. The first terminal 111 may be electrically coupled to a first die 101. The third terminal 113 may be electrically coupled to a second die 102. The second terminal 112 may be electrically coupled to both the first die 101 and the second die 102.

[0030] The first die 101 may include a first side 101a on which electrodes are formed and a second side 101b opposite to the first side 101a. The first side 101a is the side facing the substrate 103 when the first die 101 is mounted to the substrate 103, while the second side 101b is the side facing away from the substrate 103. In one embodiment, the electrodes of the first die 101 are coupled to a second patterned conductive layer 106 on the first side 103a of the substrate 103 via solder 105a. Although Figure 1 Only five solders 105a are shown, but there may be dozens or hundreds of solders providing electrical connections between the first die 101 and the second patterned conductive layer 106.

[0031] The second patterned conductive layer 106 may consist of multiple pads, such as a first pad 107a and a second pad 107b, made of copper, aluminum, gold, or any suitable alloy. These pads of the second patterned conductive layer 106 are dielectrically isolated from each other so that they can be configured to connect or couple to different potentials. Traces can be arranged between the pads, which are intentionally designed to interconnect, to ensure they are connected and form a common node in the circuit. These pads may be a metal structure formed in the same manufacturing step, or they may be located on the same horizontal plane, so that even if the pads are not continuous metal layers, they are considered a single unit and referred to as the second patterned conductive layer 106. However, these pads are not necessarily formed in the same manufacturing step, nor are they necessarily located on the same horizontal plane.

[0032] Figure 3A outline diagram of an example power supply circuit package disclosed herein is shown. As shown in the figure, as... Figure 3 As shown, from the direction perpendicular to the first surface 103a of the substrate 103 (i.e. Figure 1 When viewed along the Z-axis, the first pad 107a of the first patterned conductive layer 106 can be configured to partially overlap with the projection area of ​​the first die 101 on the first surface 103a, facilitating the shortest connection between the first die 101 and the second patterned conductive layer 106. The second pad 107b of the first patterned conductive layer 106 can be configured to cover the entire projection area of ​​the second die 102 and serve as an island structure connecting the large heat sink 104. Figure 1 As shown, solder or sintered metal 105b can be applied to the second pad 107b to electrically and mechanically couple the first side 104a of the heat sink 104 to the second patterned conductive layer 106. In one embodiment, some electrodes of the first die 101 are coupled to the first pad 107a, and some other electrodes of the first die 101 are connected to the second pad 107b.

[0033] The substrate 103 may be formed of an insulating or dielectric material, such as glass, FR-4, cotton paper-reinforced epoxy, glass-reinforced epoxy, or any other suitable choice. The substrate 103 may include a plurality of conductive vias extending therethrough. Figure 1 As shown, the first conductive via 108a is configured to be electrically connected at one end to the first pad 107a and at the other end to the first terminal 111, thereby coupling the first terminal 111 to the first die 101 and forming together with it the first conductive network 121 of the power circuit package 100. The second conductive via 108b is configured not to include the projection areas of the first die 101 and the second die 102 on the first surface 103a. One end of the second conductive via 108b is electrically connected to the second pad 107b and the other end is electrically connected to the second terminal 112, coupling the second terminal 112 to the first die 101, the second die 102 and the heat sink 104, and forming together with it the second conductive network 122 of the power circuit package 100.

[0034] The second die 102 may include a first side 102a on which electrodes are formed and a second side 102b on which electrodes are formed. The first side 102a is the side facing the first side 103a of the substrate 103 when the second die 102 is embedded in the substrate 103, while the second side 102b is the side facing away from the first side 103a of the substrate 103. In one embodiment, as... Figure 1As shown, a plurality of third conductive vias 109 are embedded in the substrate, extending from the first side 102a to the second pad 107b, to electrically connect the second patterned conductive layer 106 to the electrodes of the second die 102 on the first side 102a of the second die 102. The electrodes of the second die 102 on the second side 102b of the second die 102 can be electrically connected to the third terminal 113, forming a third conductive network 123 of the power circuit package 100 together with the plurality of third conductive vias 109 and the second die 102. However, in another embodiment, as Figure 2 As shown, a plurality of third conductive vias 109 are embedded in the substrate, extending from the second side 102b to the first patterned conductive layer 120, to electrically connect the third terminal 113 to the electrode of the second die 102 on the second side 102b of the second die 102. The electrode of the second die 102 on the first side 102a of the second die 102 can be electrically connected to the second pad 107b, forming a third conductive network 123 of the power circuit package 100 together with the plurality of third conductive vias 109 and the second die 102.

[0035] As described above, the second conductive network 122 is electrically coupled to the first die 101, the second die 102, and the heat sink 104. Therefore, it is the "busiest" of the three networks. Placing the heat sink 104 on this network can effectively enhance the current-carrying capacity of the "busiest" network, thereby reducing the overall on-resistance of the circuit. To better illustrate the contents of this disclosure, several exemplary circuit package structures will be described below.

[0036] Now for reference Figure 4A and Figure 4B The operation of a typical buck converter 400 can be described in two main phases: the charging phase (e.g., Figure 4A ) and discharge phase (e.g., Figure 4B The buck converter 400 may include a first switch 401 and a second switch 402, which are connected in series between the input voltage Vin and ground GND. The first switch 401 and the second switch 402 are connected at the first switching node SW1. An inductor L1 is connected between the first switching node SW1 and the output voltage Vout. One of the two switches is turned on and the other is turned off by gate signals (i.e., gate signals Gate_1 and Gate_2). The input voltage Vin or ground GND can be electrically connected to the first switching node SW1, and then current flows through the first inductor L1.

[0037] refer to Figure 5A and Figure 5B , Figure 1Some reference numerals in the diagram are replaced with reference numerals for circuit components of the buck converter 400, while other reference numerals remain unchanged. In this embodiment, the power supply circuit package disclosed herein can be used to package the buck converter 400 and can reduce its overall on-resistance. The first die 101 of the package 100 may be a die containing the first switch 401 of the buck converter 400, which may be a lateral field-effect transistor (FET) device. The second die 102 of the package 100 may be a die containing the second switch 402 of the buck converter 400, which may be a longitudinal field-effect transistor device. Furthermore, the first terminal 111 may be configured to couple to the input voltage Vin and serve as the VIN terminal of the power supply circuit package 100, such that the first conductive network 121 becomes the VIN network. The second terminal 112 may be configured to couple to the first switch node SW1 and serve as the SW terminal of the power supply circuit package 100, such that the second conductive network 122 becomes the SW network. The third terminal 113 can be configured as the GND terminal of the power supply circuit package 100, making the third conductive network 123 a GND network. Other components of the buck converter are not included. Figure 5A As shown in the diagram. For example, the first inductor L1 can be located outside the power supply circuit package.

[0038] See Figure 5A During the charging phase, the second switch 402 is closed, decoupling the GND network (i.e., the third conductive network 123) from the SW network (i.e., the second conductive network 122). Current flows completely from the VIN terminal (i.e., the first terminal 111) through the VIN network (i.e., the first conductive network 121) and the SW network (i.e., the second conductive network 122) to the SW terminal (i.e., the second terminal 112). See also... Figure 5B During the discharge phase, the first switch 401 is closed, decoupling the VIN network (i.e., the first conductive network 121) from the SW network (i.e., the second conductive network 122). Current flows completely from the GND terminal (i.e., the third terminal 113) through the GND network (i.e., the third conductive network 123) and the SW network (i.e., the second conductive network 122) to the SW terminal (i.e., the second terminal 112). Figure 5A and Figure 5B As shown, the SW network (i.e., the second conductive network 122) is active regardless of which phase the buck converter 400 is operating in. By configuring the copper strip 104 as part of the second conductive network 122, the current-carrying capacity of this busy network can be significantly enhanced.

[0039] Now for reference Figure 6A and Figure 6B The operation of a typical boost converter 600 can also be described in two main phases: the charging phase (e.g., Figure 6A ) and discharge phase (e.g., Figure 6BThe boost converter 600 may include a first switch 601 and a second switch 602, which are connected in series between the output voltage Vout and ground GND. The first switch 601 and the second switch 602 are connected at a second switching node SW2. An inductor L2 is connected between the second switching node SW2 and the input voltage Vin. By controlling one of the two switches to be on and the other off, the output voltage Vout or ground GND can be electrically connected to the second switching node SW2, and the current flowing through the inductor L2 can then be conducted.

[0040] refer to Figure 7A and Figure 7B , Figure 1 Some reference numerals in the diagram are replaced with reference numerals for circuit elements of the boost converter 600, while other reference numerals remain unchanged. The power supply package disclosed herein can be used in the boost converter 600 and can reduce overall on-resistance. The first die 101 of package 100 may be a die containing a first switch 601 of the boost converter 600, which may be a lateral field-effect transistor device. The second die 102 of package 100 may be a die containing a second switch 602 of the boost converter 600, which may be a longitudinal field-effect transistor device. Furthermore, the first terminal 111 may be configured to couple to the output voltage Vout and serve as the VOUT terminal of the power supply package 100, making the first conductive network 121 a VOUT network. The second terminal 112 may be configured to couple to the second switch node SW2 and serve as the SW terminal of the power supply package 100, making the second conductive network 122 a SW network. The third terminal 113 may be configured as the GND terminal of the power supply package 100, making the third conductive network 123 a GND network. Other components of the boost converter are described in... Figure 7A Not shown in the diagram. For example, the second inductor L2 may be located outside the power supply circuit package.

[0041] refer to Figure 7A During the charging phase, the first switch 601 is opened, decoupling the VOUT network (i.e., the first conductive network 121) from the SW network (i.e., the second conductive network 122). Current flows completely from the SW terminal (i.e., the second terminal 112) through the SW network (i.e., the second conductive network 122) and the GND network (i.e., the third conductive network 123) to the GND terminal (i.e., the third terminal 113). (Reference) Figure 6BDuring the discharge phase, the second switch 602 is open, decoupling the GND network (i.e., the third conductive network 123) from the SW network (i.e., the second conductive network 122). Current flows completely from the SW terminal (i.e., the second terminal 112) through the SW network (i.e., the second conductive network 122) and the VOUT network (i.e., the first conductive network 121) to the VOUT terminal (i.e., the first terminal 111). Regardless of which phase the boost converter 600 operates in, the SW network (i.e., the second conductive network 122) remains active. By configuring the copper strip 104 as part of this busy second conductive network 122, the converter's conduction losses can be reduced.

[0042] The roles of the first terminal 111, the second terminal 112, and the third terminal 113 depend on the arrangement of the circuit elements within the package; the above embodiments are merely examples. Furthermore, the power supply circuit package 100 can also be used to implement package structures for other circuits.

[0043] In the embodiments of Figures 5 and 7, the gate signals controlling the first and second dies can be provided by another die not shown in the package. However, in another embodiment disclosed herein, the controller can be integrated with the switching device in the first or second die, and the package may further include a gate network. Reference Figure 8 In the package 800, the second patterned conductive layer 106 may further include a third pad 107c, which is connected to the electrode of the first die 101 and coupled to a controller 140 integrated with the first switch in the first die 101. The first patterned conductive layer 120 may further include a fourth terminal 114, which is connected to the electrode of the second die 102 on its second side 102b. One end of the fourth conductive via 108c is electrically connected to the third pad 107c, and the other end is electrically connected to the fourth terminal 114, connecting the fourth terminal 114 to the first die 101 and the second die 102, and together forming the gate network 124 of the power circuit package 100. Figure 8 As shown, the fourth terminal 114 may not be exposed from the solder mask layer 130. In some embodiments, the first patterned conductive layer 120 may further include a fifth terminal 115, which may be connected to the electrode of the first die 101 and serve as a general-purpose input / output (GPIO) terminal of the controller 140. The fifth conductive via 108d is configured with one end electrically connected to the fourth pad 107d and the other end electrically connected to the fifth terminal 115, coupling the fifth terminal 115 to the first die 101 and forming together with it the GPIO network of the power circuit package 100.

[0044] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A power supply circuit package, characterized in that, include: A substrate having a first side and a second side opposite to the first side, the substrate including a first patterned conductive layer located on the second side and a second patterned conductive layer located on the first side, wherein the first patterned conductive layer includes a first terminal, a second terminal and a third terminal; A first grain is disposed on the first side of the substrate and electrically coupled to the second patterned conductive layer; The second grain is embedded in the substrate and electrically coupled to the second patterned conductive layer; as well as A heat sink is disposed on the first side of the substrate and electrically coupled to the second patterned conductive layer, wherein the first terminal is electrically coupled to the first die, the third terminal is electrically coupled to the second die, and the second terminal is electrically coupled to both the first die and the second die.

2. The power supply circuit package as described in claim 1, characterized in that, The substrate includes a first conductive via embedded therein, the first conductive via being configured to be electrically connected at one end to the second patterned conductive layer and at the other end to the first terminal, and wherein the substrate includes a second conductive via embedded therein, the second conductive via being configured to be electrically connected at one end to the second patterned conductive layer and at the other end to the second terminal.

3. The power supply circuit package as described in claim 2, characterized in that, The substrate includes a third conductive via embedded therein, the third conductive via being configured to be electrically connected at one end to the second patterned conductive layer and at the other end to the second grain.

4. The power supply circuit package as described in claim 2, characterized in that, The substrate includes a third conductive via embedded therein, the third conductive via being configured to be electrically connected at one end to the third terminal and at the other end to the second die.

5. The power supply circuit package as described in claim 2, characterized in that, The substrate further includes a fourth conductive via embedded therein, the fourth conductive via being configured to electrically connect the first die and the second die.

6. The power supply circuit package as described in claim 1, characterized in that, The substrate further includes a first conductive via, a second conductive via, and a third conductive via embedded in the substrate, and the second patterned conductive layer includes a first pad and a second pad. The first pad, the first conductive via, and the first terminal are electrically connected to form the first conductive network of the power circuit package. The second pad, the second conductive via, and the second terminal are electrically connected to form the second conductive network of the power circuit package. The third conductive via, the third terminal, and the second die are electrically connected to form the third conductive network of the power circuit package. Wherein, the first die is soldered to the first pad and the second pad, and The heat sink is soldered to the second pad.

7. The power supply circuit package as described in claim 6, characterized in that, The second patterned conductive layer further includes a third pad, the first patterned conductive layer further includes a fourth terminal, and the substrate further includes a fourth conductive via, wherein the third pad, the fourth conductive via, and the fourth terminal are electrically connected to form a fourth conductive network of the power circuit package.

8. A power supply circuit package, characterized in that, include: A substrate having a first side and a second side opposite to the first side, the substrate including a first patterned conductive layer on its second side and a second patterned conductive layer on its first side; A first die having a lateral field-effect transistor device inside, wherein the first die is electrically coupled to the second patterned conductive layer; A second die having a vertical field-effect transistor device therein, wherein the second die is embedded in the substrate and electrically coupled to the second patterned conductive layer; and The heat sink is electrically coupled to the second patterned conductive layer, wherein the first patterned conductive layer includes a VIN terminal, a SW terminal, and a GND terminal. The VIN terminal is configured to be coupled to the input voltage of the buck converter, and the VIN terminal is electrically coupled to the first die. The GND terminal is configured to be coupled to the ground voltage of the buck converter, and the GND terminal is electrically coupled to the second die. The SW terminal is configured to be coupled to the switching node of the buck converter and electrically coupled to the first die and the second die.

9. The power supply circuit package as described in claim 8, characterized in that, The first or second die further includes a controller, and the first patterned conductive layer further includes a fourth terminal, wherein the fourth terminal is configured to connect to the controller and to dies in the first and second dies that do not include the controller.

10. A power supply circuit package, characterized in that, include: A substrate having a first side and a second side opposite to the first side, the substrate including a first patterned conductive layer on its second side and a second patterned conductive layer on its first side; A first die having a lateral field-effect transistor device inside, wherein the first die is electrically coupled to the second patterned conductive layer; A second die having a vertical field-effect transistor device therein, wherein the second die is embedded in the substrate and electrically coupled to the second patterned conductive layer; and The heat sink is electrically coupled to the second patterned conductive layer, wherein the first patterned conductive layer includes a VOUT terminal, a SW terminal, and a GND terminal. The VOUT terminal is configured to be coupled to the output voltage of the boost converter, and the VOUT terminal is electrically coupled to the first die. The GND terminal is configured to be coupled to the ground voltage of the boost converter, and the GND terminal is electrically coupled to the second die. The SW terminal is configured to be coupled to the switching node of the boost converter and electrically coupled to the first die and the second die.

11. The power supply circuit package as described in claim 10, characterized in that, The first or second die further includes a controller, and the first patterned conductive layer further includes a fourth terminal, wherein the fourth terminal is configured to be coupled to the controller and to dies in the first and second dies that do not include the controller.

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