Short-circuit protection testing device and system

Abstract

The invention discloses a short-circuit protection testing device and system. The device comprises a main control unit, a relay, a contactor and a communication unit, the relay is electrically connected with the contactor; the relay, the contactor and the communication unit are electrically connected with the to-be-tested equipment respectively; the main control unit is used for controlling on-off of the relay according to the test time sequence; after the relay is closed, the to-be-tested equipment operates under a target working condition, and the contactor controls one field-effect tube of the to-be-tested equipment to be short-circuited so as to realize short-circuit protection test; the communication unit is used for inquiring and sending the current state of the to-be-tested equipment to the main control unit, so that the main control unit determines whether the to-be-tested equipment breaks down or not according to the current state, and the test process is ended when the to-be-tested equipment breaks down. According to the scheme, on-off of the relay can be controlled based on the test time sequence, so that automatic start and stop of test are realized, and equipment damage caused by long-time test is avoided; meanwhile, real-time monitoring of the equipment state can be achieved before testing or in the testing process, invalid testing is avoided, and the testing efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of circuit testing technology, and in particular to a short-circuit protection testing device and system. Background Technology

[0002] As the core power control component of electric vehicles, the safety and reliability of the controller directly affect the vehicle's performance, service life, and driver safety. Among various controller failures, short-circuit failure of MOSFETs is one of the most dangerous failure modes. Therefore, thorough and reliable testing and verification of the short-circuit protection function of MOSFETs has become an indispensable part of controller research and development and production.

[0003] Most existing short-circuit protection testing devices simulate speed control signals by setting the relay switching time using a digital display time controller, and simultaneously control the MOSFET short circuit by setting the contactor switching time. An electronic counter records the number of protection tests to achieve the purpose of short-circuit protection testing. However, the digital display time controller cannot automatically stop during the test, forcing testers to remain by the device for extended periods until the test is complete. Failure to shut it down in time can damage the device under test, resulting in economic losses. Furthermore, the digital display time controller only controls the on / off switching of relays and contactors, and cannot meet the needs of more efficient and safer testing. Summary of the Invention

[0004] This invention provides a short-circuit protection testing device and system that can control the opening and closing of relays based on the test timing, thereby realizing automatic start and stop of the test and avoiding equipment damage caused by long-term testing; at the same time, it can realize real-time monitoring of equipment status before and during the test, avoid invalid testing, and improve test efficiency.

[0005] According to one aspect of the present invention, a short-circuit protection testing device is provided, comprising: a main control unit, a relay, a contactor, and a communication unit; wherein the main control unit is electrically connected to the relay and the communication unit respectively, and the relay is electrically connected to the contactor; the relay, the contactor, and the communication unit are electrically connected to the device under test (DUT); the main control unit is used to control the opening and closing of the relay according to the test sequence; after the relay is closed, the DUT operates under the target operating condition, and the contactor controls a field-effect transistor of the DUT to short-circuit, thereby realizing the short-circuit protection test; the communication unit is used to query and send the current status of the DUT to the main control unit, so that the main control unit can determine whether the DUT has failed based on the current status, and terminate the test process when the DUT fails.

[0006] Optionally, it also includes: a human-computer interaction unit; the human-computer interaction unit is electrically connected to the main control unit and is used to display test information, as well as to acquire and send test parameters input by the user to the main control unit, so that the main control unit can determine the test sequence according to the test parameters.

[0007] Optionally, it also includes: a power supply unit; the power supply unit is electrically connected to the main control unit, relays, and contactors respectively, and is used to power the short circuit protection test device based on the Universal Serial Bus (USB) power transfer (PD) protocol.

[0008] Optionally, the power supply unit includes: a decoy circuit, a boost circuit, a first buck circuit, a second buck circuit, and a third buck circuit; the decoy circuit is connected to an external power source through a power interface and is used to decoy the voltage provided by the external power source to a first voltage; the boost circuit is electrically connected to the decoy circuit and is used to boost the first voltage to a second voltage and supply power to the contactor; the first buck circuit is electrically connected to the decoy circuit and is used to step down the first voltage to a third voltage and supply power to the relay; the second buck circuit is electrically connected to the first buck circuit and is used to step down the third voltage to a fourth voltage and supply power to the main control unit; the third buck circuit is electrically connected to the first buck circuit and is used to step down the third voltage to a fifth voltage, so that the third buck circuit provides auxiliary power to the device under test.

[0009] Optionally, the number of third buck circuits is at least two, and different third buck circuits enable the device under test to operate under different conditions; one of the at least two third buck circuits enables the device under test to operate in standby mode, and the other of the at least two third buck circuits enables the device under test to operate in full-speed mode.

[0010] Optionally, the decoy circuit includes: a first chip, a first capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; wherein, the DP pin, DM pin, CC1 pin, and CC2 pin of the first chip are electrically connected to the power interface respectively; the CC1 pin and CC2 pin of the first chip are electrically connected to one end of the first resistor and one end of the second resistor respectively; the other ends of the first resistor and the second resistor are both grounded; the VBUS pin of the first chip is electrically connected to one end of the third resistor, and the other end of the third resistor outputs a first voltage; the CFG1 pin, CFG2 pin, and CFG3 pin of the first chip are electrically connected to one end of the fourth resistor, one end of the fifth resistor, and one end of the sixth resistor respectively; the other ends of the fourth resistor and the sixth resistor are both grounded; the other end of the fifth resistor is connected to the power supply voltage; the VDD pin of the first chip is connected to the power supply voltage and is electrically connected to one end of the seventh resistor and one end of the first capacitor; the other end of the seventh resistor outputs the first voltage; the other end of the first capacitor and the GND pin of the first chip are both grounded.

[0011] Optionally, the boost circuit includes: a second chip, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, an eighth resistor, a ninth resistor, a tenth resistor, a first diode, and an inductor; wherein, the VIN pin of the second chip, one end of the second capacitor, one end of the third capacitor, and one end of the inductor are all connected to a first voltage; the COMP pin of the second chip is electrically connected to one end of the eighth resistor, and the other end of the eighth resistor is electrically connected to one end of the fourth capacitor; the other ends of the second capacitor, the third capacitor, the fourth capacitor, and the GND1 pin of the second chip are all grounded; the SWITCH pin of the second chip is electrically connected to the other end of the inductor and the positive terminal of the first diode, and the negative terminal of the first diode outputs a second voltage; the negative terminal of the first diode is electrically connected to one end of the fifth capacitor, one end of the sixth capacitor, and one end of the ninth resistor, and the other end of the ninth resistor is electrically connected to one end of the tenth resistor and the FEEDBACK pin of the second chip; the other ends of the fifth capacitor, the sixth capacitor, the tenth resistor, and the GND2 pin of the second chip are all grounded.

[0012] Optionally, the first step-down circuit includes: a third chip, a seventh capacitor, an eighth capacitor, and a second diode; wherein, the VIN pin of the third chip is connected to the first voltage, and the VOUT1 and VOUT2 pins of the third chip are both electrically connected to one end of the seventh capacitor, one end of the eighth capacitor, and the positive terminal of the second diode; the GND pin of the third chip, the other end of the seventh capacitor, and the other end of the eighth capacitor are all grounded; the negative terminal of the second diode outputs the third voltage.

[0013] Optionally, the second step-down circuit includes: a fourth chip, a ninth capacitor, a tenth capacitor, an eleventh resistor, a third diode, and a fourth diode; wherein, the VIN pin of the fourth chip is connected to the third voltage, and the VOUT1 and VOUT2 pins of the fourth chip are both electrically connected to one end of the ninth capacitor, one end of the tenth capacitor, and the positive terminal of the third diode; the negative terminal of the third diode is electrically connected to one end of the eleventh resistor, and the other end of the eleventh resistor is electrically connected to the positive terminal of the fourth diode; the GND pin of the fourth chip, the other end of the ninth capacitor, the other end of the tenth capacitor, and the negative terminal of the fourth diode are all grounded; the negative terminal of the third diode outputs the fourth voltage.

[0014] Optionally, the third step-down circuit includes: a fifth chip, an eleventh capacitor, a twelfth capacitor, a twelfth resistor, and a thirteenth resistor; wherein, the VIN and EN pins of the fifth chip and one end of the eleventh capacitor are all connected to the third voltage; the VOUT pin of the fifth chip is electrically connected to one end of the thirteenth resistor and one end of the twelfth capacitor, respectively; the SNS / NC pins of the fifth chip are electrically connected to one end of the twelfth resistor and the other end of the thirteenth resistor, respectively; the GND pin of the fifth chip, the other end of the eleventh capacitor, the other end of the twelfth capacitor, and the other end of the twelfth resistor are all grounded; the VOUT pin of the fifth chip outputs the fifth voltage.

[0015] Optionally, it also includes: a prompting unit; the prompting unit is electrically connected to the main control unit and is used to send a prompt message after the test is completed.

[0016] Optionally, the prompting unit includes: a fourteenth resistor, a fifth diode, a transistor, and a prompting device; one end of the fourteenth resistor is electrically connected to the main control unit, and the other end of the fourteenth resistor is electrically connected to the base of the transistor, and the emitter of the transistor is grounded; the collector of the transistor is electrically connected to the anode of the fifth diode and the cathode of the prompting device, respectively; the cathode of the fifth diode and the anode of the prompting device are connected to a third voltage.

[0017] According to another aspect of the present invention, a short-circuit protection test system is provided, including the short-circuit protection test apparatus of any of the above embodiments; wherein the short-circuit protection test system is electrically connected to the device under test.

[0018] Optionally, the device under test is the controller of an electric vehicle.

[0019] The technical solution of this invention, through the design of a short-circuit protection testing device, includes a main control unit, relays, contactors, and a communication unit. The main control unit controls the opening and closing of the relays according to the test sequence. After the relays are closed, the device under test (DUT) operates under the target condition, and the contactor controls a short circuit in one of the DUT's MOSFETs to achieve short-circuit protection testing. The communication unit queries and sends the current status of the DUT to the main control unit, enabling the main control unit to determine whether a fault has occurred in the DUT based on the current status and terminate the test process when a fault occurs. On one hand, because the main control unit can control the opening and closing of the relays according to the test sequence, and the test stops after the test sequence ends, automatic start and stop of the test can be achieved, avoiding equipment damage caused by repeated short circuits of the MOSFET over a long period, thereby reducing production costs. On the other hand, by querying the current status of the DUT through the newly added communication unit, real-time monitoring of the equipment status can be achieved throughout the entire time period (i.e., before / during the test). Once the main control unit detects a fault in the DUT, it can directly terminate the test process, avoiding invalid testing and improving test efficiency. It also enriches the functions of the main control unit, enabling the short-circuit protection test device to adapt to more efficient and safer testing needs.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a short-circuit protection testing device provided in Embodiment 1 of the present invention;

[0023] Figure 2 This is a schematic diagram of another short-circuit protection testing device provided in Embodiment 1 of the present invention;

[0024] Figure 3 This is a schematic diagram of the structure of another short-circuit protection testing device provided in Embodiment 1 of the present invention;

[0025] Figure 4 This is a circuit structure diagram of a prompting unit provided in Embodiment 1 of the present invention;

[0026] Figure 5This is a schematic diagram of another short-circuit protection testing device provided in Embodiment 1 of the present invention;

[0027] Figure 6 This is a schematic diagram of the structure of a power supply unit provided in Embodiment 1 of the present invention;

[0028] Figure 7 This is a circuit structure diagram of a power interface provided in Embodiment 1 of the present invention;

[0029] Figure 8 This is a circuit structure diagram of a deception circuit provided in Embodiment 1 of the present invention;

[0030] Figure 9 This is a circuit structure diagram of a boost circuit provided in Embodiment 1 of the present invention;

[0031] Figure 10 This is a circuit structure diagram of a first step-down circuit provided in Embodiment 1 of the present invention;

[0032] Figure 11 This is a circuit structure diagram of a second step-down circuit provided in Embodiment 1 of the present invention;

[0033] Figure 12 This is a circuit structure diagram of a third step-down circuit provided in Embodiment 1 of the present invention;

[0034] Figure 13 This is a circuit structure diagram of a switching circuit provided in Embodiment 1 of the present invention;

[0035] Figure 14 This is a circuit structure diagram of a filter circuit provided in Embodiment 1 of the present invention. Detailed Implementation

[0036] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0037] It should be noted that the terms "first," "second," "third," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0038] Example 1

[0039] Figure 1 This is a schematic diagram of a short-circuit protection testing device according to Embodiment 1 of the present invention. The short-circuit protection testing device is used to perform short-circuit protection testing on the MOSFETs of the device under test. Typically, the device under test may include one MOSFET, or it may include multiple MOSFETs. One test cycle is performed on one MOSFET. Figure 1 As shown, the short-circuit protection testing device includes: a main control unit 10, a relay 20, a contactor 30, and a communication unit 40. The main control unit 10 is electrically connected to both the relay 20 and the communication unit 40, and the relay 20 is electrically connected to the contactor 30. The relay 20, contactor 30, and communication unit 40 are all electrically connected to the device under test.

[0040] The main control unit 10 is the decision-making core of the short-circuit protection test device, responsible for scheduling the coordinated operation of all components. The main control unit 10 can have functions such as precisely controlling the test timing, interacting with the communication unit 40, and recording the number of tests, thereby meeting various test requirements.

[0041] Specifically, the main control unit 10 can be used to control the opening and closing of relays according to the test timing sequence. The test timing sequence is a standardized sequence generated by the main control unit 10 that indicates the time sequence, triggering conditions, duration, and interval logic of the relay opening and closing.

[0042] Optionally, the main control unit 10 can be a microcontroller unit (MCU). The MCU can integrate multiple functions such as time control, count statistics, status judgment, and instruction output, replacing multiple discrete components such as traditional digital display time controllers and electronic counters, making the short circuit protection test device more integrated and intelligent.

[0043] Relay 20 is electrically connected to the device under test (DUT). When closed, relay 20 provides a speed control signal to the DUT, causing it to operate under target conditions. By adjusting the speed control signal, testing under different conditions can be achieved.

[0044] Contactor 30 is electrically connected to a MOSFET of the device under test. When relay 20 is closed, contactor 30 also closes, thereby controlling the connected MOSFET to short-circuit, thus achieving short-circuit protection testing.

[0045] Optionally, contactor 30 can be a DC contactor.

[0046] The communication unit 40 is electrically connected to the communication circuit of the device under test (DUT). By communicating with the DUT's communication circuit, the communication unit 40 queries the DUT's current status and then sends this status to the main control unit 10. The main control unit 10 then determines whether the DUT has malfunctioned based on the current status and terminates the test process if a malfunction is detected. This allows for real-time monitoring of the device status throughout the entire testing period (before and during testing). Once the main control unit 10 detects a malfunction in the DUT, it can directly terminate the test process, avoiding invalid testing and improving testing efficiency.

[0047] The communication unit 40 can be configured according to the type of device under test. Optionally, the communication unit 40 can be implemented using a serial port circuit, an RS485 protocol circuit, or a Controller Area Network (CAN) communication protocol circuit.

[0048] Based on the above embodiments, Figure 2 This is a schematic diagram of another short-circuit protection testing device provided in Embodiment 1 of the present invention. Figure 2 As shown, the short-circuit protection test device may also include: a human-machine interaction unit 50.

[0049] Specifically, the human-machine interface unit 50 is electrically connected to the main control unit 10 and is used to display test information and acquire and send user-inputted test parameters to the main control unit 10, so that the main control unit 10 can determine the test sequence based on the test parameters. The test information displayed by the human-machine interface unit 50 may include, but is not limited to, at least one of the following: current number of tests, maximum number of tests, and short-circuit time. The test parameters input by the user may include, but are not limited to, at least one of the following: maximum number of tests, short-circuit time, and target operating condition.

[0050] The human-computer interaction unit 50 can also save the above test parameters and test information to avoid the repeated setup / debugging process before the next test, thereby further improving test efficiency.

[0051] Optionally, the human-computer interaction unit 50 can be a touch screen, or a display screen plus input device, or other devices capable of interactive functions.

[0052] Based on the above embodiments, Figure 3 This is a structural schematic diagram of another short-circuit protection testing device provided in Embodiment 1 of the present invention. Figure 3 As shown, the short-circuit protection test device may also include: a notification unit 60.

[0053] Specifically, the prompting unit 60 is electrically connected to the main control unit 10 and is used to send a prompt message after the test is completed. This reminds the user that the test is complete, allowing the user to disconnect the short-circuit protection test device from the device under test, or switch to the next MOSFET for testing. Additionally, the prompting unit 60 can also trigger an alarm when the main control unit 10 determines that the device under test has malfunctioned.

[0054] In one embodiment, Figure 4 This is a circuit structure diagram of a prompting unit provided in Embodiment 1 of the present invention. Figure 4 As shown, the prompting unit 60 includes: a fourteenth resistor R14, a fifth diode D5, a transistor Q, and a prompting device BUZZER.

[0055] One end of the fourteenth resistor R14 is electrically connected to the main control unit 10 (e.g., to the BUZZ pin of the main control unit 10), and the other end of the fourteenth resistor R14 is electrically connected to the base of the transistor Q, and the emitter of the transistor Q is grounded; the collector of the transistor Q is electrically connected to the anode of the fifth diode D5 and the cathode of the prompting device BUZZER, respectively; the cathode of the fifth diode D5 and the anode of the prompting device BUZZER are connected to the third voltage Vout3.

[0056] Optionally, the notification device BUZZER can be any device that can provide a notification effect, such as a buzzer or status indicator light. The third voltage Vout3 can be 5V.

[0057] Based on the above embodiments, Figure 5 This is a schematic diagram of another short-circuit protection testing device provided in Embodiment 1 of the present invention. Figure 5 As shown, the short-circuit protection test device may also include: a power supply unit 70.

[0058] Specifically, the power supply unit 70 is electrically connected to the main control unit 10, the relay 20, and the contactor 30, respectively, and is used to supply power to the short circuit protection test device based on the Universal Serial Bus (USB) Power Delivery (PD) protocol.

[0059] The USB PD protocol is a power transfer protocol based on the USB Type-C interface. It enables bidirectional data interaction between the power supply and the power receiving end, dynamically negotiating the optimal voltage and current combination, breaking through the power limitations of traditional USB, and is compatible with data transmission, audio and video transmission, and other functions. The power supply unit 70 uses the USB PD protocol to power the short-circuit protection test device, thus realizing Type-C power supply. This converts the traditional 220V AC power supply of the device into a low-voltage power supply, ensuring the personal safety of test personnel and improving test safety.

[0060] In one embodiment, Figure 6 This is a schematic diagram of the structure of a power supply unit provided in Embodiment 1 of the present invention. Figure 6 As shown, the power supply unit 70 includes: a deception circuit 71, a boost circuit 72, a first buck circuit 73, a second buck circuit 74, and a third buck circuit 75.

[0061] Specifically, the decoy circuit 71 is connected to an external power source via a power interface (such as a Type-C interface) to decoy the voltage supplied by the external power source to a first voltage, which serves as the main power supply for the short-circuit protection test device. The boost circuit 72 is electrically connected to the decoy circuit 71 to boost the first voltage to a second voltage and supply power to the contactor 30. The first buck circuit 73 is electrically connected to the decoy circuit 71 to step down the first voltage to a third voltage and supply power to the relay 20. The second buck circuit 74 is electrically connected to the first buck circuit 73 to step down the third voltage to a fourth voltage and supply power to the main control unit 10. The third buck circuit 75 is electrically connected to the first buck circuit 73 to step down the third voltage to a fifth voltage, enabling the third buck circuit 75 to provide auxiliary power to the device under test.

[0062] Optionally, the first voltage can be 20V, the second voltage can be 24V, the third voltage can be 5V, and the fourth voltage can be 3.3V.

[0063] In one embodiment, the number of third buck circuits 75 is at least two. Figure 6 The diagram shows two third buck circuits 75. Different third buck circuits 75 correspond to different values ​​of the fifth voltage, thus enabling the third buck circuit 75 to provide different auxiliary power supplies to the device under test, thereby allowing the device under test to operate under different conditions.

[0064] Typically, one of at least two third buck circuits 75 is configured to operate the device under test (DUT) in standby mode, and the other of at least two third buck circuits 75 operates the DUT at full speed. That is, one third buck circuit 75 allows the DUT to operate in standby mode, while the other third buck circuit 75 allows the DUT to operate at full speed. This allows for testing of the DUT in both standby and full-speed modes.

[0065] Understandably, the third step-down circuit 75 can also enable the device under test to operate in other conditions (such as half-speed, acceleration, deceleration, etc.), which can be achieved by adjusting the value of the fifth voltage.

[0066] Optionally, the value of the fifth voltage can be in the range of [0.9, 3.6]. When the value of the fifth voltage is 0.9V, the device under test can be operated in standby mode; when the value of the fifth voltage is 3.6V, the device under test can be operated in full-speed mode.

[0067] In one embodiment, Figure 7 This is a circuit structure diagram of a power interface provided in Embodiment 1 of the present invention. Figure 8 This is a circuit structure diagram of a deception circuit provided in Embodiment 1 of the present invention. Figure 7 and Figure 8 As shown, the deception circuit 71 includes: a first chip U1, a first capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7.

[0068] Specifically, the DP, DM, CC1, and CC2 pins of the power interface are electrically connected to the DP, DM, CC1, and CC2 pins of the first chip U1, respectively. The CC1 and CC2 pins of the first chip U1 are electrically connected to one end of the first resistor R1 and one end of the second resistor R2, respectively; the other ends of the first and second resistors R1 are grounded. The VBUS pin of the first chip U1 is electrically connected to one end of the third resistor R3, and the other end of the third resistor R3 outputs the first voltage Vout1. The CFG1, CFG2, and CFG3 pins of the first chip U1 are electrically connected to one end of the fourth resistor R4, one end of the fifth resistor R5, and one end of the sixth resistor R6, respectively; the other ends of the fourth and sixth resistors R4 and R6 are grounded, and the other end of the fifth resistor R5 is connected to the supply voltage VDD. The VDD pin of the first chip U1 is connected to the power supply voltage VDD and is electrically connected to one end of the seventh resistor R7 and one end of the first capacitor C1. The other end of the seventh resistor R7 outputs the first voltage Vout1, and the other end of the first capacitor C1 and the GND pin of the first chip U1 are grounded.

[0069] Figure 9 This is a circuit structure diagram of a boost circuit provided in Embodiment 1 of the present invention. Figure 9 As shown, the boost circuit 72 includes: a second chip U2, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a first diode D1, and an inductor L.

[0070] Specifically, the VIN pin of the second chip U2, one end of the second capacitor C2, one end of the third capacitor C3, and one end of the inductor L are all connected to the first voltage Vout1; the COMP pin of the second chip U2 is electrically connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is electrically connected to one end of the fourth capacitor C4; the other ends of the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the GND1 pin of the second chip U2 are all grounded. The SWITCH pin of the second chip U2 is electrically connected to the other end of the inductor L and the positive terminal of the first diode D1, and the negative terminal of the first diode D1 outputs the second voltage Vout2; the negative terminal of the first diode D1 is electrically connected to one end of the fifth capacitor C5, one end of the sixth capacitor C6, and one end of the ninth resistor R9, and the other end of the ninth resistor R9 is electrically connected to one end of the tenth resistor R10 and the FEEDBACK pin of the second chip U2; the other ends of the fifth capacitor C5, the sixth capacitor C6, the tenth resistor R10, and the GND2 pin of the second chip U2 are all grounded.

[0071] Optionally, the second chip U2 can be a BOOST power supply chip. The second capacitor C2 and the fifth capacitor C5 can be polarized capacitors, such as electrolytic capacitors.

[0072] Figure 10 This is a circuit structure diagram of a first step-down circuit provided in Embodiment 1 of the present invention. Figure 10 As shown, the first step-down circuit 73 includes: a third chip U3, a seventh capacitor C7, an eighth capacitor C8, and a second diode D2.

[0073] Among them, the VIN pin of the third chip U3 is connected to the first voltage Vout1, and the VOUT1 and VOUT2 pins of the third chip U3 are electrically connected to one end of the seventh capacitor C7, one end of the eighth capacitor C8, and the positive terminal of the second diode D2; the GND pin of the third chip U3, the other end of the seventh capacitor C7, and the other end of the eighth capacitor C8 are all grounded; the negative terminal of the second diode D2 outputs the third voltage Vout3.

[0074] Optionally, the third chip U3 can be a low-dropout regulator (LDO) chip.

[0075] Figure 11 This is a circuit structure diagram of a second step-down circuit provided in Embodiment 1 of the present invention. Figure 11 As shown, the second step-down circuit 74 includes: a fourth chip U4, a ninth capacitor C9, a tenth capacitor C10, an eleventh resistor R11, a third diode D3, and a fourth diode D4.

[0076] Specifically, the VIN pin of the fourth chip U4 is connected to the third voltage Vout3. The VOUT1 and VOUT2 pins of the fourth chip U4 are both electrically connected to one end of the ninth capacitor C9, one end of the tenth capacitor C10, and the positive terminal of the third diode D3. The negative terminal of the third diode D3 is electrically connected to one end of the eleventh resistor R11, and the other end of the eleventh resistor R11 is electrically connected to the positive terminal of the fourth diode D4. The GND pin of the fourth chip U4, the other end of the ninth capacitor C9, the other end of the tenth capacitor C10, and the negative terminal of the fourth diode D4 are all grounded. The negative terminal of the third diode D3 outputs the fourth voltage Vout4.

[0077] Optionally, since the second step-down circuit 74 supplies power to the main control unit 10, the fourth diode D4 can be an LED that emits light, so that the power supply status to the main control unit 10 can be observed in real time. The fourth chip U4 can be an LDO step-down chip.

[0078] Figure 12 This is a circuit structure diagram of a third step-down circuit provided in Embodiment 1 of the present invention. Figure 12 As shown, the third step-down circuit 75 includes: the fifth chip U5, the eleventh capacitor C11, the twelfth capacitor C12, the twelfth resistor R12, and the thirteenth resistor R13.

[0079] Specifically, the VIN and EN pins of the fifth chip U5, and one end of the eleventh capacitor C11 are all connected to the third voltage Vout3. The VOUT pin of the fifth chip U5 is electrically connected to one end of the thirteenth resistor R13 and one end of the twelfth capacitor C12, respectively. The SNS / NC pins of the fifth chip U5 are electrically connected to one end of the twelfth resistor R12 and the other end of the thirteenth resistor R13, respectively. The GND pin of the fifth chip U5, the other end of the eleventh capacitor C11, the other end of the twelfth capacitor C12, and the other end of the twelfth resistor R12 are all grounded. The VOUT pin of the fifth chip U5 outputs the fifth voltage Vout5.

[0080] Optionally, the fifth chip U5 can be an LDO voltage drop chip. The value of the fifth voltage Vout5 output by the third buck circuit 75 can be determined based on the resistance values ​​of the twelfth resistor R12 and the thirteenth resistor R13.

[0081] For example, the value of the fifth voltage Vout5 can be calculated according to the following formula: Vout5=(R12+R13) / R12×0.8.

[0082] Furthermore, the power supply unit 70 may also include a switching circuit and a filtering circuit. Figure 13 This is a circuit structure diagram of a switching circuit provided in Embodiment 1 of the present invention. Figure 14 This is a circuit structure diagram of a filter circuit provided in Embodiment 1 of the present invention. Figure 13 and Figure 14 As shown, the switching circuit includes: switch K, thirteenth capacitor C13 and fourteenth capacitor C14; the filtering circuit includes: fifteenth capacitor C15, sixteenth capacitor C16, seventeenth capacitor C17 and eighteenth capacitor C18.

[0083] The switching circuit and the filtering circuit can protect the power supply unit 70.

[0084] The technical solution of this invention, through the design of a short-circuit protection testing device, includes a main control unit, relays, contactors, and a communication unit. The main control unit controls the opening and closing of the relays according to the test sequence. After the relays are closed, the device under test (DUT) operates under the target condition, and the contactor controls a short circuit in one of the DUT's MOSFETs to achieve short-circuit protection testing. The communication unit queries and sends the current status of the DUT to the main control unit, enabling the main control unit to determine whether a fault has occurred in the DUT based on the current status and terminate the test process when a fault occurs. On one hand, because the main control unit can control the opening and closing of the relays according to the test sequence, and the test stops after the test sequence ends, automatic start and stop of the test can be achieved, avoiding equipment damage caused by repeated short circuits of the MOSFET over a long period, thereby reducing production costs. On the other hand, by querying the current status of the DUT through the newly added communication unit, real-time monitoring of the equipment status can be achieved throughout the entire time period (i.e., before / during the test). Once the main control unit detects a fault in the DUT, it can directly terminate the test process, avoiding invalid testing and improving test efficiency. It also enriches the functions of the main control unit, enabling the short-circuit protection test device to adapt to more efficient and safer testing needs.

[0085] Example 2

[0086] This invention also provides a short-circuit protection testing system, including the short-circuit protection testing device of any of the above embodiments. The short-circuit protection testing system is electrically connected to the device under test.

[0087] In one embodiment, the device under test is the controller of an electric vehicle.

[0088] In one embodiment, the electric vehicle can be an electric two-wheeler or an electric three-wheeler.

[0089] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A short-circuit protection testing device, characterized in that, include: Main control unit, relays, contactors, and communication unit; among which, The main control unit is electrically connected to the relay and the communication unit respectively, and the relay is electrically connected to the contactor; the relay, the contactor, and the communication unit are electrically connected to the device under test respectively. The main control unit is used to control the opening and closing of the relay according to the test sequence; after the relay is closed, the device under test operates under the target operating condition, and the contactor controls a field-effect transistor of the device under test to short-circuit, so as to realize short-circuit protection test; The communication unit is used to query and send the current status of the device under test to the main control unit, so that the main control unit can determine whether the device under test has failed based on the current status, and terminate the test process when the device under test fails.

2. The short-circuit protection testing device according to claim 1, characterized in that, Also includes: Human-computer interaction unit; The human-computer interaction unit is electrically connected to the main control unit and is used to display test information, as well as to acquire and send test parameters input by the user to the main control unit, so that the main control unit can determine the test sequence based on the test parameters.

3. The short-circuit protection testing device according to claim 1, characterized in that, Also includes: Power supply unit; The power supply unit is electrically connected to the main control unit, the relay, and the contactor, respectively, and is used to supply power to the short-circuit protection test device based on the Universal Serial Bus (USB) Power Transfer Protocol (PD).

4. The short-circuit protection testing device according to claim 3, characterized in that, The power supply unit includes: a deception circuit, a boost circuit, a first buck circuit, a second buck circuit, and a third buck circuit; The deception circuit is connected to an external power source through a power interface and is used to deceive the voltage provided by the external power source to the first voltage. The boost circuit is electrically connected to the decoy circuit and is used to boost the first voltage to the second voltage and supply power to the contactor. The first step-down circuit is electrically connected to the decoy circuit and is used to step down the first voltage to the third voltage and to power the relay. The second step-down circuit is electrically connected to the first step-down circuit and is used to step down the third voltage to the fourth voltage and supply power to the main control unit; The third step-down circuit is electrically connected to the first step-down circuit and is used to step down the third voltage to the fifth voltage so that the third step-down circuit can provide auxiliary power to the device under test.

5. The short-circuit protection testing device according to claim 4, characterized in that, The number of the third step-down circuits is at least two, and different third step-down circuits enable the device under test to operate under different conditions. One of the at least two third buck circuits enables the device under test to operate in standby mode, and the other of the at least two third buck circuits enables the device under test to operate in full-speed mode.

6. The short-circuit protection testing device according to claim 4, characterized in that, The deception circuit includes: a first chip, a first capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; Specifically, the DP, DM, CC1, and CC2 pins of the first chip are electrically connected to the power interface; the CC1 and CC2 pins of the first chip are electrically connected to one end of the first resistor and one end of the second resistor, respectively; the other ends of the first and second resistors are both grounded; the VBUS pin of the first chip is electrically connected to one end of the third resistor, and the other end of the third resistor outputs the first voltage; the CFG1, CFG2, and CFG3 pins of the first chip are electrically connected to one end of the fourth, fifth, and sixth resistors, respectively; the other ends of the fourth and sixth resistors are both grounded; the other end of the fifth resistor is connected to the power supply voltage; the VDD pin of the first chip is connected to the power supply voltage and is electrically connected to one end of the seventh resistor and one end of the first capacitor; the other end of the seventh resistor outputs the first voltage; the other end of the first capacitor and the GND pin of the first chip are both grounded. The boost circuit includes: a second chip, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, an eighth resistor, a ninth resistor, a tenth resistor, a first diode, and an inductor; In this configuration, the VIN pin of the second chip, one end of the second capacitor, one end of the third capacitor, and one end of the inductor are all connected to the first voltage; the COMP pin of the second chip is electrically connected to one end of the eighth resistor, and the other end of the eighth resistor is electrically connected to one end of the fourth capacitor; the other ends of the second capacitor, the third capacitor, the fourth capacitor, and the GND1 pin of the second chip are all grounded; the SWITCH pin of the second chip is electrically connected to the other end of the inductor and the positive terminal of the first diode, and the negative terminal of the first diode outputs the second voltage; the negative terminal of the first diode is electrically connected to one end of the fifth capacitor, one end of the sixth capacitor, and one end of the ninth resistor, and the other end of the ninth resistor is electrically connected to one end of the tenth resistor and the FEEDBACK pin of the second chip; the other ends of the fifth capacitor, the sixth capacitor, the tenth resistor, and the GND2 pin of the second chip are all grounded. The first step-down circuit includes: a third chip, a seventh capacitor, an eighth capacitor, and a second diode; The third chip's VIN pin is connected to the first voltage; the third chip's VOUT1 and VOUT2 pins are both electrically connected to one end of the seventh capacitor, one end of the eighth capacitor, and the positive terminal of the second diode; the third chip's GND pin, the other end of the seventh capacitor, and the other end of the eighth capacitor are all grounded; the negative terminal of the second diode outputs the third voltage. The second step-down circuit includes: a fourth chip, a ninth capacitor, a tenth capacitor, an eleventh resistor, a third diode, and a fourth diode; Specifically, the VIN pin of the fourth chip is connected to the third voltage; the VOUT1 and VOUT2 pins of the fourth chip are both electrically connected to one end of the ninth capacitor, one end of the tenth capacitor, and the positive terminal of the third diode; the negative terminal of the third diode is electrically connected to one end of the eleventh resistor, and the other end of the eleventh resistor is electrically connected to the positive terminal of the fourth diode; the GND pin of the fourth chip, the other end of the ninth capacitor, the other end of the tenth capacitor, and the negative terminal of the fourth diode are all grounded; the negative terminal of the third diode outputs the fourth voltage. The third step-down circuit includes: a fifth chip, an eleventh capacitor, a twelfth capacitor, a twelfth resistor, and a thirteenth resistor; Specifically, the VIN and EN pins of the fifth chip and one end of the eleventh capacitor are all connected to the third voltage; the VOUT pin of the fifth chip is electrically connected to one end of the thirteenth resistor and one end of the twelfth capacitor; the SNS / NC pins of the fifth chip are electrically connected to one end of the twelfth resistor and the other end of the thirteenth resistor; the GND pin of the fifth chip, the other end of the eleventh capacitor, the other end of the twelfth capacitor, and the other end of the twelfth resistor are all grounded; and the VOUT pin of the fifth chip outputs the fifth voltage.

7. The short-circuit protection testing device according to claim 1, characterized in that, Also includes: Prompt unit; The prompting unit is electrically connected to the main control unit and is used to send a prompt message after the test is completed.

8. The short-circuit protection testing device according to claim 7, characterized in that, The prompting unit includes: a fourteenth resistor, a fifth diode, a transistor, and a prompting device; One end of the fourteenth resistor is electrically connected to the main control unit, and the other end of the fourteenth resistor is electrically connected to the base of the transistor. The emitter of the transistor is grounded. The collector of the transistor is electrically connected to the anode of the fifth diode and the cathode of the prompting device, respectively. The cathode of the fifth diode and the anode of the prompting device are connected to a third voltage.

9. A short-circuit protection testing system, characterized in that, Includes the short-circuit protection testing device as described in any one of claims 1-8; wherein, The short-circuit protection test system is electrically connected to the device under test.

10. The short-circuit protection test system according to claim 9, characterized in that, The device under test is the controller of an electric vehicle.

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