Radio frequency chip testing device, automatic testing system and testing method

Abstract

The invention discloses a radio frequency chip testing device, an automatic testing system and a testing method, the radio frequency chip testing device comprises a substrate and a testing bonding pad, and a frequency selective impedance unit is connected in series between the bonding pad corresponding to a chip grounding pin and a signal ground. The unit conducts a radio frequency signal to access a signal ground and blocks a direct current signal to realize isolation, so that passive switching of a grounding state is realized by using a physical principle. The device can be compatible with direct current connectivity and radio frequency performance tests, and efficiency loss of substations is avoided. Compared with a traditional scheme, the design does not need additional control signal lines, wiring is simplified, the cost is reduced, and the stability and reliability of the system are remarkably improved.

Description

Technical Field

[0001] This application relates to the field of radio frequency chip testing technology, and in particular to a radio frequency chip testing device, an automated testing system, and a testing method. Background Technology

[0002] In mass production testing of radio frequency (RF) chips, DC testing and RF performance testing are typically required. DC testing mainly includes open / short circuit testing, also known as connectivity testing, which is used to check whether the chip pins are properly soldered or have physical connection faults. RF testing is used to verify the chip's S11 parameters, gain, power, and other performance indicators under high-frequency operating conditions.

[0003] However, the inventors discovered that commonly used testing techniques face a fundamental contradiction in grounding treatment when achieving "RF" and "DC" combined station operation (i.e., completing all tests at the same workstation): like Figure 1 As shown, during DC testing, when performing open-short circuit tests on the grounding pin, the grounding pin under test must be isolated from the common ground or other pins. If the grounding pin is directly connected to the common ground, the DC test current will be shunted through the common ground, making it impossible to determine whether the specific pin is properly soldered.

[0004] like Figure 2 As shown, in RF testing, in order to ensure a smooth return path for RF signals and reduce parasitic inductance, all ground pins of the chip must be connected to the same low-impedance common signal ground.

[0005] Therefore, RF and DC testing need to be carried out in two separate workstations, but this greatly increases testing time and equipment footprint, and reduces production efficiency.

[0006] If the grounding circuit is switched by a relay, the relay, as an active mechanical or electronic switch, is relatively large and difficult to place close to the test pads corresponding to the chip pins. This results in a long signal transmission path from the ground pin to the relay. In the radio frequency band (especially the high frequency band), this long path will introduce a non-negligible parasitic inductance, which will seriously disrupt the return path of the radio frequency signal and cause distortion of the radio frequency performance test results. Summary of the Invention

[0007] The purpose of this application is to provide an RF chip testing device, automated testing system, and testing method that can meet both the common ground requirement for RF testing and the isolation requirement for DC testing, while ensuring testing accuracy.

[0008] To achieve the above-mentioned objectives, one embodiment of this application provides an RF chip testing apparatus, comprising: The substrate body has a signal ground provided on it; Several test pads are disposed on the substrate body for establishing electrical connections with the pins of the chip under test; Among them, a frequency selective impedance unit is connected in series between the test pad corresponding at least partially to the ground pin of the chip under test and the signal ground. The frequency selective impedance unit is configured to: be in a conducting state for radio frequency test signals to connect the ground pin to the signal ground; and be in a blocking state for DC test signals to DC isolate the ground pin from the signal ground.

[0009] As a further improvement of this application, the frequency selective impedance unit is a surface-mount or embedded capacitor unit inside the substrate body.

[0010] As a further improvement of this application, the frequency selective impedance unit is composed of a planar capacitor structure formed between adjacent conductive layers inside the substrate body.

[0011] As a further improvement of this application, the RF chip testing apparatus further includes a DC test circuit; The plurality of test pads includes a grounding pad corresponding to the ground pin of the chip under test; The DC test line is connected to the connection node between the grounding pad and the frequency selective impedance unit to perform open / short circuit tests on the grounding pin while the frequency selective impedance unit isolates the signal ground.

[0012] As a further improvement of this application, the radio frequency chip testing device further includes radio frequency testing circuitry; The plurality of test pads includes signal pads corresponding to the signal pins of the chip under test; The RF test line is connected to the signal pad for transmitting RF test signals. The frequency selective impedance unit and the test pad connected thereto together provide a reference ground return path for the RF test signals.

[0013] As a further improvement of this application, the chip under test includes a signal pin and at least one ground pin disposed adjacent to the signal pin, and at least a portion of the frequency selective impedance unit is disposed between the test pad corresponding to the adjacent ground pin and the signal ground.

[0014] As a further improvement to this application, the frequency selective impedance unit is connected in series between the test pads corresponding to all the grounding pins and the signal ground.

[0015] As a further improvement of this application, the frequency selective impedance unit is disposed on the surface or inner layer of the substrate body and is disposed adjacent to the test pad, so as to reduce the signal transmission path length between the test pad and the frequency selective impedance unit.

[0016] As a further improvement of this application, the substrate body is provided with a test socket mounting position for mounting a test socket; The test pad is located within the test socket mounting position and is configured to contact the probe or spring of the test socket; The frequency selective impedance unit is disposed in the area of ​​the test socket mounting position or adjacent to the edge of the test socket mounting position, and the frequency selective impedance unit is directly connected to the corresponding test pad through the printed circuit of the substrate body, so as to minimize the conductive path length between the probe or spring of the test socket and the frequency selective impedance unit.

[0017] To achieve one of the above-mentioned objectives, one embodiment of this application provides an automated testing system for radio frequency chips, comprising: Radio frequency (RF) test equipment is used to generate and analyze RF test signals. A DC tester is used to generate and analyze DC test signals. The radio frequency chip testing device is electrically connected to the radio frequency tester and the DC tester, respectively. The DC tester is configured to perform a connectivity test on the ground pin of the chip under test through the radio frequency chip testing device. The radio frequency tester is configured to perform radio frequency performance tests on the chip under test when the ground pin is grounded through the frequency selective impedance unit.

[0018] To achieve one of the above-mentioned objectives, one embodiment of this application provides a method for DC and RF co-station testing of an RF chip, which utilizes the aforementioned RF chip testing apparatus and includes the following steps: During the DC testing phase, a DC test signal is applied between the test pad and the frequency selective impedance unit. Based on the frequency selective impedance unit's blocking state in response to the DC test signal, the continuity of the grounding pin is detected. During the radio frequency (RF) testing phase, an RF test signal is applied to the signal pads of the signal pins connected to the chip under test (DUT). Based on the frequency selective impedance unit (FDI) being in a conducting state for the RF test signal, the ground pin is connected to the signal ground through the FDI, forming an RF test signal return path to detect the RF performance of the DUT.

[0019] Compared with commonly used technologies, this application has the following advantages: The RF chip testing device utilizes the physical principle that frequency-selective impedance units present different impedance characteristics to signals of different frequencies, cleverly realizing the "passive switching" of the grounding state, while supporting DC connectivity testing and RF performance testing, avoiding efficiency losses caused by substation testing; and adopts the method of series frequency-selective impedance units, eliminating the need for additional control signal lines to drive the switching action, simplifying the wiring design of the substrate, reducing hardware costs, and improving the stability and reliability of the testing system. Attached Figure Description

[0020] Figure 1 This is a schematic block diagram of a standalone DC test in a commonly used test scheme; Figure 2 This is a schematic block diagram of a standalone RF test in a commonly used test scheme; Figure 3 This is a schematic block diagram of a DC and RF combined station test of an RF chip test apparatus according to an embodiment of this application; Among them, 10 is the chip under test; 11 is the ground pin; 12 is the signal pin; 20 is the substrate body; 21 is the signal ground; 30 is the test pad; 31 is the ground pad; 32 is the signal pad; 40 is the frequency selective impedance unit; 41 is the capacitor unit; 50 is the RF tester; 60 is the DC tester; and 70 is the signal switching unit. Detailed Implementation

[0021] The present application will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present application, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of this application.

[0022] One embodiment of this application provides an RF chip testing device, automated testing system, and testing method that can meet both the common ground requirement for RF testing and the isolation requirement for DC testing, while ensuring testing accuracy.

[0023] The following text is divided into three parts: RF chip testing equipment, RF chip automated testing system, and RF chip DC and RF co-station testing methods.

[0024] Example 1: Radio Frequency Chip Testing Device This embodiment provides an RF chip testing device, which is mainly used to solve the technical problem that the grounding requirements of RF performance testing and DC connectivity testing are contradictory when RF chips are being tested in an automated manner. It enables the completion of RF and DC combined station testing without mechanical switching or changing the test station.

[0025] like Figure 3As shown, the RF chip testing device described in this embodiment includes a substrate body 20 and test pads 30.

[0026] The substrate body 20 serves as the physical carrier of the entire test device. A conductive layer is provided in the inner or bottom layer of the substrate body 20 as a "signal ground 21" to provide a zero potential reference point for the test process.

[0027] The substrate body 20 is usually a multilayer printed circuit board (PCB), but it can also be a ceramic substrate, flexible film (FPC), glass substrate, etc.

[0028] A plurality of conductive test pads 30 are provided on the surface of the substrate body 20. These test pads 30 correspond in spatial arrangement to the pin packages of the chip under test 10. When the chip under test 10 is placed on the test apparatus, its pins (including signal pins 12 and ground pins 11) can establish electrical connections with these test pads 30 through physical contact, such as through probes or direct contact, thereby introducing the signals of the chip under test 10 into the test apparatus.

[0029] The core improvement in this embodiment lies in the handling of the ground pin 11 of the chip under test 10. In common techniques, for testing the ground pin 11 of the chip under test 10, the pad is usually directly connected to the signal ground 21 through a via.

[0030] In this embodiment, the test pad 30, which corresponds at least partially to the ground pin 11 of the chip under test 10, is not directly connected to the signal ground 21 of the substrate body 20, but is connected in series with a "frequency selective impedance unit 40".

[0031] Specifically, a frequency selective impedance unit 40 is connected in series between the test pad 30, which at least partially corresponds to the ground pin 11 of the chip under test 10, and the signal ground 21. The frequency selective impedance unit 40 is configured to: be in a conducting state for radio frequency test signals to connect the ground pin 11 to the signal ground 21; and be in a blocking state for DC test signals to DC isolate the ground pin 11 from the signal ground 21.

[0032] Thus, the current flowing from the ground pin 11 of the chip under test 10 must first flow through the frequency selective impedance unit 40 before reaching the common signal ground 21. The frequency selective impedance unit 40 constitutes a "passive frequency valve" connected in series in the grounding loop.

[0033] The frequency-selective impedance unit 40 is configured as a passive device or circuit network that is sensitive to the signal frequency. Its impedance value changes significantly with the frequency of the signal passing through it, thereby using the frequency characteristics of the signal being measured to automatically switch between "conduction" and "isolation" states.

[0034] When receiving DC test signals, i.e., during the DC test phase: When the tester applies a DC test signal to the chip under test 10, such as a weak DC current used for open / short circuit testing, the frequency of this signal is zero or extremely low. At this frequency, the frequency-selective impedance unit 40 exhibits a high-impedance blocking state. Here, "high impedance" means that its impedance value is extremely high, approximating an open circuit.

[0035] Due to its extremely high impedance, the ground pin 11 of the chip under test 10 is effectively isolated from the signal ground 21 of the substrate on the DC plane. In this case, the DC tester can apply a signal to the ground pin 11 to detect its continuity with the other grounded pins. If the test result shows continuity, it indicates that the ground pin 11 is well soldered inside the chip, and the internal connections are complete; if the test result shows no continuity, it indicates that the internal connection of the ground pin 11 is broken. This isolation ensures that the DC test can accurately reflect the internal connection status of the chip, avoiding false positives caused by direct grounding of the ground pin 11.

[0036] When receiving RF test signals, i.e., during the RF test phase: When the tester transmits an radio frequency (RF) test signal to the chip under test 10, the signal frequency is within the operating frequency band. The RF test signal is typically a high-frequency AC signal in the MHz to GHz range. At this frequency, the frequency-selective impedance unit 40 exhibits a low-impedance conduction state. Here, "low impedance" means that its impedance value is extremely small, approximating a short circuit.

[0037] For high-frequency radio frequency (RF) signals, the frequency-selective impedance unit 40 acts as a conductor, allowing the ground pin 11 of the chip under test (DUT) 10 to be smoothly connected to the signal ground 21 through the frequency-selective impedance unit 40, thus providing a low-impedance, stable reference ground return path for the RF signal. Good grounding is crucial for maintaining the characteristic impedance of the transmission line, reducing signal reflection, and minimizing return loss. In this state, the RF chip test equipment can accurately evaluate the RF performance indicators of the DUT 10, such as power, gain, and S11 parameters.

[0038] This embodiment cleverly utilizes the significant difference in frequency domain between "DC signal" and "RF signal" by connecting a frequency-selective impedance unit 40 in series in the grounding path of the grounding pin 11 of the chip under test 10. The grounding and isolation of the grounding pin 11 can achieve intelligent passive switching of "disconnecting ground when testing DC and connecting ground when testing RF" without any external control signal. This not only simplifies the wiring design of the test board and reduces hardware costs, but more importantly, it eliminates the problems of large size and high parasitic parameters caused by traditional mechanical relays, such as ground bounce and crosstalk caused by excessive grounding distance of the grounding pin 11 during RF testing. This significantly improves the integration of the test system and the high-frequency test accuracy.

[0039] In one embodiment, the frequency-selective impedance unit 40 is a capacitor unit 41.

[0040] The capacitor unit 41 can be one or more discrete surface-mount capacitors, and the capacitor unit 41 is usually a multilayer ceramic capacitor. The capacitor with a specific capacitance value and package size can be selected according to the operating frequency band of the chip under test 10 (e.g., Sub6G, millimeter wave, etc.).

[0041] When selecting capacitors, smaller package sizes are preferred for the capacitor unit 41. This is because the smaller the capacitor, the closer it can be physically placed against the test pad corresponding to the ground pin 11 on the substrate body 20, thereby minimizing the physical distance from the test pad to the signal ground 21. Specifically, capacitors with 0201 packages (0.6mm × 0.3mm), 01005 packages (0.3mm × 0.15mm), or smaller packages can be used. This miniaturized design helps reduce parasitic inductance introduced by the leads, ensuring that multiple ground pins 11 can be connected to the same signal ground 21 at a very close distance.

[0042] Regarding frequency characteristics, according to the capacitive reactance formula XC=1 / 2πfC, for an ideal capacitor, its impedance (capacitive reactance) decreases as the frequency increases. However, in practical engineering, due to parasitic effects, a capacitor has a self-resonant frequency at which its impedance reaches its minimum value. When the operating frequency exceeds the self-resonant frequency, the capacitor will exhibit inductive characteristics, and its impedance will actually increase.

[0043] Therefore, in this embodiment, when selecting a capacitor, the highest radio frequency test frequency of the chip under test 10 does not exceed the self-resonant frequency of the capacitor unit 41 by too much, so as to ensure that the capacitor unit 41 always maintains a low impedance state throughout the entire test frequency band, and avoids affecting the grounding effect due to high inductive reactance.

[0044] As a specific quantitative selection criterion, the suitability of a capacitor can be determined by examining its S-parameters (scattering parameters). In this embodiment, it is required that the selected capacitor unit 41 preferably maintains a return loss S11 below -20dB throughout the entire operating frequency band of the chip 10 under test.

[0045] In contrast, when using relays for ground switching, it is difficult to ensure that S11 is below -15dB over a wide frequency range due to limitations in the internal structure and contacts of the relays. However, the capacitor unit 41 scheme used in this embodiment can easily achieve the performance target of S11 < -20dB across the entire frequency band, with minimal reflection of RF signals from the grounding path, and its matching performance is significantly better than that of the relay-based ground switching scheme.

[0046] This embodiment utilizes the inherent physical characteristic of capacitors to "pass AC and block DC": DC isolation: For DC test signals, the capacitor acts as an open circuit, with extremely high insulation resistance. Therefore, when the DC tester 60 performs a continuity test on the ground pin 11, the test current will not leak into the signal ground 21, ensuring the accuracy of the test.

[0047] RF conduction: For high-frequency RF signals, the capacitor acts as a low-impedance path, and the RF return signal of the ground pin 11 of the chip under test can pass through the capacitor and enter the main ground layer with almost no loss.

[0048] Using capacitors as impedance units is a more economical and mature solution for achieving the goals of this application. Surface mount capacitors are inexpensive, have a mature supply chain, standardized mounting processes, and excellent high-frequency response characteristics, enabling high-performance co-station testing at extremely low cost.

[0049] In addition to being mounted on the surface of the substrate 20, the capacitor unit 41 can also be implemented using PCB embedded component technology. That is, the capacitor unit 41 is a discrete capacitor component (such as a ceramic capacitor or a film capacitor), which is directly embedded inside the dielectric layer of the substrate 20. This method of embedding discrete capacitors also has the advantages of not occupying substrate surface space and shortening signal paths.

[0050] In one embodiment, the frequency-selective impedance unit 40 is composed of a planar capacitor structure formed between adjacent conductive layers inside the substrate body 20.

[0051] The substrate body 20 typically comprises multiple conductive copper layers. In this embodiment, a very thin insulating dielectric material is sandwiched between a conductive layer connected to the test pad 30, such as the top layer or a specific signal layer, and the adjacent signal ground layer 21. Thus, the metal region extending downwards from the test pad 30 acts as one electrode, the adjacent internal ground layer acts as another electrode, and the intermediate PCB dielectric acts as the dielectric, thereby forming a distributed planar capacitor.

[0052] By controlling the overlap area between the two conductive layers, as well as the thickness and dielectric constant of the dielectric layer, the capacitance value of this planar structure can be precisely designed to meet the requirements for radio frequency conduction.

[0053] Compared to surface-mount capacitors, planar capacitors do not require pads and solder, eliminating the parasitic resistance and inductance introduced by solder joints. In extremely high-frequency tests (such as millimeter-wave bands), this structure exhibits flat transmission characteristics and superior high-frequency performance.

[0054] Furthermore, since the capacitors are "buried" inside the substrate, there is no need to occupy additional patch space on the substrate surface, making it suitable for testing the 10 high-density pins of the chip under test, simplifying the wiring difficulty and allowing for a more compact probe layout.

[0055] In addition to the embodiments described above, the frequency-selective impedance unit 40 can also be a combination of multiple capacitors in parallel, such as at least two capacitors with different capacitance values ​​connected in parallel, or an LC series resonant network. The impedance unit can be composed of an inductor (L) and a capacitor (C) connected in series. The frequency-selective impedance unit 40 described below uses a capacitor as an example.

[0056] In one embodiment, the frequency selective impedance unit 40 is disposed on the surface or inner layer of the substrate body 20 and is disposed adjacent to the test pad 30 to reduce the signal transmission path length between the test pad 30 and the frequency selective impedance unit 40.

[0057] The capacitor is soldered directly onto the lead line adjacent to the test pad 30, requiring no vias or only very short traces.

[0058] For high-density BGA packages, when space is limited, test pad 30 can be extended to the back side through a via, and the capacitor is placed close to the back pad of this via.

[0059] In this embodiment, "close to" means placing the impedance unit as close as possible to the test pad 30 within the minimum spacing allowed by the layout and wiring design rules of the substrate body 20.

[0060] In this embodiment, the "signal transmission path length" refers to the physical distance from the center point of the test pad 30, along the conductive copper foil, through the capacitor pad, to the center of the via leading to the main ground layer.

[0061] Since a conductor is equivalent to an inductor at high frequencies, and its inductance is proportional to its length, placing the capacitor "closely" to it essentially cuts off the long conductor between the grounding pin 11 and "ground", reducing the inductance of the trace.

[0062] In addition, in the radio frequency band, PCB traces are no longer considered ideal conductors, but have distributed parameter effects. Their parasitic inductance is proportional to the trace length. If a device with a large physical size, such as a relay, is used to switch the ground pin 11, it cannot be placed close to the test pad corresponding to the ground pin 11 of the chip under test 10. This results in an excessively long conductive path from the test pad to the signal ground 21. The connection between several ground pins 11 and the corresponding signal ground 21 usually needs to be several centimeters apart.

[0063] At higher frequencies (e.g., above 2GHz), the parasitic inductance introduced by long conductors over long distances can significantly increase the impedance of the grounding loop. This prevents grounding pin 11 from obtaining a stable zero-potential reference and disrupts the low-impedance return path of the RF signal, ultimately leading to severe attenuation and reflection of the high-frequency test signal, which cannot meet the accuracy requirements of high-frequency (e.g., 2GHz-8GHz, or even higher) chip testing.

[0064] The close proximity design of this embodiment eliminates this hidden danger. The signal transmission path length from the center of the test pad 30 through the capacitor unit 41 to the center of the grounding via can be less than or equal to 3 mm. The extremely short path corresponds to extremely low parasitic inductance, and the RF return path is extremely smooth, ensuring the test accuracy at 8 GHz or even higher frequencies.

[0065] In one embodiment, the substrate body 20 is provided with a test socket mounting position for mounting a test socket, the test socket mounting position being filled with test pads 30 that contact the probes or springs of the test socket.

[0066] The frequency selective impedance unit 40 is disposed in the area of ​​the test socket mounting position or adjacent to the edge of the test socket mounting position, and the frequency selective impedance unit 40 is directly connected to the corresponding test pad 30 through the printed circuit of the substrate body 20, so as to minimize the conductive path length between the probe or spring of the test socket and the frequency selective impedance unit 40.

[0067] If the test socket structure allows, for example, if the test socket has a cutout at the bottom, the impedance unit can be placed directly inside the projection area of ​​the test socket mounting position, in the gap between the two probe pads.

[0068] If there is insufficient space at the bottom of the test socket, the impedance unit should be placed close to the outer edge of the test socket.

[0069] The test pad 30 is directly connected to the impedance unit through the printed circuit on the substrate, that is, the connection does not pass through any unnecessary vias or windings, and is connected by the shortest path.

[0070] By placing the frequency-selective impedance unit 40 below the test socket or close to the edge, the physical distance from the probe contact point to the capacitor is compressed to the extreme, for example, controlled within 3 mm in engineering. This allows the RF signal to find a discharge path almost instantly after flowing out from the signal pin 12, maximizing the restoration of the grounding performance of the chip under test 10 on the actual application circuit board, thus making the test results highly reliable.

[0071] The close proximity arrangement of the frequency selective impedance unit 40 and the test pad 30, the close proximity arrangement of the frequency selective impedance unit 40 and the test socket, and the miniaturization of the capacitor structure all enable this application to achieve the closest possible arrangement, significantly shortening the grounding path, thereby reducing parasitic inductance, improving high-frequency test accuracy, and ultimately ensuring test accuracy at 8GHz or even higher frequencies.

[0072] Furthermore, current chip pins are extremely dense, making it impossible to install relays. This results in only being able to test the more important ground pin 11, while other ground pins 11 must either be abandoned for DC testing or left floating. However, the structure of this application can achieve full coverage, allowing each ground pin 11 of the chip under test 10 to simultaneously handle both RF and DC testing.

[0073] In one embodiment, the chip under test 10 includes a signal pin 12 and at least one ground pin 11 adjacent to the signal pin 12, and at least a portion of the frequency selective impedance unit 40 is disposed between the test pad 30 corresponding to the adjacent ground pin 11 and the signal ground 21.

[0074] This embodiment has made specific optimization configurations for the adjacent structures of "signal ground 21" in the chip under test 10 that have the most stringent performance requirements, such as GSG, GS or SG.

[0075] In the packaging design of high-performance RF chips, in order to control the characteristic impedance and provide the shortest return path, signal pin 12 is usually adjacent to one or more ground pins 11.

[0076] In this embodiment, the frequency selective impedance unit 40 is preferentially configured on the test path of the ground pin 11, which is adjacent to the physical location of these radio frequency signal pins 12.

[0077] Taking the GSG pin arrangement of one RF port of the chip under test 10 as an example, that is, the arrangement of ground pin a-signal pin-ground pin b, the signal pad 32 corresponding to the signal pin 12 on the substrate body 20 is directly connected to the RF tester 50; while the adjacent "ground pin a" and "ground pin b" are connected in series with their own independent frequency selective impedance units 40, and then connected to the signal ground 21.

[0078] According to high-frequency electromagnetic field theory, the return current of radio frequency signals always tends to flow along the path of least impedance, that is, the reference ground path that is spatially adjacent to the signal conductor. By connecting a low-impedance conducting impedance unit in series on the ground pin 11, which is adjacent to the signal pin 12, a return bridge closest to the signal line is constructed.

[0079] At the same time, this layout ensures that the return current does not need to detour through other grounding pins 11 at a distance, thereby minimizing the loop area of ​​the return path, significantly reducing parasitic inductance, effectively suppressing radiated interference of RF signals and crosstalk between adjacent signal lines, greatly improving return loss and insertion loss, and ensuring the accuracy of high-frequency test data.

[0080] In one embodiment, the frequency selective impedance unit 40 is connected in series between the test pads 30 corresponding to all the ground pins 11 and the signal ground 21.

[0081] In this embodiment, not only the ground pin 11 near the RF port, but all the ground pins 11 of the chip under test 10, including digital ground, analog ground, RF ground, etc., are connected in series with a frequency selective impedance unit 40 between each test pad 30 and the substrate signal ground 21.

[0082] If the chip under test 10 is a ball grid array (BGA) or LGA package, there may be dozens or even hundreds of ground pins 11 on the bottom. In this embodiment, an independent frequency selective impedance unit 40 is configured for each ground pad 31 on the substrate body 20, such as forming an array of capacitor units 41, to achieve 100% open and short circuit test coverage.

[0083] In traditional solutions, all ground pins 11 are typically shorted to ground directly for RF performance reasons, making it impossible to detect whether individual ground pins 11 are properly soldered. In solutions using relays to switch ground lines, the relatively bulky relays simply cannot meet the testing requirements of a large number of ground pins 11.

[0084] In this embodiment, since each grounding pin 11 is connected in series with an impedance unit, they are "isolated" and "floating" from DC perspective. Therefore, the DC tester 60 can independently perform continuity tests on each grounding pin 11. If a grounding pin 11 is poorly soldered, the DC tester 60 can immediately detect the open circuit signal, thereby intercepting defective products and greatly improving test coverage and product shipment quality.

[0085] In RF test mode, all capacitor units 41 are turned on simultaneously, and dozens or even hundreds of ground pins 11 are grounded simultaneously through capacitors, further improving power integrity and signal integrity.

[0086] In one embodiment, the RF chip testing apparatus further includes a DC test circuit for implementing DC testing functions, particularly for open / short circuit testing of the ground pin 11.

[0087] The plurality of test pads 30 include a ground pad 31 corresponding to the ground pin 11 of the chip under test 10; one end of the DC test line is connected to the connection node between the ground pad 31 and the frequency selective impedance unit 40, and the other end is connected to the DC tester 60 (or the DC resource board of the tester) so as to perform open and short circuit tests on the ground pin 11 while the frequency selective impedance unit 40 isolates the signal ground 21.

[0088] In circuit topology, the connection node for DC testing is located "upstream" of the capacitor, i.e., close to the side of the chip under test, rather than "downstream" of the capacitor, i.e., close to the ground side.

[0089] In one embodiment, the RF chip testing apparatus further includes RF test lines for connecting signal pads 32 to an RF tester 50, such as a network analyzer or a comprehensive tester. The RF test lines are typically designed with a specific characteristic impedance (e.g., 50 ohms) to achieve impedance matching.

[0090] The plurality of test pads 30 include signal pads 32 corresponding to the signal pins 12 of the chip under test 10, which are specifically used to contact the radio frequency signal pins 12 of the chip under test 10.

[0091] The RF test line is connected to the signal pad 32 for transmitting RF test signals. The frequency-selective impedance unit 40 and the test pad 30 connected to it together provide a reference ground return path for the RF test signals. The RF test signals are transmitted bidirectionally between the RF tester 50 and the signal pin 12 via the RF test line.

[0092] Although this application cleverly solves the multiplexing problem of ground pin 11 through passive frequency selective impedance unit 40, for signal pin 12 carrying the core test signal, in order to time-division multiplex the resources of DC tester 60 and RF tester 50, this embodiment introduces an active switching structure.

[0093] like Figure 3 As shown, the RF chip testing device also includes a signal switching unit 70. The common terminal of the signal switching unit 70 is connected to the signal pad 32, thereby connecting with the signal pin 12 of the chip under test 10. The first branch terminal (RF terminal) of the signal switching unit 70 is used to connect to the RF test line, and the second branch terminal (DC terminal) is used to connect to the DC test line.

[0094] The signal switching unit 70 is configured to: connect the signal pad 32 to the RF test line during RF testing; and connect the signal pad 32 to the DC test line during DC testing.

[0095] In one embodiment, the signal switching unit 70 is a single-pole double-throw relay or a high-frequency MEMS switch with equivalent functionality.

[0096] The operation of the signal switching unit 70 is driven by a control signal from the testing machine and is strictly synchronized with the test program flow. When performing DC testing, the DC tester 60 applies a test signal, such as DC current, to the connection node of the DC test. Because the frequency selective impedance unit 40 presents high impedance to DC (i.e., DC blocking characteristic), the current cannot flow directly into the signal ground 21.

[0097] At this point, the only path for the current is to flow to the test pad 31 and then through the probe into the ground pin 11 of the chip under test 10. The DC tester 60 simultaneously configures the other ground pins of the chip as loop terminals to detect the continuity (or short circuit) between the ground pin 11 and the chip's internal common ground network.

[0098] If the DC tester 60 detects continuity, it indicates that the grounding pin is well soldered; if the tester detects an open circuit, it can accurately determine that the specific grounding pin 11 has poor soldering or poor probe contact, perfectly solving the problem that the grounding pin 11 cannot be tested for open circuit once it is grounded.

[0099] Additionally, the signal switching unit 70 activates, connecting its common terminal to the second branch terminal (DC terminal) while simultaneously disconnecting it from the first branch terminal (RF terminal). The test signal emitted by the DC tester 60 travels through the DC test circuit, signal switching unit 70, and signal test pad 30, ultimately reaching the signal pin 12 of the chip. The RF chip automated test system can perform DC parameter tests on the signal pin 12, such as open / short circuit and leakage current tests. Although the capacitor on the adjacent ground pin 11 blocks DC at this time, the DC path of the signal pin 12 itself is complete, meeting the test requirements.

[0100] When the RF test signal is transmitted at signal pin 12, the signal switching unit 70 switches, making its common terminal connected to the first branch terminal (RF terminal), while simultaneously disconnecting from the DC tester 60. The high-frequency excitation signal emitted by the RF tester 50 enters the chip via the RF test line, signal switching unit 70, and signal test pad 30. The RF signal output by the chip under test 10 returns to the RF tester 50 along the reverse path. In addition, the return current flows out through the adjacent ground pin 11, passes through the ground pad 31, and is quickly discharged into the signal ground layer 21 of the substrate using the low impedance conduction characteristics of the impedance unit. This structure ensures the shortest return path and the smallest loop area for the RF signal, effectively reduces the parasitic inductance on the ground path, ensures the impedance continuity of the RF transmission line, thereby significantly reducing signal reflection, improving return loss (S11) and insertion loss (S21), and ensuring the authenticity and accuracy of the chip RF performance test.

[0101] By introducing the signal switching unit 70, the RF chip testing device can ensure that the same signal pin 12 of the chip under test 10 can be connected to different types of test resources in a physical manner. With the help of the capacitor isolation structure on the grounding path, the "one-stop" automated testing process of the RF chip is fully realized.

[0102] The combination of active switching of the signal pin and passive adaptive switching of the grounding pin ensures the signal integrity of signal pin 12 in both modes, while avoiding the parasitic inductance problem caused by using a relay in the grounding circuit, thus achieving the best balance between test accuracy and system complexity.

[0103] Example 2: Automated Testing System for Radio Frequency Chips One embodiment of this application provides an automated testing system for radio frequency chips, such as... Figure 3 As shown, it includes an RF tester 50, a DC tester 60, and the aforementioned RF chip test apparatus.

[0104] The RF tester 50 is equipped with an RF signal generator and an analyzer to generate high-frequency RF test signals and receive feedback signals from the chip in order to analyze parameters such as S-parameters and noise figure.

[0105] The DC tester 60 is equipped with a precision measurement unit or digital channel to provide DC voltage / current, generate DC test signals, and perform parameter measurements such as open / short circuit tests and leakage current tests.

[0106] The RF chip test device serves as the physical and electrical interface between the chip under test 10 and the RF tester 50 and the DC tester 60. The RF tester 50 is connected to the signal pad 32 via an RF connector on the test device; the probe card or cable of the DC tester 60 is connected to the DC test node on the RF chip test device via a ribbon cable.

[0107] The DC tester 60 is configured to perform a connectivity test on the ground pin 11 of the chip under test 10 through the RF chip test device; the RF tester 50 is configured to perform an RF performance test on the chip under test 10 when the ground pin 11 is grounded through the frequency selective impedance unit 40.

[0108] In DC testing tasks, the DC tester 60 is configured to send DC current to the test device. Since the frequency-selective impedance unit 40 on the test device naturally blocks DC, this physical isolation characteristic is used to accurately determine the continuity of the chip's ground pin 11, simplifying the development of the test program.

[0109] In RF testing tasks, the RF tester 50 is configured to send high-frequency signals to the chip. At this time, the impedance unit on the test device automatically presents a low impedance state, shorting the ground pin 11 to the system ground, thereby obtaining a low-noise, low-inductance RF test environment, ensuring that the RF parameters read by the tester truly reflect the chip performance.

[0110] This automated RF chip testing system enables a single device, a single pin insertion, and no hardware switching required to complete the entire testing process. Compared to traditional dual-station systems, it significantly reduces the number of times the robotic arm handles the chip and the contact wear, thereby substantially improving the throughput and overall economic benefits of mass production testing.

[0111] Example 3: DC and RF co-station test method for RF chips One embodiment of this application provides a method for testing DC and RF combined stations, which utilizes the aforementioned RF chip testing apparatus and includes the following steps: During the DC test phase, a DC test signal is applied between the test pad 30 and the frequency selective impedance unit 40. Based on the fact that the frequency selective impedance unit 40 presents a blocking state for the DC test signal, the continuity of the grounding pin 11 is detected.

[0112] During the radio frequency (RF) testing phase, an RF test signal is applied to the signal pad 32 of the signal pin 12 connected to the chip under test 10. Based on the frequency selective impedance unit 40 being in a conducting state for the RF test signal, the ground pin 11 is connected to the signal ground 21 through the frequency selective impedance unit 40, forming an RF test signal return path to detect the RF performance of the chip under test 10.

[0113] For the specific principles and details of this DC and RF combined station test method, please refer to the details disclosed in the RF chip test device and RF chip automated test system above.

[0114] This method for combined DC and RF testing uses the signal frequency as an invisible switch to seamlessly connect DC and RF testing. It avoids the cumbersome mechanical switching required for ground isolation in traditional methods, ensuring both the "isolation" requirement of DC testing and the "common ground" requirement of RF testing, thus achieving a dual improvement in testing efficiency and coverage.

[0115] Compared with commonly used technologies, this embodiment has the following advantages: This RF chip testing device cleverly achieves "passive switching" of grounding state by utilizing the physical principle that the frequency selective impedance unit 40 presents different impedance characteristics to signals of different frequencies. It also supports DC connectivity testing and RF performance testing, avoiding efficiency losses caused by substation testing. Furthermore, by using the series frequency selective impedance unit 40, no additional control signal lines are needed to drive the switching action, simplifying the wiring design of the substrate body 20, reducing hardware costs, and improving the stability and reliability of the testing system.

[0116] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0117] The detailed descriptions listed above are merely specific descriptions of feasible implementation methods of this application, and are not intended to limit the scope of protection of this application. All equivalent implementation methods or modifications made without departing from the specific spirit of this application should be included within the scope of protection of this application.

Claims

1. A radio frequency chip testing device, characterized in that, include: The substrate body has a signal ground provided on it; Several test pads are disposed on the substrate body for establishing electrical connections with the pins of the chip under test; Among them, a frequency selective impedance unit is connected in series between the test pad corresponding at least partially to the ground pin of the chip under test and the signal ground. The frequency selective impedance unit is configured to: be in a conducting state for radio frequency test signals to connect the ground pin to the signal ground; and be in a blocking state for DC test signals to DC isolate the ground pin from the signal ground.

2. The RF chip testing apparatus according to claim 1, characterized in that, The frequency-selective impedance unit is a surface-mount or embedded capacitor unit inside the substrate body, or it is composed of a planar capacitor structure formed between adjacent conductive layers inside the substrate body.

3. The radio frequency chip testing apparatus according to claim 1 or 2, characterized in that, The frequency selective impedance unit is disposed on the surface or inner layer of the substrate body and is disposed adjacent to the test pad to reduce the signal transmission path length between the test pad and the frequency selective impedance unit.

4. The radio frequency chip testing apparatus according to claim 1 or 2, characterized in that, The substrate body is provided with a test socket mounting position for mounting a test socket; The test pad is located within the test socket mounting position and is configured to contact the probe or spring of the test socket; The frequency selective impedance unit is disposed in the area of ​​the test socket mounting position or adjacent to the edge of the test socket mounting position, and the frequency selective impedance unit is directly connected to the corresponding test pad through the printed circuit of the substrate body, so as to minimize the conductive path length between the probe or spring of the test socket and the frequency selective impedance unit.

5. The radio frequency chip testing apparatus according to claim 1, characterized in that, The chip under test includes a signal pin and at least one ground pin adjacent to the signal pin. At least a portion of the frequency selective impedance unit is disposed between the test pad corresponding to the adjacent ground pin and the signal ground.

6. The radio frequency chip testing apparatus according to claim 1, characterized in that, The frequency-selective impedance unit is connected in series between the test pads corresponding to all the grounding pins and the signal ground.

7. The radio frequency chip testing apparatus according to claim 1, characterized in that, The RF chip testing device also includes a DC testing circuit; The plurality of test pads includes a grounding pad corresponding to the ground pin of the chip under test; The DC test line is connected to the connection node between the grounding pad and the frequency selective impedance unit to perform open / short circuit tests on the grounding pin while the frequency selective impedance unit isolates the signal ground.

8. The radio frequency chip testing apparatus according to claim 7, characterized in that, The radio frequency chip testing device also includes radio frequency testing circuitry. The plurality of test pads includes signal pads corresponding to the signal pins of the chip under test; The RF test line is connected to the signal pad for transmitting RF test signals. The frequency selective impedance unit and the test pad connected thereto together provide a reference ground return path for the RF test signals.

9. The radio frequency chip testing apparatus according to claim 8, characterized in that, The RF chip testing device also includes a signal switching unit. The common terminal of the signal switching unit is connected to the signal pad. The first branch terminal of the signal switching unit is used to connect to the RF test line, and the second branch terminal is used to connect to the DC test line. The signal switching unit is configured to: connect the signal pad to the RF test line during RF testing; and connect the signal pad to the DC test line during DC testing.

10. An automated testing system for radio frequency chips, characterized in that, include: Radio frequency (RF) test equipment is used to generate and analyze RF test signals. A DC tester is used to generate and analyze DC test signals. And the RF chip testing apparatus as described in any one of claims 1 to 9, wherein the RF chip testing apparatus is electrically connected to the RF tester and the DC tester respectively, wherein the DC tester is configured to perform a connectivity test on the ground pin of the chip under test through the RF chip testing apparatus; and the RF tester is configured to perform an RF performance test on the chip under test when the ground pin is grounded through the frequency selective impedance unit.

11. A method for DC and RF co-station testing of an RF chip, wherein the testing is performed using the RF chip testing apparatus as described in any one of claims 1 to 9, characterized in that, Includes the following steps: During the DC testing phase, a DC test signal is applied between the test pad and the frequency selective impedance unit. Based on the frequency selective impedance unit's blocking state in response to the DC test signal, the continuity of the grounding pin is detected. During the radio frequency (RF) testing phase, an RF test signal is applied to the signal pads of the signal pins connected to the chip under test (DUT). Based on the frequency selective impedance unit (FDI) being in a conducting state for the RF test signal, the ground pin is connected to the signal ground through the FDI, forming an RF test signal return path to detect the RF performance of the DUT.

Images