Wafer alignment deviation compensation method and semiconductor manufacturing equipment
By dividing the wafer into multiple radius partitions and obtaining and feeding back overlay accuracy compensation values, the problem of inconsistent overlay accuracy between the wafer center and edge is solved, thereby improving overlay accuracy and manufacturing yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-17
- Publication Date
- 2026-04-03
AI Technical Summary
In existing technologies, the overlay accuracy compensation values between the wafer center and the edge are inconsistent, resulting in overlay accuracy errors that affect device performance and yield.
The wafer is divided into multiple radius-based partitions, and the overlay accuracy measurement value of each partition is obtained. The overlay accuracy compensation value is then fed back to the lithography machine for differential compensation through an advanced process control system.
It achieves precise differential compensation for wafer overlay accuracy, improving manufacturing yield, especially suitable for scenarios where the behavior of the central and edge regions is inconsistent in advanced processes.
Smart Images
Figure CN121785066A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a method for compensating wafer alignment deviations and semiconductor manufacturing equipment. Background Technology
[0002] As semiconductor manufacturing nodes continue to shrink to less than 28nm and even more advanced levels, the requirements for overlay accuracy on wafers are becoming increasingly stringent. Traditional overlay accuracy compensation methods typically treat the entire wafer as a homogeneous region, using a unified mathematical model (such as a 10-parameter model or a higher-order polynomial model) to calculate compensation values, which are then fed back to the lithography machine through an advanced process control (APC) system. However, in actual production, due to factors such as the non-uniformity of the preceding process, machine thermal effects, and differences in stress distribution, the overlay error fingerprint (OVL fingerprint) of the wafer center and the far edge often exhibits significant differences, or even completely opposite behaviors.
[0003] Traditional overlay accuracy compensation involves collecting data from the entire wafer and calculating the compensation values for various parameters using a model. The advanced process control (APC) system then feeds these parameters back to the lithography machine. This model treats the entire wafer as a single region, and this calculation model may not reflect actual production conditions, leading to incomplete compensation and severely impacting device performance and yield.
[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a wafer alignment deviation compensation method and semiconductor manufacturing equipment to solve the problem of inconsistent overlay accuracy compensation values required between the wafer center and edge in advanced processes in the prior art.
[0006] To achieve the above and other related objectives, the present invention provides a method for compensating wafer alignment deviations. The method includes: dividing the wafer into at least two radius-based partition regions; obtaining the overlay accuracy measurement value of each partition region, and calculating the overlay accuracy compensation value of each partition region based on the overlay accuracy measurement value; feeding back the overlay accuracy compensation value of each partition region to the lithography machine through an advanced process control system; and exposing the wafer after the lithography machine performs overlay accuracy compensation on each partition region based on the overlay accuracy compensation value.
[0007] Optionally, radius-based partitioning includes dividing the wafer into a central circle based on the wafer radius and at least one annulus extending sequentially from the central circle toward the outer edge of the wafer, wherein the annulus and the central circle are concentric.
[0008] Optionally, the number of rings can be 2 to 5.
[0009] Optionally, obtaining the overlay accuracy measurement value for each partition region includes: setting one or more detection points in each partition region, and obtaining the actual overlay accuracy measurement value for each partition region based on the overlay accuracy measurement of one or more detection points.
[0010] Optionally, the method for compensating for overlay accuracy in each partition region includes translating, rotating, and / or scaling each partition region corresponding to the current exposure layer.
[0011] Optionally, the method further includes the step of: performing overlay accuracy detection on the exposed wafer, and further adjusting the overlay accuracy compensation value of the corresponding partition area based on the overlay accuracy detection result.
[0012] Optionally, the overlay accuracy compensation value for each zone can be calculated using an overlay accuracy compensation model.
[0013] Optionally, each zone may use the same overlay accuracy compensation model or different overlay accuracy compensation models.
[0014] Optionally, the overlay accuracy compensation model includes a 10-parameter overlay accuracy compensation model or a high-order polynomial overlay accuracy compensation model.
[0015] The present invention also provides a semiconductor manufacturing apparatus, comprising: a lithography machine; an overlay accuracy measuring device; and an advanced process control system for performing a wafer alignment deviation compensation method for any of the above schemes.
[0016] As described above, the wafer alignment deviation compensation method and semiconductor manufacturing equipment of the present invention have the following beneficial effects:
[0017] This invention achieves individual compensation for the overlay accuracy of different regions by dividing the wafer into radius regions and calculating the compensation value based on the overlay accuracy measurement value of each region. Compared with the traditional method of treating the entire wafer as a single region for overlay accuracy compensation, this invention achieves precise and differentiated compensation for wafer overlay accuracy. It is particularly suitable for scenarios where the behavior of the wafer center region and the edge region is inconsistent in advanced processes, and the compensation for the wafer edge region is more accurate. It can effectively solve the overlay accuracy differences caused by certain previous layers. This invention can significantly improve the wafer overlay accuracy and increase manufacturing yield. Attached Figure Description
[0018] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.
[0019] Figure 1 This is a schematic diagram showing a scenario where all units are translated in the same direction during overlay accuracy compensation.
[0020] Figure 2 This is a schematic diagram illustrating a scenario where the behavior of the wafer's center region and edge region is inconsistent during overlay accuracy compensation.
[0021] Figure 3 The diagram shows a step flow chart of the wafer alignment deviation compensation method in an embodiment of the present invention.
[0022] Figure 4 The diagram shows a wafer partitioning structure for a wafer alignment deviation compensation method according to an embodiment of the present invention.
[0023] Component designation explanation
[0024] 101 Central circle 102 First Ring 103 Second ring Detailed Implementation
[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0026] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.
[0027] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.
[0028] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0029] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.
[0030] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0031] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0032] Traditional overlay error compensation involves collecting data from the entire wafer, calculating the compensation values for various parameters using a model, and then feeding these parameters back to the lithography machine via an Advanced Process Control (APC) system. This model treats the entire wafer as a single region, and can only handle scenarios where all cells translate in the same direction. Figure 1 As shown, however, due to factors such as the non-uniformity of the preceding process, the thermal effect of the equipment, and differences in stress distribution, the overlay error fingerprints of the wafer center and the far edge often exhibit significant differences, or even completely opposite behaviors, such as... Figure 2 As shown, the overlay units on the outer side of the wafer are significantly offset towards the wafer edge, which is inconsistent with the performance of the overlay units in the middle (which have a lower offset or almost no offset). If the same model is used to compensate for the overlay accuracy of the middle and outer sides, it will not be possible to take into account the overlay accuracy of the middle and outer sides. As a result, the wafer cannot be compensated properly, which seriously affects the device performance and yield.
[0033] like Figure 3 and Figure 4 As shown, this embodiment provides a method for compensating for wafer alignment deviations. The compensation method includes the following steps:
[0034] like Figure 3 and Figure 4 As shown, step S11 is performed first, dividing the wafer into at least two radius-based partition regions.
[0035] In some embodiments, radius-based partitioning includes dividing the wafer into a central circle based on the wafer radius and at least one annulus extending sequentially from the central circle toward the outer edge of the wafer, wherein the annulus and the central circle are concentric.
[0036] In some embodiments, the number of rings is 2 to 5.
[0037] In some embodiments, the wafer can be divided into a central circle and at least one ring extending from the central circle toward the outer edge of the wafer, based on the difference in overlay error in the wafer radius direction. The dividing boundary can be dynamically adjusted according to historical data, previous process diagrams, or real-time measurement results.
[0038] In some embodiments, the partition radius ratio (relative to the wafer radius R) can be divided into a central circle 101 with radius R1 and a first ring 102 and a second ring 103 with outer radii R2 and R3 respectively. R1 can be selected as 30%, 40%, 50%, 60%, etc. of the wafer radius R; R2 can be selected as 50%, 60%, 80%, etc. of the wafer radius R; and R3 can be selected as 100% of the wafer radius R. Figure 4 As shown, the overlay accuracy of the central circle 101 has a small offset, and its required compensation value is small. However, the first ring 102 and the second ring 103 are offset towards the outer edge as a whole. For the first ring 102 and the second ring 103, the offset value of the second ring 103 is larger than the offset value of the first ring 102. Therefore, by performing partitioning processing in the overlay accuracy compensation, compensation can be performed separately for each different area, which greatly increases the compensation accuracy.
[0039] In a specific example, for a wafer with a diameter of 300mm, the partitioning is set as follows: the central circle 101 region is the area between 0mm and 75mm in wafer radius, the first ring 102 region is the area between 75mm and 120mm in wafer radius, and the second ring 103 region is the area between 120mm and 150mm in wafer radius.
[0040] like Figure 3 and Figure 4 As shown, then step S12 is performed to obtain the overlay accuracy measurement value of each partition area, and to calculate the overlay accuracy compensation value of each partition area based on the overlay accuracy measurement value of each partition area.
[0041] In some embodiments, obtaining the overlay accuracy measurement value of each partition region includes: setting one or more detection points in each partition region, and obtaining the actual overlay accuracy measurement value of each partition region based on the overlay accuracy measurement of the one or more detection points. For example, 3 to 5 detection points can be set in each partition region to obtain the actual overlay accuracy measurement value of each partition region.
[0042] In some embodiments, the overlay accuracy compensation value for each partition region is calculated using an overlay accuracy compensation model.
[0043] In some embodiments, each partition region may use the same overlay accuracy compensation model or different overlay accuracy compensation models.
[0044] In some embodiments, the overlay accuracy compensation model includes a 10-parameter overlay accuracy compensation model or a high-order polynomial overlay accuracy compensation model. For example, the 10-parameter overlay accuracy compensation model includes the following parameters: positioning error, straightness error in the Y direction during X-axis movement, straightness error in the Z direction during X-axis movement, rotation error around the X-axis, rotation error around the Y-axis, rotation error around the Z-axis, perpendicularity error between the X-axis and Y-axis, perpendicularity error between the X-axis and Z-axis, perpendicularity error between the Y-axis and Z-axis, and origin offset error of the axis.
[0045] like Figure 3 and Figure 4 As shown, then step S13 is performed, in which the overlay accuracy compensation value of each partition area is fed back to the lithography machine through the advanced process control system. The lithography machine performs overlay accuracy compensation on each partition area based on the overlay accuracy compensation value and then exposes the wafer.
[0046] In some embodiments, the method for compensating for overlay accuracy of each partition region includes translating, rotating, and / or scaling each partition region corresponding to the current exposure layer.
[0047] In some embodiments, the feedback method for feeding back the overlay accuracy compensation value of each partition area to the lithography machine can be real-time feedback or batch feedback.
[0048] In some embodiments, the wafer alignment deviation compensation method further includes the steps of: performing overlay accuracy detection on the exposed wafer, and further adjusting the overlay accuracy compensation value of the corresponding partition area based on the overlay accuracy detection result.
[0049] In some embodiments, the wafer alignment deviation compensation method can be used for advanced process nodes less than 28nm, or the wafer alignment deviation compensation method can also be used for 40nm or 55nm process nodes, etc., and can be used for advanced process modules such as 3D NAND memory, fin field-effect transistors, high-k metal gates, dual patterning technology, etc., and is not limited to the examples listed herein.
[0050] This embodiment also provides a semiconductor manufacturing apparatus, including: a lithography machine; an overlay accuracy measurement device; and an advanced process control system for performing a wafer alignment deviation compensation method as described in the above embodiment.
[0051] As described above, the wafer alignment deviation compensation method and semiconductor manufacturing equipment of the present invention have the following beneficial effects:
[0052] This invention achieves individual compensation for the overlay accuracy of different regions by dividing the wafer into radius regions and calculating the compensation value based on the overlay accuracy measurement value of each region. Compared with the traditional method of treating the entire wafer as a single region for overlay accuracy compensation, this invention achieves precise and differentiated compensation for wafer overlay accuracy. It is particularly suitable for scenarios where the behavior of the wafer center region and the edge region is inconsistent in advanced processes, and the compensation for the wafer edge region is more accurate. It can effectively solve the overlay accuracy differences caused by certain previous layers. This invention can significantly improve the wafer overlay accuracy and increase manufacturing yield.
[0053] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0054] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for compensating for wafer alignment deviation, characterized in that, The compensation method includes: Divide the wafer into at least two radius-based partition regions; Obtain the overlay accuracy measurement value for each of the partition regions, and calculate the overlay accuracy compensation value for each of the partition regions based on the overlay accuracy measurement value for each of the partition regions; The advanced process control system feeds back the overlay accuracy compensation value of each partition region to the lithography machine. The lithography machine performs overlay accuracy compensation on each partition region based on the overlay accuracy compensation value and then exposes the wafer.
2. The wafer alignment deviation compensation method according to claim 1, characterized in that: The radius-based division includes dividing the wafer into a central circle based on the wafer radius and at least one annulus extending sequentially from the central circle toward the outer edge of the wafer, wherein the annulus and the central circle are concentric.
3. The wafer alignment deviation compensation method according to claim 2, characterized in that: The number of the rings is 2 to 5.
4. The wafer alignment deviation compensation method according to claim 1, characterized in that: Obtaining the overlay accuracy measurement value for each partition region includes: setting one or more detection points in each partition region, and measuring the overlay accuracy based on the one or more detection points to obtain the actual overlay accuracy measurement value for each partition region.
5. The wafer alignment deviation compensation method according to claim 1, characterized in that: Methods for compensating for overlay accuracy in each zone include translating, rotating, and / or scaling the zone corresponding to the current exposure layer.
6. The wafer alignment deviation compensation method according to claim 1, characterized in that, It also includes the steps of: performing overlay accuracy detection on the exposed wafer, and further adjusting the overlay accuracy compensation value of the corresponding partition area based on the overlay accuracy detection results.
7. The wafer alignment deviation compensation method according to claim 1, characterized in that: The overlay accuracy compensation value for each zone is calculated using the overlay accuracy compensation model.
8. The wafer alignment deviation compensation method according to claim 7, characterized in that: Each of the aforementioned partitioned regions may use the same overlay accuracy compensation model or different overlay accuracy compensation models.
9. The wafer alignment deviation compensation method according to claim 7, characterized in that: The overlay accuracy compensation model includes a 10-parameter overlay accuracy compensation model or a high-order polynomial overlay accuracy compensation model.
10. A semiconductor manufacturing apparatus, characterized in that, include: Photolithography equipment; Overlay accuracy measuring device; An advanced process control system for performing the wafer alignment deviation compensation method as described in any one of claims 1 to 9.