Application programming interface for decompressing information

Abstract

The invention relates to an application programming interface for decompressing information. Apparatus, systems, and techniques for performing decompression on compressed data. In at least one embodiment, a processor executes an application programming interface to cause information to be decompressed and stored in one or more storage locations indicated by a user.

Description

Technical Field

[0001] Apparatus, systems, and methods for performing data decompression using processor hardware. In at least one embodiment, the processor includes one or more circuitry for executing an application programming interface to decompress information and store it in one or more storage locations indicated by a user. In at least one embodiment, the processor includes one or more circuitry for executing instructions to decompress information at least in part based on one or more instructions of one or more decompression algorithms. Background Technology

[0002] Compressed data received at the processor needs to be decompressed before it can be used in operations. Using software-based algorithms to perform data decompression consumes computational resources, slowing down the activation and processing speed of the operations. Data decompression can be improved by configuring the processor to perform decompression using hardware via CUDA code. Attached Figure Description

[0003] Figure 1 A processor for performing data decompression according to at least one embodiment is shown;

[0004] Figure 2A The basic architecture of a replication engine for performing data decompression according to at least one embodiment is shown;

[0005] Figure 2B The basic architecture of a dual-die replication engine for performing data decompression, according to at least one embodiment, is shown;

[0006] Figure 3 A block diagram of an application programming interface (API) according to at least one embodiment is shown, the API including instruction calls and instruction responses for identifying the decompression capabilities of a hardware device;

[0007] Figure 4 A block diagram of an application programming interface (API) according to at least one embodiment is shown, the API including instruction calls and instruction responses for identifying the maximum size that a hardware device can decompress;

[0008] Figure 5 A block diagram of an application programming interface (API) is shown, which includes instruction calls and instruction responses for identifying memory buffers capable of storing data during hardware device decompression.

[0009] Figure 6A block diagram of an application programming interface (API) is shown, which includes instruction calls and instruction responses for allocating memory in a buffer that has been identified as being capable of being used for hardware decompression.

[0010] Figure 7 A block diagram of an application programming interface (API) according to at least one embodiment is shown, the API including instruction calls and instruction responses for using hardware to decompress compressed data;

[0011] Figure 8 The process for performing hardware decompression according to at least one embodiment is illustrated;

[0012] Figure 9 A block diagram is shown of a driver and / or runtime comprising one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment;

[0013] Figure 10 A block diagram is shown of a driver and / or runtime comprising one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment;

[0014] Figure 11 An exemplary data center according to at least one embodiment is shown;

[0015] Figure 12 A processing system according to at least one embodiment is shown;

[0016] Figure 13 A computer system according to at least one embodiment is shown;

[0017] Figure 14 A system according to at least one embodiment is shown;

[0018] Figure 15 An exemplary integrated circuit according to at least one embodiment is shown;

[0019] Figure 16 A computing system according to at least one embodiment is shown;

[0020] Figure 17 An APU according to at least one embodiment is shown;

[0021] Figure 18 A CPU according to at least one embodiment is shown;

[0022] Figure 19 An exemplary accelerator integration slice according to at least one embodiment is shown;

[0023] Figures 20A-20B An exemplary graphics processor according to at least one embodiment is shown;

[0024] Figure 21A A graphics core according to at least one embodiment is shown;

[0025] Figure 21B A GPGPU according to at least one embodiment is shown;

[0026] Figure 22A A parallel processor according to at least one embodiment is shown;

[0027] Figure 22B A processing cluster according to at least one embodiment is shown;

[0028] Figure 22C A graphics multiprocessor according to at least one embodiment is shown;

[0029] Figure 23 A graphics processor according to at least one embodiment is shown;

[0030] Figure 24 A processor according to at least one embodiment is shown;

[0031] Figure 25 A processor according to at least one embodiment is shown;

[0032] Figure 26 A graphics processor core according to at least one embodiment is shown;

[0033] Figure 27 A PPU according to at least one embodiment is shown;

[0034] Figure 28 A GPC according to at least one embodiment is shown;

[0035] Figure 29 A streaming multiprocessor according to at least one embodiment is illustrated;

[0036] Figure 30 A software stack of a programming platform according to at least one embodiment is shown;

[0037] Figure 31 The illustration shows an embodiment according to at least one of the embodiments. Figure 30 The CUDA implementation of the software stack;

[0038] Figure 32 The illustration shows an embodiment according to at least one of the embodiments. Figure 30 The ROCm implementation of the software stack;

[0039] Figure 33 The illustration shows an embodiment according to at least one of the embodiments. Figure 30The OpenCL implementation of the software stack;

[0040] Figure 34 Software supported by a programming platform according to at least one embodiment is shown;

[0041] Figure 35 The illustration shows an embodiment of at least one of the following: Figures 30-33 Compiled code executed on the programming platform;

[0042] Figure 36 The illustration shows an embodiment of at least one of the following: Figures 30-33 More detailed compiled code executed on the programming platform;

[0043] Figure 37 This illustrates the transformation of source code before compilation, according to at least one embodiment;

[0044] Figure 38A A system configured to compile and execute CUDA source code using different types of processing units, according to at least one embodiment, is shown;

[0045] Figure 38B The diagram illustrates a configuration, according to at least one embodiment, to compile and execute using a CPU and a CUDA-enabled GPU. Figure 38A The system of CUDA source code;

[0046] Figure 38C The diagram illustrates a configuration, according to at least one embodiment, to compile and execute using a CPU and a GPU with CUDA disabled. Figure 38A The system of CUDA source code;

[0047] Figure 39 The diagram illustrates a method according to at least one embodiment. Figure 38C An example kernel converted by the CUDA to HIP conversion tool;

[0048] Figure 40 A more detailed description is provided according to at least one embodiment. Figure 38C GPUs without CUDA enabled;

[0049] Figure 41 This illustrates how threads of an exemplary CUDA grid, according to at least one embodiment, are mapped to... Figure 40 Different computational units;

[0050] Figure 42 This illustrates how to migrate existing CUDA code to data-parallel C++ code according to at least one embodiment; and

[0051] Figure 43Components of a system for accessing a large language model according to at least one embodiment are shown. Detailed Implementation

[0052] In at least one embodiment, the computing system uses a processor to transfer data to other processors. In at least one embodiment, the processor is part of a graphics processing unit (GPU), a general-purpose GPU (GPGPU), a parallel processing unit (PPU), a central processing unit (CPU), a data processing unit (DPU), a system-on-a-chip (SoC), and / or a combination thereof. In at least one embodiment, to save bandwidth, such data transferred between processors is compressed data. In at least one embodiment, the compressed data must be decompressed in order to be used at the receiving processor.

[0053] In at least one embodiment, software-based decompression is used to perform decompression. In at least one embodiment, this software-based decompression utilizes processor cores, processor clusters, streaming multiprocessors, and / or other processing units to perform the decompression. In at least one embodiment, because the processor cores, processor clusters, streaming multiprocessors, and / or other processing units are being used for decompression, other operations must wait until decompression is complete.

[0054] In at least one embodiment, hardware-based decompression is performed using another processing circuit, which frees up the processor core to perform the other operations. In at least one embodiment, hardware-based decompression is performed using the processor's replication engine so that decompression is performed while data is being transferred between processors or processing units. In at least one embodiment, hardware-based decompression is performed using a dual-die replication engine so that multiple data decompressions can be performed in parallel.

[0055] In at least one embodiment, decompression is activated by calling one or more application programming interfaces (APIs) to identify which decompressions can be performed using hardware, identifying memory that can be used for decompression, allocating memory for the decompression operation, and performing the decompression operation.

[0056] Figure 1A processor 100 for performing data decompression according to at least one embodiment is illustrated. In at least one embodiment, the processor 100 is part of and / or a combination of a graphics processing unit (GPU), a general-purpose GPU (GPGPU), a parallel processing unit (PPU), a central processing unit (CPU), a data processing unit (DPU), a system-on-a-chip (SoC), and so on. In at least one embodiment, the processor includes any other type of processor further described herein. In at least one embodiment, the processor 100 includes one or more processing clusters (PCs) 110 and a global memory 180 that stores information for use by the PCs 110. In at least one embodiment, the processor 100 can be used to execute an application programming interface to decompress information and store it in one or more storage locations indicated by a user. In at least one embodiment, the processor 100 can be used to execute instructions to decompress information at least in part based on one or more instructions of one or more decompression algorithms. In at least one embodiment, the processor 100 includes hardware decompression circuitry, which may be part of a copy engine.

[0057] In at least one embodiment, each processing cluster 110 includes a texture processing cluster (TPC) 120. In at least one embodiment, each texture processing cluster 120 includes one or more streaming multiprocessors (SM) 122, one or more copy engines (CE) 130, and / or one or more memories 150.

[0058] In at least one embodiment, each streaming multiprocessor (SM) 122 includes one or more tensor cores or acceleration circuits for performing arithmetic or logical computations, as instructed by threads from a cooperative thread array (CTA). In at least one embodiment, instructions, data, or operands to be used by the SM 122 to perform the arithmetic or logical computation are retrieved from memory 150 or global memory 180. In at least one embodiment, instructions, data, or operands to be used by the SM 122 to perform the arithmetic or logical computation are received from another processing cluster 110 in processor 100 and / or a processing cluster or unit of another processor, and received into the replication engine (CE) 130.

[0059] In at least one embodiment, a processor (e.g., a CPU) provides instructions to a different processor (e.g., a GPU) to perform a decompression operation. In at least one embodiment, processor 100 is a GPU that receives compressed data to be decompressed and decompression instructions from the CPU. In at least one embodiment, the instructions are application programming interface (API) calls that cause processor 100 to decompress the received compressed data. In at least one embodiment, the instructions are mid-level instructions, low-level instructions, machine-level instructions, machine code, assembly language, or other code specific to a given instruction set architecture (e.g., LLVM, PTX, ROCm, AMDGPU, HIP, HIPCC, UXL, etc.).

[0060] In at least one embodiment, the API instruction uses dedicated hardware to perform decompression to cause decompression. In at least one embodiment, the decompression hardware is part of the copy engine 130. In at least one embodiment, the instruction uses software programmed to perform decompression to cause decompression. In at least one embodiment, the decompression software is executed using one or more streaming multiprocessors 122.

[0061] In at least one embodiment, some or all of the processes described herein (or any other processes described, or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions and / or other data, and may be implemented as executable instructions that execute jointly on processor 100 or a combination of processors 100. In at least one embodiment, the executable instructions and / or other data may be stored on a non-transitory computer-readable storage medium (e.g., a computer program persistently stored on a magnetic, optical, or flash memory medium).

[0062] In at least one embodiment, processor 100 may execute reference Figure 8 The described process can be executed according to the reference. Figure 3-7 and Figure 9 The described instructions or application programming interface (API) functions can be compared with the reference. Figures 2A-2B The described structure can be used together, or can be used by any suitable system, such as the reference. Figure 11-43 Description or execution Figure 11-43 A computing device for the process. In at least one embodiment, Figure 1 The logic and hardware structure in it can be compared with Figure 2A-10 The systems, processors, architectures, and / or process integrations disclosed herein. For example, Figure 1 The logic / hardware structure within can execute at least some or all of the processes or APIs 300, 400, 500, 600, 700, 800, and / or 900. In at least one embodiment, Figure 1The logic and / or processes within can also be integrated into the system, processor, and architecture, and / or executed. Figure 11-43 The processes disclosed herein. In at least one embodiment, by executing at least some or all of the processes or APIs 300, 400, 500, 600, 700, 800 and / or 900, Figure 1 The systems or apparatus disclosed herein cause a processor to execute an application programming interface to decompress information and store it in one or more storage locations specified by a user. In at least one embodiment, this is achieved by executing at least some or all of the procedures or APIs 300, 400, 500, 600, 700, 800 and / or 900. Figure 1 The system or apparatus disclosed herein causes a processor to execute instructions such that information is decompressed based at least in part on one or more instructions of one or more decompression algorithms.

[0063] Figure 2A A basic hardware architecture for a replication engine 200 for performing data decompression, according to at least one embodiment, is shown. In at least one embodiment, a processor (e.g., Figure 1 The processor 100 in the process uses a copy engine (CE) 200 in response to calls to the application programming interface to decompress information and store it in one or more storage locations specified by the user. In at least one embodiment, the processor (e.g., Figure 1 The processor 100 in the copy engine 200 executes instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms.

[0064] In at least one embodiment, the processor (e.g.) Figure 1 The processor 100 in the system uses the replication engine 200 to perform various data transfer tasks. In at least one embodiment, the processor uses the replication engine 200 to transfer data between multiple graphics processing units (GPUs), general-purpose GPUs (GPGPUs), parallel processing units (PPUs), or between processing cores within said GPUs, GPGPUs, or PPUs. In at least one embodiment, the processor uses the replication engine 200 to transfer data between a central processing unit (CPU) and at least one of a GPU, GPGPU, or PPU. In at least one embodiment, the replication engine 200 is a data transfer circuit that enables data to be transferred from a source device or host device to a target device. In at least one embodiment, data to be transferred from the source is copied to the replication engine 200 and then copied from the replication engine 200 to the target.

[0065] In at least one embodiment, replication engine 200 includes a region having a plurality of physical replication engines (PCEs) 202 and a region having a plurality of logical replication engines (LCEs) 206. In at least one embodiment, one of the plurality of LCEs 206 designates and controls a subset of the plurality of PCEs 202 to perform various specific tasks. In at least one embodiment, PCEs 202 may include a subset designated for performing host-to-device data transfers, device-to-host data transfers, and / or NVLINK peer-to-peer transfers, wherein each LCE among the plurality of LCEs 206 can control each subset.

[0066] In at least one embodiment, the processor uses a copy function (e.g., memcpy from NVIDIA CUDA) to copy information from a source to copy engine 200 or from copy engine 200 to a destination to facilitate data transfer. In at least one embodiment, the copy function includes parameters indicating various parameters, such as destination memory location, source memory location, data size, and copy type. In at least one embodiment, the copy type parameter indicates that decompression will be performed by PCE 202. In at least one embodiment, these parameters are passed to a function (e.g., the copy function) using instructions or an application programming interface (API) to perform decompression on the target data located at the indicated source memory location.

[0067] In at least one embodiment, a subset of PCE 202 is designated as decompression PCE 204. In at least one embodiment, decompression PCE 204 performs hardware-based decompression to generate uncompressed data from compressed data received by replication engine 200. In at least one embodiment, decompression PCE 204 is pre-programmed in software or otherwise designed to perform discrete, specified decompression algorithms. In at least one embodiment, decompression PCE 204 is pre-programmed to decompress data using one or more decompression algorithms corresponding to commonly used compression algorithms, such as deflate compression, GZIP compression, LZ4 compression, and / or Snappy compression. In at least one embodiment, these pre-programmed settings or algorithms are stored in a semiconductor intellectual property (IP) core or a block of PCE 204. In at least one embodiment, if the received compressed data does not use a commonly used compression algorithm, the data can be converted to match one of the pre-programmed decompression algorithms before decompression is performed by decompression PCE 204. In at least one embodiment, if the received compressed data does not use a common compression algorithm, the data can be transmitted to a processing cluster (e.g., ...) without decompression. Figure 1 The processing cluster 110) can be used as an auxiliary decompression option to utilize one or more streaming multiprocessors (e.g., Figure 1The SM 122 performs software-based decompression.

[0068] In at least one embodiment, when data is decompressed using a decompression PCE 204, the data can be divided and distributed across multiple decompression PCEs 204 to perform decompression in parallel. In at least one embodiment, when data is to be decompressed, the data can be divided into multiple parts, but these parts are decompressed serially in a single or group of PCEs.

[0069] In at least one embodiment, the replication engine 200 may be part of the processor 100 (e.g., as replication engine 130), and some or all of the processes described herein (or any other processes described, or variations and / or combinations of these processes) may be executed under the control of one or more computer systems configured with executable instructions and / or other data, and may be implemented as executable instructions that execute jointly on processor 100 or a combination of processors 100. In at least one embodiment, the executable instructions and / or other data may be stored on a non-transitory computer-readable storage medium (e.g., a computer program persistently stored on a magnetic, optical, or flash memory medium).

[0070] Figure 2B A basic hardware architecture for a dual-die replication engine 210 for performing data decompression, according to at least one embodiment, is shown. In at least one embodiment, the processor (e.g., Figure 1 The processor 100 in the process uses a dual-die replication engine (CE) 210 to decompress information and store it in one or more storage locations specified by the user in response to calls to the application programming interface. In at least one embodiment, the processor (e.g., Figure 1 The processor 100 in the process uses the dual-die copy engine 210 to execute instructions such that information is decompressed at least in part based on one or more instructions of one or more decompression algorithms.

[0071] In at least one embodiment, the processor (e.g.) Figure 1 The processor 100 uses a dual-die copy engine 210 to perform various data transfer tasks. In at least one embodiment, the processor uses the dual-die copy engine 210 to transfer data between multiple graphics processing units (GPUs), general-purpose GPUs (GPGPUs), parallel processing units (PPUs), or between processing cores within said GPUs, GPGPUs, or PPUs. In at least one embodiment, the processor uses the dual-die copy engine 210 to transfer data between a central processing unit (CPU) and at least one of a GPU, GPGPU, or PPU.

[0072] In at least one embodiment, the dual-die replication engine 210 includes multiple replication engines embodied on a single chip (e.g., Figure 2A The dual-die replication engine 210 includes: a first side comprising a first plurality of physical replication engines (PCEs) 212 and a first plurality of logical replication engines (LCEs) 216; and a second side comprising a second plurality of physical replication engines (PCEs) 222 and a second plurality of logical replication engines (LCEs) 226.

[0073] In at least one embodiment, the processor uses a copy function (e.g., memcpy from NVIDIA CUDA) to copy information from a source to copy engine 210 or from copy engine 210 to a destination to facilitate data transfer. In at least one embodiment, the copy function includes parameters indicating various parameters, such as destination memory location, source memory location, data size, and copy type. In at least one embodiment, the copy type parameter indicates that decompression will be performed by decompression PCE 214 or 224. In at least one embodiment, these parameters are passed to a function (e.g., the copy function) using instructions or an application programming interface (API) to perform decompression on the target data located at the indicated source memory location.

[0074] In at least one embodiment, the size of the file to be decompressed is larger than the size that can be decompressed in a single operation. In at least one embodiment, the decompression operation comprises a series of smaller decompression operations distributed across decompression PCEs 214 and / or 224. In at least one embodiment, these smaller decompression operations are distributed across PCEs of a single die of the replication engine (e.g., across multiple decompression PCEs 214). In at least one embodiment, these smaller decompression operations are distributed across PCEs of the entire replication engine (e.g., multiple decompression PCEs 214 and multiple decompression PCEs 224). In at least one embodiment, these smaller decompression operations are distributed to perform load balancing and parallelize the decompression operations, thereby improving execution speed. In at least one embodiment, load balancing is evenly distributed among the decompression PCEs. In at least one embodiment, load balancing is unevenly distributed among the decompression PCEs to account for differences in processing requirements, such as differences in the number of bytes to be processed in each smaller operation.

[0075] In at least one embodiment, the first side of the dual-die replication engine 210 includes a plurality of physical replication engines (PCEs) 212 and a plurality of logical replication engines (LCEs) 216. In at least one embodiment, one of the plurality of LCEs 216 designates and controls a subset of the plurality of PCEs 212 to perform various specific tasks of the first die of the dual-die replication engine 210. In at least one embodiment, the PCEs 212 may include a subset designated for performing host-to-device data transfers, device-to-host data transfers, and / or NVLINK peer-to-peer transfers, wherein each of the plurality of LCEs 216 can control each subset within the first side of the dual-die replication engine 210.

[0076] In at least one embodiment, the first PCE 212 further includes a subset of PCEs designated as decompression PCE 214. In at least one embodiment, the decompression PCE 214 performs hardware-based decompression to generate uncompressed data from compressed data received from the dual-die replication engine 210. In at least one embodiment, the decompression PCE 214 is pre-programmed to decompress data using one or more decompression algorithms corresponding to common compression algorithms, such as deflate compression, GZIP compression, LZ4 compression, and / or Snappy compression. In at least one embodiment, if the received compressed data does not use a common compression algorithm, the data can be converted to match one of the pre-programmed decompression algorithms before decompression is performed by the decompression PCE 214. In at least one embodiment, if the received compressed data does not use a common compression algorithm, the data can be transmitted to the processing cluster (e.g., ...) without decompression. Figure 1 The processing cluster 110 in the middle) can use one or more streaming multiprocessors as an auxiliary decompression option (e.g., Figure 1 The SM 122 in the middle performs software-based decompression.

[0077] In at least one embodiment, the second side of the dual-die replication engine 210 includes a plurality of physical replication engines (PCEs) 222 and a plurality of logical replication engines (LCEs) 226. In at least one embodiment, one of the plurality of LCEs 226 designates and controls a subset of the plurality of PCEs 222 to perform various specific tasks of the second die of the dual-die replication engine 210. In at least one embodiment, the PCEs 222 may include a subset designated for performing host-to-device data transfers, device-to-host data transfers, and / or NVLINK peer-to-peer transfers, wherein each of the plurality of LCEs 226 can control each subset within the second side of the dual-die replication engine 210.

[0078] In at least one embodiment, the second PCE 212 further includes a subset of PCEs designated as decompression PCE 224. In at least one embodiment, decompression PCE 224 performs hardware-based decompression to generate uncompressed data from compressed data received from the dual-die replication engine 210. In at least one embodiment, decompression PCE 224 is pre-programmed to decompress data using one or more decompression algorithms corresponding to common compression algorithms, such as deflate compression, GZIP compression, LZ4 compression, and / or Snappy compression. In at least one embodiment, if the received compressed data does not use a common compression algorithm, the data can be converted to match one of the pre-programmed decompression algorithms before decompression is performed by decompression PCE 224. In at least one embodiment, if the received compressed data does not use a common compression algorithm, the data can be transmitted to the processing cluster (e.g., ...) without decompression. Figure 1 The processing cluster 110 in the middle) can use one or more streaming multiprocessors as an auxiliary decompression option (e.g., Figure 1 The SM 122 in the middle performs software-based decompression.

[0079] In at least one embodiment, the first LCE 216 and the second LCE 226 receive instructions or batch of instructions to perform an operation, such as decompression. In at least one embodiment, the instructions or batch of instructions indicate whether the operation will be performed by either or both of LCEs 216 and 226. In at least one embodiment, if the instructions or batch of instructions will be performed by both the first LCE 216 and the second LCE 226, the dual-die replication engine 210 performs replication splitting and / or load balancing to specify which LCEs will execute one or more portions of the instructions or batch of instructions.

[0080] In at least one embodiment, the dual-die replication engine 210 may be part of the processor 100 (e.g., as replication engine 130), and some or all of the processes described herein (or any other processes described, or variations and / or combinations of these processes) may be executed under the control of one or more computer systems configured with executable instructions and / or other data, and may be implemented as executable instructions that execute jointly on processor 100 or a combination of processors 100. In at least one embodiment, the executable instructions and / or other data may be stored on a non-transitory computer-readable storage medium (e.g., a computer program persistently stored on a magnetic, optical, or flash memory medium).

[0081] In at least one embodiment, Figure 2B The hardware architecture (e.g., replication engine 210) can perform reference... Figure 8 The described process can be executed according to the reference. Figure 3-7 and Figure 9 The described instructions or application programming interface (API) functions can be compared with the reference. Figure 2B The described structure can be used together, or can be used by any suitable system, such as the reference. Figure 11-43 Description or execution Figure 11-43 A computing device for the process. In at least one embodiment, Figure 2B Its logic and hardware structure can be compared with Figure 1 and Figure 3-10 The systems, processors, architectures, and / or process integrations disclosed herein. For example, Figure 2B The logic / hardware structure in the code can execute at least some or all of the processes or APIs 300, 400, 500, 600, 700, 800, and / or 900. In at least one embodiment, by executing at least some or all of the processes or APIs 300, 400, 500, 600, 700, 800, and / or 900, Figure 2B The systems or apparatus disclosed herein cause a processor to execute an application programming interface to decompress information and store it in one or more storage locations specified by a user. In at least one embodiment, this is achieved by executing at least some or all of the procedures or APIs 300, 400, 500, 600, 700, 800 and / or 900. Figure 2B The system or apparatus disclosed herein causes a processor to execute instructions such that information is decompressed based at least in part on one or more instructions of one or more decompression algorithms.

[0082] In at least one embodiment, Figure 2A-2B The logic and hardware architecture can be integrated into Figure 1 and Figure 3-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 2A-2B The logic / hardware structure within can execute at least some or all of the processes or APIs 300, 400, 500, 600, 700, 800, and / or 900. In at least one embodiment, Figure 2A-2B Its logic and hardware structure can be compared with Figure 1 and Figure 3-10 The system, processor, architecture, and / or process integration disclosed herein. In at least one embodiment, Figure 2A-2B The logic, hardware architecture, and / or processes (e.g., replication engine 200 or dual-die replication engine 210) can also be integrated into the system, processor, and architecture, and / or executed. Figure 11-43 The process disclosed herein may be part or all of the process. In at least one embodiment, Figure 2A-2BThe disclosed system or apparatus causes a processor to execute an application programming interface (API) in response to an API call, such that information is decompressed and stored in one or more storage locations specified by a user. In at least one embodiment, Figure 2A-2B The system or apparatus disclosed herein executes instructions to cause a processor to execute instructions such that information is decompressed based at least in part on one or more instructions of one or more decompression algorithms.

[0083] Figure 3 A block diagram of an application programming interface (API) 300 according to at least one embodiment is shown. The API 300 includes instruction calls and instruction responses for identifying the decompression capabilities of a hardware device. In at least one embodiment, a processor (e.g., Figure 1 The processor 100 in the process calls API 300 in response to an application programming interface call, causing information to be decompressed and stored in one or more storage locations indicated by the user. In at least one embodiment, the processor (e.g., Figure 1 The processor 100 in the process calls API 300 to execute instructions such that information is decompressed at least in part based on one or more instructions of one or more decompression algorithms.

[0084] In at least one embodiment, one or more processors perform one or more operations of API 300. In at least one embodiment, the processor performing one or more operations of API 300 is any one of the processors described herein or a combination of processors, including... Figure 1 The processor 100 is used in the process. In at least one embodiment, two or more processors performing the operations of API 300 are mounted on different computing machines (e.g., servers), different server racks, different data centers, or some combination thereof. In at least one embodiment, the processor performing the operations of API 300 performs operations, such as decompression operations for decompressing information and storing it in one or more storage locations indicated by the user. In at least one embodiment, the processor performing the operations of API 300 executes instructions, such as instructions for causing information to be decompressed at least partially based on one or more decompression algorithms. In at least one embodiment, the processor performing the operations of API is combined with... Figure 1-2B and Figure 8 The described process or structure, when used in combination, can be executed according to the reference. Figure 4-7 and Figure 9 The described instructions or application programming interface (API) functions, or those that can be used by any suitable system, such as the reference. Figure 11-43 Described or executed Figure 11-43The computing device for the process.

[0085] In at least one embodiment, the processor executes API 300 to issue device attribute instruction 302 to identify whether the processing hardware is capable of performing hardware-based decompression. In at least one embodiment, device attribute instruction 302 is initiated by a thread in a streaming multiprocessor or processor cluster. In at least one embodiment, device attribute instruction 302 causes a replication engine, streaming multiprocessor, processor core, MMA accelerator, tensor core, or other processing unit to perform one or more of the operations described herein, including combinations. Figure 1-2B and Figure 4-10 The described operation. In at least one embodiment, the processor uses API 300 to indicate one or more decompression algorithms to be used to decompress the compressed data.

[0086] In at least one embodiment, in response to a query received in instruction 302, the processor identifies specific parameters of the system hardware and whether the hardware is capable of performing decompression. In at least one embodiment, device attribute response 304 generates and returns an indication indicating which decompression algorithms (if any) the system hardware can perform. In at least one embodiment, if the hardware cannot perform decompression, any data decompression is specified as: as an auxiliary decompression option, by the processing cluster (e.g., Figure 1 The processing cluster 110 in the middle uses software-based decompression on one or more streaming multiprocessors (e.g., Figure 1 Execute in SM 122).

[0087] In at least one embodiment, example code for executing API 300 is as follows:

[0088]

[0089]

[0090] The values ​​in the bitmask identify which decompression algorithms the hardware supports (if any):

[0091]

[0092] In at least one embodiment, some or all of the processes described herein (or any other processes described, or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions and / or other data, and may be implemented as executable instructions that execute jointly on processor 100 or a combination of processors 100. In at least one embodiment, the executable instructions and / or other data may be stored on a non-transitory computer-readable storage medium (e.g., a computer program persistently stored on a magnetic, optical, or flash memory medium).

[0093] In at least one embodiment, Figure 3 The logic and / or procedures in can be integrated into Figure 1-2B and Figure 4-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 1-2B The logic / hardware structure within can execute at least some or all of the processes or APIs 300, 400, 500, 600, 700, 800, and / or 900. In at least one embodiment, Figure 3 The logic and / or processes within can be additionally integrated into the system, processor, and architecture, and / or executed. Figure 11-43 The process disclosed herein may be partially or entirely. In at least one embodiment, the process is performed. Figure 3 The disclosed API enables the processor to execute an application programming interface to decompress and store information in one or more storage locations specified by the user. In at least one embodiment, execution... Figure 3 The API disclosed in the document enables the circuit to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms.

[0094] Figure 4 A block diagram of an application programming interface (API) 400 according to at least one embodiment is shown. The API 400 includes instruction calls and instruction responses for identifying the maximum size that a hardware device can decompress. In at least one embodiment, the processor (e.g., Figure 1 The processor 100 in the process calls API 400 to decompress information and store it in one or more storage locations indicated by the user in response to an application programming interface call. In at least one embodiment, the processor (e.g., Figure 1 The processor 100 in the process calls API 400 to execute instructions such that information is decompressed at least in part based on one or more instructions of one or more decompression algorithms.

[0095] In at least one embodiment, one or more processors perform one or more operations of API 400. In at least one embodiment, the processor performing one or more operations of API 400 is any one or a combination of processors described herein, including... Figure 1 The processor 100 is used in the API 400. In at least one embodiment, two or more processors performing the operations of API 400 are mounted on different computing machines (e.g., servers), different server racks, different data centers, or some combination thereof. In at least one embodiment, the processor performing the operations of API 400 performs operations, such as decompression operations for decompressing information and storing it in one or more storage locations indicated by the user. In at least one embodiment, the processor performing the operations of API 400 executes instructions, such as instructions for causing information to be decompressed at least partially based on one or more decompression algorithms. In at least one embodiment, the processor performing the operations of API 400 is combined with... Figure 1-2B and Figure 8 The described process or structure, when used in combination, can be executed according to the reference. Figure 3 , Figure 5-7 and Figure 9 The described instructions or application programming interface (API) functions, or those that can be used by any suitable system, such as the reference. Figure 11-43 Described or executed Figure 11-43 The computing device for the process.

[0096] In at least one embodiment, the processor executes API 400 to issue a device decompression size limit instruction 402, for identifying the maximum size that the hardware device can decompress for a given instruction. In at least one embodiment, the decompression size limit instruction 402 is initiated by a thread in a streaming multiprocessor or processor cluster. In at least one embodiment, the decompression size limit instruction 402 causes a replication engine, streaming multiprocessor, processor core, MMA accelerator, tensor core, or other processing unit to perform one or more of the operations described herein, including combining... Figure 1-3 and Figure 5-10 The described operation. In at least one embodiment, the processor uses API 400 as at least part of the decompression operation.

[0097] In at least one embodiment, the size of the data file that the processor can decompress in a given operation can be fixed by the user or the processor's hardware capabilities. In at least one embodiment, the size of the data file that can be decompressed by the decompression circuitry ranges from 512KB to 4GB. In at least one embodiment, the processor uses multiple decompression PCEs (e.g., Figure 2AThe decompression PCE 204 in the process decompresses portions of the data file in parallel (e.g., a 512-byte portion of a 512KB total data file) to accelerate the decompression operation.

[0098] In at least one embodiment, in response to a query received in instruction 402, the processor identifies a maximum decompression size parameter in the system hardware. In at least one embodiment, a decompression size limit response 404 generates and returns an indication of the maximum decompression size executable by the system hardware. In at least one embodiment, the information indicated by the decompression size limit response 404 is used to prevent memory overflow or other errors.

[0099] In at least one embodiment, example code for executing API 400 is as follows:

[0100]

[0101] In at least one embodiment, some or all of the processes described herein (or any other processes described, or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions and / or other data, and may be implemented as executable instructions that execute jointly on processor 100 or a combination of processors 100. In at least one embodiment, the executable instructions and / or other data may be stored on a non-transitory computer-readable storage medium (e.g., a computer program persistently stored on a magnetic, optical, or flash memory medium).

[0102] In at least one embodiment, Figure 4 The logic and / or processes can be integrated into Figure 1-3 and Figure 4-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 1-2B The logic / hardware structure within can execute at least some or all of the processes or APIs 300, 400, 500, 600, 700, 800, and / or 900. In at least one embodiment, Figure 4 The logic and / or processes within can be additionally integrated into the system, processor, and architecture, and / or executed. Figure 11-43 The disclosed part or all of the process. In at least one embodiment, the process is performed. Figure 4 The disclosed API enables the processor to execute an application programming interface to decompress and store information in one or more storage locations specified by the user. In at least one embodiment, execution... Figure 4 The API disclosed in the document enables the circuit to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms.

[0103] Figure 5A block diagram of an application programming interface (API) 500 according to at least one embodiment is shown. The API 500 includes instruction calls and instruction responses for identifying a memory buffer capable of storing data during decompression by a hardware device. In at least one embodiment, the processor (e.g., Figure 1 The processor 100 in the process calls API 500 to decompress information and store it in one or more storage locations specified by the user in response to an application programming interface call. In at least one embodiment, the processor (e.g., Figure 1 The processor 100 in the process calls API 500 to execute instructions such that information is decompressed at least in part based on one or more instructions of one or more decompression algorithms.

[0104] In at least one embodiment, one or more processors perform one or more operations of API 500. In at least one embodiment, the processor performing one or more operations of API 500 is any one or a combination of processors described herein, including... Figure 1 The processor 100 is used in the process. In at least one embodiment, two or more processors performing the operations of API 500 are installed on different computers (e.g., servers), different server racks, different data centers, or some combination thereof. In at least one embodiment, the processor performing the operations of API 500 performs operations, such as decompression operations for decompressing information and storing it in one or more storage locations indicated by the user. In at least one embodiment, the processor performing the operations of API 500 executes instructions, such as instructions for causing information to be decompressed at least partially based on one or more decompression algorithms. In at least one embodiment, the processor performing the operations of API 500 is combined with... Figure 1-2B and Figure 8 The described process or structure, when used in combination, can be executed according to the reference. Figure 3-4 , Figure 6-7 and Figure 9-10 The described instructions or application programming interface (API) functions, or those that can be used by any suitable system, such as the reference. Figure 11-43 Description or execution Figure 11-43 The computing device for the process.

[0105] In at least one embodiment, the processor executes API 500 to issue a memory capability instruction 502 for identifying a hardware buffer capable of receiving compressed data, storing data during decompression, and / or receiving uncompressed data. In at least one embodiment, the memory capability instruction 502 is initiated by a thread in a streaming multiprocessor or processor cluster. In at least one embodiment, the memory capability instruction 502 causes a replication engine, streaming multiprocessor, processor core, MMA accelerator, tensor core, or other processing unit to perform one or more of the operations described herein, including combinations. Figure 1-4 and Figure 6-10 The described operation. In at least one embodiment, the processor uses API 500 as part of a decompression operation to indicate whether a memory location can store compressed data or decompressed data. In at least one embodiment, if API 500 indicates that a location can store data or decompressed data, a copy type parameter of a copy function (e.g., memcpy in NVIDIA CUDA) can be set to perform decompression on the target data located in the indicated source memory location.

[0106] In at least one embodiment, in response to receiving a memory pointer in instruction 502, the processor identifies whether a memory buffer at the location identified by the memory pointer is capable of being used for hardware decompression. In at least one embodiment, a memory capability response 504 generates and returns an indication that the memory at the location indicated by the memory pointer is capable of being used for hardware decompression. In at least one embodiment, the information indicated by the memory capability response 504 is used to identify a memory buffer with sufficient capacity or speed to prevent memory overflow or other errors.

[0107] In at least one embodiment, example code for executing API 500 is as follows:

[0108]

[0109] In at least one embodiment, some or all of the processes described herein (or any other processes described, or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions and / or other data, and may be implemented as executable instructions that execute jointly on processor 100 or a combination of processors 100. In at least one embodiment, the executable instructions and / or other data may be stored on a non-transitory computer-readable storage medium (e.g., a computer program persistently stored on a magnetic, optical, or flash memory medium).

[0110] In at least one embodiment, Figure 5 The logic and / or processes can be integrated into Figure 1-4 and Figure 5-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 1-2B The logic / hardware structure within can execute at least some or all of the processes or APIs 300, 400, 500, 600, 700, 800, and / or 900. In at least one embodiment, Figure 5 The logic and / or processes within can be additionally integrated into the system, processor, and architecture, and / or executed. Figure 11-43 The process disclosed herein may be partially or entirely. In at least one embodiment, the process is performed. Figure 5 The disclosed API enables the processor to execute an application programming interface to decompress and store information in one or more storage locations specified by the user. In at least one embodiment, execution... Figure 5 The API disclosed in the document enables the circuit to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms.

[0111] Figure 6 A block diagram of an application programming interface (API) 600 according to at least one embodiment is shown. The API 600 includes instruction calls and instruction responses for allocating memory in a buffer identified as capable of hardware decompression. In at least one embodiment, the processor (e.g., Figure 1 The processor 100 in the process calls API 600 to decompress information and store it in one or more storage locations specified by the user in response to an application programming interface call. In at least one embodiment, the processor (e.g., Figure 1 The processor 100 in the process calls API 600 to execute instructions such that information is decompressed at least in part based on one or more instructions of one or more decompression algorithms.

[0112] In at least one embodiment, one or more processors perform one or more operations of API 600. In at least one embodiment, the processor performing one or more operations of API 600 is any one or a combination of processors described herein, including... Figure 1The processor 100 is used in the process. In at least one embodiment, two or more processors performing the operations of API 600 are mounted on different computing machines (e.g., servers), different server racks, different data centers, or some combination thereof. In at least one embodiment, the processor performing the operations of API 600 performs operations, such as decompression operations for decompressing information and storing it in one or more storage locations indicated by the user. In at least one embodiment, the processor performing the operations of API 600 executes instructions, such as instructions for causing information to be decompressed at least in part based on one or more decompression algorithms. In at least one embodiment, the processor performing the operations of API 600 is combined with... Figure 1-2B and Figure 8 The described process or structure, when used in combination, can be executed according to the reference. Figure 3-5 , Figure 7 and Figure 9-10 The described instructions or application programming interface (API) functions, or those that can be used by any suitable system, such as the reference. Figure 11-43 Described or executed Figure 11-43 The computing device for the process.

[0113] In at least one embodiment, the processor executes API 600 to issue a memory allocation instruction 602 for allocating memory (e.g., as identified using API 500) in a hardware buffer capable of being used for hardware decompression. In at least one embodiment, the memory allocation instruction 602 is initiated by a thread in a streaming multiprocessor or processor cluster. In at least one embodiment, the memory allocation instruction 602 causes a replication engine, streaming multiprocessor, processor core, MMA accelerator, tensor core, or other processing unit to perform one or more of the operations described herein, including combining... Figure 1-5 and Figure 7-10 The described operation. In at least one embodiment, the processor uses API 600 as part of a decompression operation to allocate memory for compressed or decompressed data. In at least one embodiment, if API 600 allocates memory for compressed or decompressed data, a copy type parameter of a copy function (e.g., memcpy in NVIDIA CUDA) can be set to perform operations of reading compressed data from the memory location and / or writing decompressed data to the memory location.

[0114] In at least one embodiment, the memory allocation instruction 602 submits instructions for allocating memory for decompression and a usage flag indicating that the memory is allocated for hardware decompression. In at least one embodiment, the memory allocation response 604 allocates the memory and returns an indication that the memory allocation has been successfully completed.

[0115] In at least one embodiment, the example code for executing API 600 is as follows:

[0116] CUmemAllocationProp prop={}; prop.location.id=device;

[0117] prop.location.type=CU_MEM_LOCATION_TYPE_DEVICE;

[0118] prop.type=CU_MEM_ALLOCATION_TYPE_PINNED;

[0119] prop.allocFlags.usage=CU_MEM_CREATE_USAGE_HW_DECOMPRESS;

[0120] CUmemGenericAllocationHandle handle;

[0121] cuMemCreate(&handle,size,&prop,0));

[0122] In at least one embodiment, some or all of the processes described herein (or any other processes described, or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions and / or other data, and may be implemented as executable instructions that execute jointly on processor 100 or a combination of processors 100. In at least one embodiment, the executable instructions and / or other data may be stored on a non-transitory computer-readable storage medium (e.g., a computer program persistently stored on a magnetic, optical, or flash memory medium).

[0123] In at least one embodiment, Figure 6 The logic and / or procedures in can be integrated into Figure 1-5 and Figure 7-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 1-2B The logic / hardware structure within can execute at least some or all of the processes or APIs 300, 400, 500, 600, 700, 800, and / or 900. In at least one embodiment, Figure 6 The logic and / or processes within can also be integrated into the system, processor, and architecture, and / or executed. Figure 11-43 The process disclosed herein may be partially or entirely. In at least one embodiment, the process is performed. Figure 6The disclosed API enables the processor to execute an application programming interface to decompress and store information in one or more storage locations specified by the user. In at least one embodiment, execution... Figure 6 The API disclosed in the document enables the circuit to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms.

[0124] Figure 7 A block diagram of an application programming interface (API) 700 according to at least one embodiment is shown. The API 700 includes instruction calls and instruction responses for decompressing compressed data using hardware. In at least one embodiment, a processor (e.g., Figure 1 The processor 100 in the process calls API 700 to decompress information and store it in one or more storage locations indicated by the user in response to an application programming interface call. In at least one embodiment, the processor (e.g., Figure 1 The processor 100 in the process calls API 700 to execute instructions such that information is decompressed at least in part based on one or more instructions of one or more decompression algorithms.

[0125] In at least one embodiment, one or more processors perform one or more operations of API 700. In at least one embodiment, the processor performing one or more operations of API 700 is any of the processors or combinations of processors described herein, including... Figure 1 The processor 100 is used in the process. In at least one embodiment, two or more processors performing the operations of API 700 are mounted on different computing machines (e.g., servers), different server racks, different data centers, or some combination thereof. In at least one embodiment, the processor performing the operations of API 700 performs operations, such as decompression operations for decompressing information and storing it in one or more storage locations indicated by the user. In at least one embodiment, the processor performing the operations of API 700 executes instructions, such as instructions for causing information to be decompressed based at least in part on one or more decompression algorithms. In at least one embodiment, the processor performing the operations of API 700 is combined with... Figure 1-2B and Figure 8 The described process or structure, when used in combination, can be executed according to the reference. Figure 3-6 and Figure 9 The described instructions or application programming interface (API) functions, or those that can be used by any suitable system, such as the reference... Figure 11-43 Description or execution Figure 11-43 The computing device for the process.

[0126] In at least one embodiment, the processor executes API 700 to issue a decompression instruction 702 for performing hardware decompression of compressed data. In at least one embodiment, the decompression instruction 702 is initiated by a thread in a streaming multiprocessor or processor cluster. In at least one embodiment, the decompression instruction 702 causes a replication engine, streaming multiprocessor, processor core, MMA accelerator, tensor core, or other processing unit to perform one or more of the operations described herein, including combining... Figure 1-6 and Figure 8-10 The described operation. In at least one embodiment, the processor uses API 700 at least as part of a decompression operation. In at least one embodiment, when API 700 is invoked, the hardware circuitry (e.g., Figure 1 The copy engine transmits compressed data to the decompression circuit (e.g., Figure 2A-2B The PCE (Programmable Execution Environment) is used to perform decompression, and then the result is transferred to the specified target location.

[0127] In at least one embodiment, decompression instruction 702 submits a decompression request, along with associated decompression parameters and load balancing parameters. In at least one embodiment, the decompression parameters include a pointer to a memory buffer containing compressed data, the size of the data after decompression, a pointer to a memory buffer to store the decompressed data, the decompression algorithm to be used, and / or other parameters related to decompression. In at least one embodiment, the load balancing parameters include a value indicating how many parts a batch of instructions should be divided into, such that each part is composed of the plurality of LCEs (e.g., ...). Figure 2A-2B The decompression is performed on one of the LCEs (LCEs 206, 216, and / or 226) in the stream. In at least one embodiment, the decompression response 704 returns the decompressed data to the stream and / or returns an indication of the memory location to the decompressed data.

[0128] In at least one embodiment, example code for executing API 700 is as follows:

[0129] CUresult libraryDecompressBatchAsync(

[0130] CUmemDecompressParams*const params,

[0131] const size_t count,

[0132] void*const tmp,

[0133] const CUmemDecompressBatchConfig*const config,

[0134] CUstream stream){

[0135] CUdevice device;

[0136] cuCtxGetDevice(&device);

[0137] CUmemDecompressAlgorithm algo=config->algo;

[0138] return cuMemDecompressBatchAsync(params,count,config,stream);}

[0139] In at least one embodiment, some or all of the processes described herein (or any other processes described, or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions and / or other data, and may be implemented as executable instructions that execute jointly on processor 100 or a combination of processors 100. In at least one embodiment, the executable instructions and / or other data may be stored on a non-transitory computer-readable storage medium (e.g., a computer program persistently stored on a magnetic, optical, or flash memory medium).

[0140] In at least one embodiment, Figure 7 The logic and / or procedures in can be integrated into Figure 1-6 and Figure 8-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 1-2B The logic / hardware structure within can execute at least some or all of the processes or APIs 300, 400, 500, 600, 700, 800, and / or 900. In at least one embodiment, Figure 7 The logic and / or processes can be additionally integrated into the system, processor, and architecture, and / or executed. Figure 11-43 The process disclosed herein may be partially or entirely. In at least one embodiment, the process is performed. Figure 7 The disclosed API enables the processor to execute an application programming interface to decompress and store information in one or more storage locations specified by the user. In at least one embodiment, execution... Figure 7 The API disclosed in the document enables the circuit to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms.

[0141] Figure 8 A process 800 for performing hardware decompression according to at least one embodiment is illustrated. In at least one embodiment, a processor (e.g., Figure 1 The processor 100 in the process executes process 800 to perform decompression using decompression circuitry. In at least one embodiment, the processor executing process 800 (e.g., ...) Figure 1 The processor 100 in the process 800, in response to a call to the application programming interface, decompresses the information and stores it in one or more storage locations indicated by the user. In at least one embodiment, the processor executing the process 800 (e.g., Figure 1 The processor 100 in the processor executes instructions to decompress the information at least in part based on one or more instructions of one or more decompression algorithms.

[0142] In at least one embodiment, in step 802, the processor receives instructions to perform decompression and compressed data to be decompressed from the user (e.g., via API 700). In at least one embodiment, the decompression is a hardware-based decompression performed in hardware, such as a copy engine (e.g., Figure 1 Replication engine 130 Figure 2A Copy engine 200 or Figure 2B The replication engine 210). In at least one embodiment, the decompression is performed as an auxiliary decompression option by the processing cluster of the processor (e.g., processor 100) (e.g., Figure 1 The processing cluster 110 performs software-based decompression.

[0143] In at least one embodiment, in step 804, the processor identifies whether the system device is capable of hardware decompression (e.g., via API 300). In at least one embodiment, this identification includes an indication of which decompression algorithms (if any) the system device may perform.

[0144] In at least one embodiment, at step 806, a response from step 804 is received (e.g., via API 300) indicating whether the system device is capable of hardware decompression. In at least one embodiment, if hardware decompression is not possible due to device incompatibility ("No" at step 806), process 800 proceeds to step 808.

[0145] In at least one embodiment, in step 808, the processor uses software-based decompression as an auxiliary decompression option to decompress the compressed data. In at least one embodiment, the software-based decompression is performed using a processing cluster, streaming multiprocessor, or other processor cores.

[0146] In at least one embodiment, if hardware decompression is possible using the system device (Yes at step 806), process 800 proceeds to step 810. In at least one embodiment, in step 810, the response from step 804 (e.g., via API 300) indicates which decompression algorithms have been pre-programmed on the system device and are capable of execution. In at least one embodiment, these decompression algorithms will decompress the data using at least one of deflate compression, LZ4 compression, or Snappy compression. In at least one embodiment, if the received data is compressed using a compatible type that can be decompressed by the system device (Yes at step 810), process 800 proceeds to step 814.

[0147] In at least one embodiment, if the received data is compressed using an incompatible type (No at step 810), process 800 proceeds to step 808 or optionally to step 812. In at least one embodiment, if process 800 proceeds to step 808, the processor performs decompression on the received compressed data using software-based decompression. In at least one embodiment, this software-based decompression is performed using a processing cluster, streaming multiprocessor, or other processor core. In at least one embodiment, if process 800 proceeds to step 812, the processor performs a conversion to modify the compressed data to a compatible type identified in step 810. In at least one embodiment, after the compressed data is successfully converted to a compatible type, process 800 proceeds to step 814.

[0148] In at least one embodiment, in step 814, the processor identifies memory that can be used for decompression (e.g., via API 400 and / or 500), and then allocates the identified memory (e.g., via API 600) for use.

[0149] In at least one embodiment, in step 816, the processor performs decompression on the received compressed data. In at least one embodiment, decompression is invoked via an API (e.g., via API 700) and performed by hardware dedicated to decompression, such as a subset of PCE in a replication engine (e.g., ...). Figure 2B Decompress PCE 214 in the middle.

[0150] In at least one embodiment, in step 818, the processor stores the decompressed data in the memory allocated at step 814.

[0151] In at least one embodiment, this document relates to Figure 8Some or all of the described processes (or any other described processes, or variations and / or combinations thereof) can be executed under the control of one or more computer systems configured with executable instructions and / or other data, and can be implemented as executable instructions that execute jointly on one or more processors. In at least one embodiment, the executable instructions and / or other data can be stored on a non-transitory computer-readable storage medium (e.g., a computer program persistently stored on a magnetic, optical, or flash memory medium). In at least one embodiment, process 800 can be combined with reference to... Figure 1-2B The described structure or process can be executed, and the reference can be executed. Figure 3-7 and Figure 9 The described instructions or application programming interface (API) functions, or those that can be utilized by any suitable system, such as references... Figure 11-43 Described or executed Figure 11-43 The computing device for the process.

[0152] In at least one embodiment, Figure 8 The logic and / or processes can be integrated into Figure 1-7 and Figure 9 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 1-2B The logic / hardware structure within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, and / or 900. In at least one embodiment, Figure 8 The logic and / or processes can also be integrated into the system, processor, and architecture and / or executed. Figure 11-43 The process disclosed herein may be partially or entirely. In at least one embodiment, the process is performed. Figure 8 The disclosed API enables the processor to execute an application programming interface to decompress and store information in one or more storage locations specified by the user. In at least one embodiment, execution... Figure 8 The API disclosed in the document enables the circuit to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms.

[0153] Figure 9 This is a block diagram illustrating a driver and / or runtime comprising one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, software program 902 is stored in a processor (such as...) Figure 1 The software modules described herein. In at least one embodiment, software program 902 includes one or more software modules. In at least one embodiment, the software modules are as follows: Figure 1The following description is provided in a non-exclusive manner. In at least one embodiment, one or more APIs 910 are software instruction sets that, if executed, cause one or more processors to perform one or more computational operations. In at least one embodiment, one or more APIs 910 are distributed or otherwise provided as part of one or more libraries 906, runtimes 904, drivers, and / or any other software and / or executable code sets further described herein. In at least one embodiment, one or more APIs 910 perform one or more computational operations in response to a call to a software program 902. In at least one embodiment, the software program 902 is a collection of software code, commands, instructions, or other text sequences for instructing a computing device to perform one or more computational operations and / or to call one or more other instruction sets (e.g., APIs 910 or API functions 912) to be executed. In at least one embodiment, the functionality provided by one or more APIs 910 includes software functions 912, such as software functions that can be used to accelerate one or more portions of the software program 902 using one or more parallel processing units (PPUs) (e.g., graphics processing units (GPUs)). In at least one embodiment, the software program is a compiler.

[0154] In at least one embodiment, API 910 is a hardware interface of one or more circuits for performing one or more computational operations. In at least one embodiment, the one or more software APIs 910 described herein are implemented for performing combined... Figure 1-8 and Figure 10 The description refers to one or more circuits employing one or more techniques. In at least one embodiment, one or more software programs 902 include instructions that, when executed, cause one or more hardware devices and / or circuits to perform a combination. Figure 3-8 and Figure 10 Describing one or more technologies.

[0155] In at least one embodiment, software program 902 (e.g., user-implemented software program) utilizes one or more application programming interfaces (APIs) 910 to perform various computational operations, such as memory reservation, matrix multiplication, arithmetic operations, or any computational operation performed by a parallel processing unit (PPU) (e.g., a graphics processing unit (GPU)), as further described herein. In at least one embodiment, one or more APIs 910 provide a set of callable functions 912 (referred to herein as APIs, API functions, and / or functions), which can each perform one or more computational operations, such as computational operations related to parallel computing. In at least one embodiment, one or more APIs 910 provide functions 912 to execute 916 application programming interfaces to decompress information and store it in one or more storage locations indicated by the user.

[0156] In at least one embodiment, one or more software programs 902 interact with or otherwise communicate with one or more APIs 910 to perform one or more computational operations using one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more computational operations using one or more PPUs include at least one or more sets of computational operations that will be accelerated by being executed at least partially by said one or more PPUs. In at least one embodiment, one or more software programs 902 interact with one or more APIs 910 to facilitate parallel computing using remote or local interfaces.

[0157] In at least one embodiment, the interface is software instructions that, if executed, provide access to one or more functions 912 provided by one or more APIs 910. In at least one embodiment, when a software developer compiles one or more software programs 902 in conjunction with one or more libraries 906 that include one or more APIs 910 or otherwise provide access to one or more APIs 910, the software program 902 uses a native interface. In at least one embodiment, one or more software programs 902 are statically compiled in conjunction with precompiled libraries 906 or uncompiled source code including instructions for executing one or more APIs 910. In at least one embodiment, one or more software programs 902 are dynamically compiled, and the one or more software programs are linked to one or more precompiled libraries 906 that include one or more APIs 910 using a linker.

[0158] In at least one embodiment, when a software developer executes a software program that communicates with a library 906 including one or more APIs 910, or otherwise via a network or other remote communication medium, the software program 902 uses a remote interface. In at least one embodiment, the library 906 including one or more APIs 910 is executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, the library 906 including one or more APIs 910 is executed by any other computing host that provides the one or more APIs 910 to the software program 902.

[0159] In at least one embodiment, one or more software programs 902 use one or more APIs 910 to allocate and otherwise manage memory to be used by the software program 902. In at least one embodiment, one or more software programs 902 use one or more APIs 910 to allocate and otherwise manage memory to be used by one or more portions of the software program 902 that will be accelerated using one or more PPUs (e.g., GPUs) or any other accelerators or processors further described herein. These software programs 902 select which of the one or more portions to deactivate during the training of the one or more neural networks, based at least in part on whether the one or more portions of the one or more neural networks will be used after training them.

[0160] In at least one embodiment, API 910 is an API for facilitating parallel computing. In at least one embodiment, API 910 is any other API further described herein. In at least one embodiment, API 910 is provided by a driver and / or runtime 904. In at least one embodiment, API 910 is provided by a CUDA user-mode driver. In at least one embodiment, API 910 is provided by a CUDA runtime. In at least one embodiment, the driver is data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 912 of API 910 during the loading and execution of one or more portions of software program 902. In at least one embodiment, runtime 904 is data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 912 of API 910 during the execution of software program 902. In at least one embodiment, one or more software programs 902 utilize one or more APIs 910 implemented or otherwise provided by a driver and / or runtime 904 to perform combined arithmetic operations by the one or more software programs 902 during execution by one or more PPUs (e.g., GPUs).

[0161] In at least one embodiment, one or more software programs 902 utilize one or more APIs 910 provided by a driver and / or runtime 904 to perform combinatorial arithmetic operations on one or more PPUs (e.g., GPUs). In at least one embodiment, one or more APIs 910 provide combinatorial arithmetic operations via a driver and / or runtime 904, as described above. In at least one embodiment, one or more software programs 902 utilize one or more APIs 910 provided by a driver and / or runtime 904 to allocate or otherwise reserve one or more blocks of memory 914 for one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 902 utilize one or more APIs 910 provided by a driver and / or runtime 904 to allocate or otherwise reserve blocks of memory. In at least one embodiment, one or more APIs 910 are used to perform decompression operations, as incorporated herein by reference. Figure 1-8 and Figure 10 As stated above.

[0162] To improve the usability of software program 902 and / or optimize one or more portions of software program 902 for acceleration by one or more PPUs (e.g., GPUs), in one embodiment, one or more APIs 910 provide one or more API functions 912 to execute decompression instructions 916, so that information is decompressed and stored in one or more storage locations indicated by the user, as described above and in combination with... Figure 1-8 and Figure 10 Further described. In at least one embodiment, exemplary block diagram 900 depicts a processor including one or more circuitry for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, exemplary block diagram 900 depicts a system including one or more processors for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, the API is used to identify one or more expected software outputs for comparison with one or more other software outputs to be generated by the software.

[0163] In at least one embodiment, Figure 9 The logic and / or procedures in can be integrated into Figure 1-8 and Figure 10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 1-2B The logic / hardware structure within can execute at least some or all of the processes or APIs 300, 400, 500, 600, 700, 800, and / or 900. In at least one embodiment, Figure 9 The logic and / or processes within can also be integrated into the system, processor, and architecture, and / or executed. Figure 11-43 The process disclosed herein may be partially or entirely. In at least one embodiment, the process is performed. Figure 9 The disclosed API enables the processor to execute an application programming interface to decompress and store information in one or more storage locations specified by the user. In at least one embodiment, execution... Figure 9 The API disclosed in the document enables the circuit to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms.

[0164] Figure 10 This is a block diagram illustrating a driver and / or runtime comprising one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, software program 1002 is stored on a processor (such as...) Figure 1The software modules described herein. In at least one embodiment, software program 1002 includes one or more software modules. In at least one embodiment, the software modules are as follows: Figure 1 The following description is provided in a non-exclusive manner. In at least one embodiment, one or more APIs 1010 are software instruction sets that, if executed, cause one or more processors to perform one or more computational operations. In at least one embodiment, one or more APIs 1010 are distributed or otherwise provided as part of one or more libraries 1006, runtimes 1004, drivers, and / or any other software and / or executable code sets further described herein. In at least one embodiment, one or more APIs 1010 perform one or more computational operations in response to a call to software program 1002. In at least one embodiment, software program 1002 is a collection of software code, commands, instructions, or other text sequences for instructing a computing device to perform one or more computational operations and / or to invoke one or more other instruction sets (e.g., API 1010 or API function 1012) to be executed. In at least one embodiment, the functionality provided by one or more APIs 1010 includes software functions 1012, such as software functions that can be used to accelerate one or more portions of software program 1002 using one or more parallel processing units (PPUs) (e.g., graphics processing units (GPUs)). In at least one embodiment, the software program is a compiler.

[0165] In at least one embodiment, API 1010 is a hardware interface of one or more circuits for performing one or more computational operations. In at least one embodiment, one or more software APIs 1010 described herein are implemented for performing combined... Figure 1-9 The description refers to one or more circuits employing one or more techniques. In at least one embodiment, one or more software programs 1002 include instructions that, when executed, cause one or more hardware devices and / or circuits to perform combined... Figure 3-9 Describing one or more technologies.

[0166] In at least one embodiment, software program 1002 (e.g., user-implemented software program) utilizes one or more application programming interfaces (APIs) 1010 to perform various computational operations, such as memory reservation, matrix multiplication, arithmetic operations, or any computational operation performed by a parallel processing unit (PPU) (e.g., a graphics processing unit (GPU)), as further described herein. In at least one embodiment, one or more APIs 1010 provide a set of callable functions 1012 (referred to herein as APIs, API functions, and / or functions), each of which performs one or more computational operations, such as computational operations related to parallel computing. In at least one embodiment, one or more APIs 1010 provide functions 1012 to cause one or more circuits 1016 to execute instructions such that information is decompressed based at least in part on one or more instructions of one or more decompression algorithms.

[0167] In at least one embodiment, one or more software programs 1002 interact with or otherwise communicate with one or more APIs 1010 to perform one or more computational operations using one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more computational operations using one or more PPUs include at least one or more sets of computational operations that will be accelerated by being executed at least partially by said one or more PPUs. In at least one embodiment, one or more software programs 1002 interact with one or more APIs 1010 to facilitate parallel computing using remote or local interfaces.

[0168] In at least one embodiment, the interface is software instructions that, if executed, provide access to one or more functions 1012 provided by one or more APIs 1010. In at least one embodiment, when a software developer compiles one or more software programs 1002 in conjunction with one or more libraries 1006 that include one or more APIs 1010 or otherwise provide access to one or more APIs 1010, the software program 1002 uses the native interface. In at least one embodiment, one or more software programs 1002 are statically compiled in conjunction with pre-compiled libraries 1006 or uncompiled source code including instructions for executing one or more APIs 1010. In at least one embodiment, one or more software programs 1002 are dynamically compiled, and the one or more software programs are linked to one or more pre-compiled libraries 1006 that include one or more APIs 1010 using a linker.

[0169] In at least one embodiment, when a software developer executes a software program that communicates with a library 1006 including one or more APIs 1010, or otherwise via a network or other remote communication medium, the software program 1002 uses a remote interface. In at least one embodiment, the library 1006 including one or more APIs 1010 is executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, the library 1006 including one or more APIs 1010 is executed by any other computing host that provides the one or more APIs 1010 to the software program 1002.

[0170] In at least one embodiment, one or more software programs 1002 use one or more APIs 1010 to allocate and otherwise manage memory to be used by the software program 1002. In at least one embodiment, one or more software programs 1002 use one or more APIs 1010 to allocate and otherwise manage memory to be used by one or more portions of the software program 1002 that will be accelerated using one or more PPUs (e.g., GPUs) or any other accelerators or processors further described herein. These software programs 1002 select which of the one or more portions to deactivate during the training of the one or more neural networks, based at least in part on whether the one or more portions of the one or more neural networks will be used after training them.

[0171] In at least one embodiment, API 1010 is an API for facilitating parallel computing. In at least one embodiment, API 1010 is any other API further described herein. In at least one embodiment, API 1010 is provided by a driver and / or runtime 1004. In at least one embodiment, API 1010 is provided by a CUDA user-mode driver. In at least one embodiment, API 1010 is provided by a CUDA runtime. In at least one embodiment, the driver is a data value and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 1012 of API 1010 during the loading and execution of one or more portions of software program 1002. In at least one embodiment, runtime 1004 is a data value and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 1012 of API 1010 during the execution of software program 1002. In at least one embodiment, one or more software programs 1002 utilize one or more APIs 1010 implemented by a driver and / or runtime 1004 or otherwise provided to perform combined arithmetic operations by the one or more software programs 1002 during execution by one or more PPUs (e.g., GPUs).

[0172] In at least one embodiment, one or more software programs 1002 utilize one or more APIs 1010 provided by a driver and / or runtime 1004 to perform combined arithmetic operations on one or more PPUs (e.g., GPUs). In at least one embodiment, one or more APIs 1010 provide combined arithmetic operations via a driver and / or runtime 1004, as described above. In at least one embodiment, one or more software programs 1002 utilize one or more APIs 1010 provided by a driver and / or runtime 1004 to allocate or otherwise reserve one or more blocks of memory 1014 for one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 1002 utilize one or more APIs 1010 provided by a driver and / or runtime 1004 to allocate or otherwise reserve blocks of memory. In at least one embodiment, one or more APIs 1010 are used to perform decompression operations, as incorporated herein by reference. Figure 1-9 As stated above.

[0173] To improve the usability of software program 1002 and / or optimize one or more portions of software program 1002 that will be accelerated by one or more PPUs (e.g., GPUs), in one embodiment, one or more APIs 1010 provide one or more API functions 1012 to cause one or more circuits 1016 to execute instructions to decompress information at least in part based on one or more instructions of one or more decompression algorithms, as described above and in combination. Figure 1-9 Further description. In at least one embodiment, exemplary block diagram 1000 depicts a processor including one or more circuitry for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, exemplary block diagram 1000 depicts a system including one or more processors for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, the API is used to identify one or more expected software outputs for comparison with one or more other software outputs generated by the software.

[0174] In at least one embodiment, Figure 10 The logic and / or procedures in can be integrated into Figure 1-9 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 1-2B The logic / hardware structure within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, and / or 1000. In at least one embodiment, Figure 10 The logic and / or processes within can also be integrated into the system, processor, and architecture, and / or executed. Figure 11-43 The process disclosed herein may be partially or entirely. In at least one embodiment, the process is performed. Figure 10 The disclosed API enables the processor to execute an application programming interface, thereby decompressing information and storing it in one or more storage locations specified by the user. In at least one embodiment, execution... Figure 10 The publicly disclosed API enables the circuit to execute instructions that allow information to be decompressed, at least in part, based on one or more instructions of one or more decompression algorithms.

[0175] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, those skilled in the art will appreciate that the concepts of the invention can be practiced without one or more of these specific details.

[0176] Data Center

[0177] Figure 11An exemplary data center 1100 according to at least one embodiment is shown. In at least one embodiment, the data center 1100 includes, but is not limited to, a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0178] In at least one embodiment, such as Figure 11 As shown, the data center infrastructure layer 1110 may include a resource coordinator 1112, grouped computing resources 1114, and node computing resources (“nodes CR”) 1116(1)-1116(N), where “N” represents any complete positive integer. In at least one embodiment, nodes CR 1116(1)-1116(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (“FPGAs”), data processing units (“DPUs”) in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 1116(1)-1116(N) may be servers having one or more of the aforementioned computing resources.

[0179] In at least one embodiment, the grouped computing resources 1114 may include individual groups (not shown) of node CRs housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographical locations. The individual groups of node CRs within the grouped computing resources 1114 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0180] In at least one embodiment, resource coordinator 1112 may be configured or otherwise control one or more nodes CR1116(1)-1116(N) and / or grouped computing resources 1114. In at least one embodiment, resource coordinator 1112 may include a Software Design Infrastructure (“SDI”) management entity for data center 1100. In at least one embodiment, resource coordinator 1112 may include hardware, software, or some combination thereof.

[0181] In at least one embodiment, such as Figure 11 As shown, framework layer 1120 includes, but is not limited to, job scheduler 1132, configuration manager 1134, resource manager 1136, and distributed file system 1138. In at least one embodiment, framework layer 1120 may include a framework of software 1152 supporting software layer 1130 and / or one or more applications 1142 supporting application layer 1140. In at least one embodiment, software 1152 or application 1142 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1120 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark") which can utilize distributed file system 1138 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 1132 may include Spark drivers to facilitate the scheduling of workloads supported by the various layers of data center 1100. In at least one embodiment, configuration manager 1134 may be able to configure different layers, such as software layer 1130 and framework layer 1120 including Spark and distributed file system 1138 for supporting large-scale data processing. In at least one embodiment, resource manager 1136 is able to manage cluster or group computing resources mapped to or allocated to support distributed file system 1138 and job scheduler 1132. In at least one embodiment, cluster or group computing resources may include grouped computing resources 1114 on data center infrastructure layer 1110. In at least one embodiment, resource manager 1136 may coordinate with resource coordinator 1112 to manage these mapped or allocated computing resources.

[0182] In at least one embodiment, the software 1152 included in software layer 1130 may include software used by at least a portion of nodes CR1116(1)-1116(N), grouped computing resources 1114, and / or the distributed file system 1138 of framework layer 1120. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0183] In at least one embodiment, one or more applications 1142 included in application layer 1140 may include one or more types of applications used by at least a portion of nodes CR1116(1)-1116(N), grouped computing resources 1114, and / or the distributed file system 1138 of framework layer 1120. One or more types of applications may include, but are not limited to, CUDA applications.

[0184] In at least one embodiment, any of the configuration manager 1134, resource manager 1136, and resource coordinator 1112 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 1100 and can prevent underutilization and / or poor performance of the data center.

[0185] Figure 11 The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 11 The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figure 11 The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figure 11 The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figure 11 The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figure 11 The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0186] Computer-based systems

[0187] The following figures present, but are not limited to, exemplary computer-based systems that can be used to implement at least one embodiment.

[0188] Figure 12A processing system 1200 according to at least one embodiment is illustrated. In at least one embodiment, the system 1200 includes one or more processors 1202 and one or more graphics processors 1208, and may be a single-processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 1202 or processor cores 1207. In at least one embodiment, the processing system 1200 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices. In at least one embodiment, the processor core 1207 is referred to as a computing unit or arithmetic unit.

[0189] In at least one embodiment, the processing system 1200 may include or be integrated into a server-based gaming platform, including a game console, mobile game console, handheld game console, or online game console, which are game and media consoles. In at least one embodiment, the processing system 1200 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, the processing system 1200 may also include components coupled to or integrated into a wearable device, such as a smartwatch wearable device, smart glasses device, augmented reality device, or virtual reality device. In at least one embodiment, the processing system 1200 is a television or set-top box device having one or more processors 1202 and a graphical interface generated by one or more graphics processors 1208.

[0190] In at least one embodiment, each of the one or more processors 1202 includes one or more processor cores 1207 for processing instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 1207 is configured to process a specific instruction set 1209. In at least one embodiment, the instruction set 1209 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, the plurality of processor cores 1207 may each process a different instruction set 1209, which may include instructions that facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 1207 may also include other processing devices, such as digital signal processors (DSPs).

[0191] In at least one embodiment, processor 1202 includes cache memory 1204. In at least one embodiment, processor 1202 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 1202. In at least one embodiment, processor 1202 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 1207 using known cache coherence techniques. In at least one embodiment, processor 1202 further includes a register file 1206, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 1206 may include general-purpose registers or other registers.

[0192] In at least one embodiment, one or more processors 1202 are coupled to one or more interface buses 1210 to transmit communication signals, such as address, data, or control signals, between the processor 1202 and other components in the system 1200. In at least one embodiment, the interface bus 1210 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 1210 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 1202 includes an integrated memory controller 1216 and a platform controller hub 1230. In at least one embodiment, the memory controller 1216 facilitates communication between storage devices and other components of the processing system 1200, while the platform controller hub (PCH) 1230 provides connectivity to input / output (I / O) devices via a local I / O bus. In at least one embodiment, one or more peripheral component interconnect buses include PCIe Gen 5, which provides an interface for the processor.

[0193] In at least one embodiment, storage device 1220 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or a device with suitable performance for use as processor memory. In at least one embodiment, storage device 1220 may be used as system memory of processing system 1200 to store data 1222 and instructions 1221 for use when one or more processors 1202 execute an application or process. In at least one embodiment, memory controller 1216 is also coupled to an optional external graphics processor 1212, which may communicate with one or more graphics processors 1208 of processor 1202 to perform graph and media operations. In at least one embodiment, display device 1211 may be connected to processor 1202. In at least one embodiment, display device 1211 may include one or more internal display devices, such as those in mobile electronic devices or portable computer devices, or external display devices connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 1211 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0194] In at least one embodiment, the platform controller hub 1230 enables peripheral devices to connect to the storage device 1220 and the processor 1202 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 1246, a network controller 1234, a firmware interface 1228, a wireless transceiver 1226, a touch sensor 1225, and a data storage device 1224 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 1224 may be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1225 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1226 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 1228 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 1234 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 1210. In at least one embodiment, audio controller 1246 is a multi-channel high-definition audio controller. In at least one embodiment, processing system 1200 includes an optional legacy I / O controller 1240 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to processing system 1200. In at least one embodiment, platform controller hub 1230 may also be connected to one or more Universal Serial Bus (USB) controllers 1242 that connect input devices, such as a keyboard and mouse combination 1243, a camera 1244, or other USB input devices.

[0195] In at least one embodiment, instances of the memory controller 1216 and platform controller hub 1230 may be integrated into a discrete external graphics processor, such as external graphics processor 1212. In at least one embodiment, the platform controller hub 1230 and / or the memory controller 1216 may be external to one or more processors 1202. For example, in at least one embodiment, the processing system 1200 may include an external memory controller 1216 and a platform controller hub 1230, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset communicating with the processor 1202.

[0196] Figure 12 The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 12The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figure 12 The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figure 12 The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figure 12 The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figure 12 The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0197] Figure 13 A computer system 1300 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1300 may be a system having interconnected devices and components, a System-on-a-Chip (SoC), or some combination thereof. In at least one embodiment, the computer system 1300 is formed by a processor 1302, which may include execution units for executing instructions. In at least one embodiment, the computer system 1300 may include, but is not limited to, components such as the processor 1302, which employs execution units including logic to execute algorithms for process data. In at least one embodiment, the computer system 1300 may include a processor, such as one available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM A microprocessor may be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, computer system 1300 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0198] In at least one embodiment, the computer system 1300 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of executing one or more instructions according to at least one embodiment.

[0199] In at least one embodiment, the computer system 1300 may include, but is not limited to, a processor 1302, which may include, but is not limited to, one or more execution units 1308 configured to execute a Computational Unified Device Architecture (“CUDA”). (Developed by NVIDIA Corporation, Santa Clara, California) In at least one embodiment, the CUDA program is at least a part of a software application written in the CUDA programming language. In at least one embodiment, the computer system 1300 is a single-processor desktop or server system. In at least one embodiment, the computer system 1300 may be a multiprocessor system. In at least one embodiment, the processor 1302 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing instruction set combinations, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1302 may be coupled to a processor bus 1310, which can transmit data signals between the processor 1302 and other components in the computer system 1300.

[0200] In at least one embodiment, processor 1302 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1304. In at least one embodiment, processor 1302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1302. In at least one embodiment, processor 1302 may include a combination of internal and external caches. In at least one embodiment, register file 1306 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0201] In at least one embodiment, an execution unit 1308, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 1302. The processor 1302 may also include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, the execution unit 1308 may include logic for processing a packaged instruction set 1309. In at least one embodiment, by including the packaged instruction set 1309 in the instruction set of the general-purpose processor 1302, along with the associated circuitry for executing the instructions, packaged data in the general-purpose processor 1302 can be used to perform operations used by many multimedia applications. In at least one embodiment, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor's data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on a data element at a time.

[0202] In at least one embodiment, the execution unit 1308 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, the computer system 1300 may include, but is not limited to, the memory 1320. In at least one embodiment, the memory 1320 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. The memory 1320 may store instructions 1319 and / or data 1321 represented by data signals that can be executed by the processor 1302.

[0203] In at least one embodiment, the system logic chip may be coupled to the processor bus 1310 and the memory 1320. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1316, and the processor 1302 may communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 may provide a high-bandwidth memory path 1318 to the memory 1320 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1316 may initiate data signals between the processor 1302, the memory 1320, and other components in the computer system 1300, and bridge data signals between the processor bus 1310, the memory 1320, and the system I / O 1322.

[0204] In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1316 may be coupled to memory 1320 via high-bandwidth memory path 1318, and the graphics / video card 1312 may be coupled to the MCH 1316 via Accelerated Graphics Port (“AGP”) interconnect 1314.

[0205] In at least one embodiment, computer system 1300 may use system I / O 1322 as a proprietary hub interface bus to couple MCH 1316 to I / O controller hub (“ICH”) 1330. In at least one embodiment, ICH 1330 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1320, chipset, and processor 1302. Examples may include, but are not limited to, an audio controller 1329, a firmware hub (“Flash BIOS”) 1328, a wireless transceiver 1326, data storage 1324, a conventional I / O controller 1323 and keyboard interface including user input 1325, a serial expansion port 1327 (e.g., USB), and a network controller 1334. Data storage 1324 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0206] In at least one embodiment, Figure 13 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Figure 13 An exemplary SoC can be shown. In at least one embodiment, Figure 13 The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1300 are interconnected using a Compute Fast Link (CXL) interconnect.

[0207] Figure 13 The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 13 The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figure 13The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figure 13 The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figure 13 The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figure 13The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0208] Figure 14 A system 1400 according to at least one embodiment is illustrated. In at least one embodiment, system 1400 is an electronic device utilizing processor 1410. In at least one embodiment, system 1400 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, edge device communicatively coupled to one or more locations or cloud service providers, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0209] In at least one embodiment, system 1400 may include, but is not limited to, processor 1410 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1410 is coupled using a bus or interface, such as I... 2 C-bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Accessory (“SATA”) bus, USB (versions 1, 2, and 3) or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 14 A system is illustrated, comprising interconnected hardware devices or "chips". In at least one embodiment, Figure 14 An exemplary SoC can be shown. In at least one embodiment, Figure 14 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 14 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0210] In at least one embodiment, Figure 14This may include a display 1424, a touchscreen 1425, a touchpad 1430, a near-field communication unit (“NFC”) 1445, a sensor hub 1440, a thermal sensor 1446, a fast chipset (“EC”) 1435, a trusted platform module (“TPM”) 1438, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1422, a DSP 1460, a solid-state drive (“SSD”) or hard disk drive (“HDD”) 1420, a wireless local area network unit (“WLAN”) 1450, a Bluetooth unit 1452, a wireless wide area network unit (“WWAN”) 1456, a global positioning system (GPS) 1455, a camera (“USB 3.0 camera”) 1454 (e.g., a USB 3.0 camera), or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1415 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0211] In at least one embodiment, other components may be communicatively coupled to processor 1410 via the components discussed above. In at least one embodiment, accelerometer 1441, ambient light sensor (“ALS”) 1442, compass 1443, and gyroscope 1444 may be communicatively coupled to sensor hub 1440. In at least one embodiment, thermal sensor 1439, fan 1437, keyboard 1446, and touchpad 1430 may be communicatively coupled to EC 1435. In at least one embodiment, speaker 1463, earphone 1464, and microphone (“mic”) 1465 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1464, which in turn may be communicatively coupled to DSP 1460. In at least one embodiment, audio unit 1464 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1457 may be communicatively coupled to WWAN unit 1456. In at least one embodiment, components such as WLAN unit 1450, Bluetooth unit 1452, and WWAN unit 1456 can be implemented as next-generation form factor (NGFF).

[0212] Figure 14 The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 14 The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figure 14The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figure 14 The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figure 14 The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figure 14The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0213] Figure 15 An exemplary integrated circuit 1500 according to at least one embodiment is illustrated. In at least one embodiment, the exemplary integrated circuit 1500 is a SoC (System-on-a-Chip) that can be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 1500 includes one or more application processors 1505 (e.g., CPU, DPU), at least one graphics processor 1510, and may additionally include an image processor 1515 and / or a video processor 1520, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1500 includes peripheral or bus logic, which includes a USB controller 1525, a UART controller 1530, an SPI / SDIO controller 1535, and an I... 2 S / I 2 C controller 1540. In at least one embodiment, integrated circuit 1500 may include display device 1545 coupled to one or more of high-definition multimedia interface (HDMI) controller 1550 and mobile industrial processor interface (MIPI) display interface 1555. In at least one embodiment, storage may be provided by flash memory subsystem 1560, including flash memory and flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 1565 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include embedded security engine 1570.

[0214] Figure 15 The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 15 The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figure 15 The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figure 15 The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figure 15 The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figure 15 The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0215] Figure 16A computing system 1600 according to at least one embodiment is illustrated. In at least one embodiment, the computing system 1600 includes a processing subsystem 1601 having one or more processors 1602 and a system memory 1604 communicating via an interconnect path that may include a memory hub 1605. In at least one embodiment, the memory hub 1605 may be a separate component within a chipset assembly or may be integrated within one or more processors 1602. In at least one embodiment, the memory hub 1605 is coupled to an I / O subsystem 1611 via a communication link 1606. In at least one embodiment, the I / O subsystem 1611 includes an I / O hub 1607 that enables the computing system 1600 to receive input from one or more input devices 1608. In at least one embodiment, the I / O hub 1607 may enable a display controller, which is included in one or more processors 1602, for providing output to one or more display devices 1610A. In at least one embodiment, one or more display devices 1610A coupled to the I / O hub 1607 may include local, internal, or embedded display devices.

[0216] In at least one embodiment, the processing subsystem 1601 includes one or more parallel processors 1612 coupled to a memory hub 1605 via a bus or other communication link 1613. In at least one embodiment, the communication link 1613 may be one of many standards-based communication link technologies or protocols, such as, but not limited to, PCIe, or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, the one or more parallel processors 1612 form a compute-intensive parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as multi-core processors or computing units. In at least one embodiment, the one or more parallel processors 1612 form a graphics processing subsystem capable of outputting pixels to one or more display devices 1610A coupled via an I / O hub 1607. In at least one embodiment, the one or more parallel processors 1612 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1610B.

[0217] In at least one embodiment, system storage unit 1614 may be connected to I / O hub 1607 to provide a storage mechanism for computing system 1600. In at least one embodiment, I / O switch 1616 may be used to provide an interface mechanism to enable connectivity between I / O hub 1607 and other components, such as network adapter 1618 and / or wireless network adapter 1619 that may be integrated into the platform, and various other devices that may be added via one or more additional devices 1620. In at least one embodiment, network adapter 1618 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1619 may include one or more Wi-Fi, Bluetooth, NFC, or other network devices comprising one or more radios.

[0218] In at least one embodiment, the computing system 1600 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., and may also be connected to the I / O hub 1607. In at least one embodiment, for Figure 16 The communication paths that interconnect the various components can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocols).

[0219] In at least one embodiment, one or more parallel processors 1612 include circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1612 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computing system 1600 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1612, memory hub 1605, processor 1602, and I / O hub 1607 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computing system 1600 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1600 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computing system. In at least one embodiment, the I / O subsystem 1611 and display device 1610B are omitted from the computing system 1600. In at least one embodiment, one or more parallel processors 1612 include one or more tensor memory accelerator (TMA) units that can transfer data blocks between global memory and shared memory. In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, such as from global memory to shared memory and vice versa.

[0220] Figure 16 The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 16 The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figure 16 The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figure 16 The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figure 16 The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figure 16 The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0221] Processing system

[0222] The following figures illustrate, but are not limited to, exemplary processing systems that can be used to implement at least one embodiment.

[0223] Figure 17An accelerated processing unit (“APU”) 1700 according to at least one embodiment is illustrated. In at least one embodiment, the APU 1700 was developed by AMD Inc. of Santa Clara, California. In at least one embodiment, the APU 1700 can be configured to execute applications, such as CUDA programs. In at least one embodiment, the APU 1700 includes, but is not limited to, a core complex 1710, a graphics complex 1740, an architecture 1760, an I / O interface 1770, a memory controller 1780, a display controller 1792, and a multimedia engine 1794. In at least one embodiment, the APU 1700 can be, but is not limited to, any combination of any number of core complexes 1710, any number of graphics complexes 1740, any number of display controllers 1792, and any number of multimedia engines 1794. For illustrative purposes, multiple instances of similar objects are indicated herein by reference numerals, wherein the reference numerals identify the object, and the numbers in parentheses identify the desired instances.

[0224] In at least one embodiment, the core complex 1710 is a CPU, the graphics complex 1740 is a GPU, and the APU 1700 is a processing unit that is not limited to 1710 and 1740 integrated onto a single chip. In at least one embodiment, some tasks may be assigned to the core complex 1710, while other tasks may be assigned to the graphics complex 1740. In at least one embodiment, the core complex 1710 is configured to execute master control software associated with the APU 1700, such as an operating system. In at least one embodiment, the core complex 1710 is the master processor of the APU 1700, which controls and coordinates the operation of other processors. In at least one embodiment, the core complex 1710 issues commands to control the operation of the graphics complex 1740. In at least one embodiment, the core complex 1710 may be configured to execute host executable code derived from CUDA source code, and the graphics complex 1740 may be configured to execute device executable code derived from CUDA source code.

[0225] In at least one embodiment, the core complex 1710 includes, but is not limited to, cores 1720(1)-1720(4) and L3 cache 1730. In at least one embodiment, the core complex 1710 may include, but is not limited to, any combination of any number of cores 1720 and any number and type of cache. In at least one embodiment, the cores 1720 are configured to execute instructions of a specific instruction set architecture (“ISA”). In at least one embodiment, each core 1720 is a CPU core. In at least one embodiment, the core 1720 is referred to as a compute unit or arithmetic unit.

[0226] In at least one embodiment, each core 1720 includes, but is not limited to, a fetch / decode unit 1722, an integer execution engine 1724, a floating-point execution engine 1726, and an L2 cache 1728. In at least one embodiment, the fetch / decode unit 1722 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 1724 and the floating-point execution engine 1726. In at least one embodiment, the fetch / decode unit 1722 may simultaneously dispatch one micro-instruction to the integer execution engine 1724 and another micro-instruction to the floating-point execution engine 1726. In at least one embodiment, the integer execution engine 1724 performs operations not limited to integer and memory operations. In at least one embodiment, the floating-point engine 1726 performs operations not limited to floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1722 dispatches micro-instructions to a single execution engine, which replaces both the integer execution engine 1724 and the floating-point execution engine 1726.

[0227] In at least one embodiment, each core 1720(i) can access an L2 cache 1728(i) included in core 1720(i), where i is an integer representing a specific instance of core 1720. In at least one embodiment, each core 1720 included in core complex 1710(j) is connected to other cores 1720 included in core complex 1710(j) via an L3 cache 1730(j) included in core complex 1710(j), where j is an integer representing a specific instance of core complex 1710. In at least one embodiment, a core 1720 included in core complex 1710(j) can access all L3 caches 1730(j) included in core complex 1710(j), where j is an integer representing a specific instance of core complex 1710. In at least one embodiment, the L3 cache 1730 may include, but is not limited to, any number of slices.

[0228] In at least one embodiment, the graphics complex 1740 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the graphics complex 1740 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the graphics complex 1740 is configured to perform graphics-independent operations. In at least one embodiment, the graphics complex 1740 is configured to perform both graphics-related and graphics-independent operations.

[0229] In at least one embodiment, the graphics complex 1740 includes, but is not limited to, any number of computing units 1750 and an L2 cache 1742. In at least one embodiment, the computing units 1750 share the L2 cache 1742. In at least one embodiment, the L2 cache 1742 is partitioned. In at least one embodiment, the graphics complex 1740 includes, but is not limited to, any number of computing units 1750 and any number (including zero) and type of cache. In at least one embodiment, the graphics complex 1740 includes, but is not limited to, any number of dedicated graphics hardware.

[0230] In at least one embodiment, each computing unit 1750 includes, but is not limited to, any number of SIMD units 1752 and shared memory 1754. In at least one embodiment, each SIMD unit 1752 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each computing unit 1750 may execute any number of thread blocks, but each thread block executes on a single computing unit 1750. In at least one embodiment, a thread block includes, but is not limited to, any number of execution threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1752 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process different datasets based on a single instruction set. In at least one embodiment, prediction can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 1754. In at least one embodiment, each computing unit 1750 includes one or more thread block clusters, wherein the thread block clusters can provide local programming control at a larger granularity than a single thread block of a single streaming multiprocessor (SM). In at least one embodiment, the thread block cluster (also referred to as a “cluster”) enables multiple thread blocks running concurrently across a streaming multiprocessor to synchronously and cooperatively acquire, exchange, or otherwise use data.

[0231] In at least one embodiment, structure 1760 is a system interconnect that facilitates data and control transfers across core complex 1710, graphics complex 1740, I / O interface 1770, memory controller 1780, display controller 1792, and multimedia engine 1794. In at least one embodiment, in addition to or instead of structure 1760, APU 1700 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of components that may be directly or indirectly linked, either internally or externally to APU 1700. In at least one embodiment, I / O interface 1770 represents any number and type of I / O interface (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1770. In at least one embodiment, the peripheral device coupled to the I / O interface 1770 may include, but is not limited to, a keyboard, mouse, printer, scanner, joystick or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0232] In at least one embodiment, the display controller 1792 displays images on one or more display devices (e.g., liquid crystal display (LCD) devices). In at least one embodiment, the multimedia engine 1794 includes, but is not limited to, any number and type of multimedia-related circuitry, such as video decoders, video encoders, image signal processors, etc. In at least one embodiment, the memory controller 1780 facilitates data transfer between the APU 1700 and the unified system memory 1790. In at least one embodiment, the core complex 1710 and the graphics complex 1740 share the unified system memory 1790.

[0233] In at least one embodiment, the APU 1700 implements a memory subsystem, including but not limited to any number and type of memory controllers 1780 and memory devices (e.g., shared memory 1754) that can be dedicated to a single component or shared among multiple components. In at least one embodiment, the APU 1700 implements a cache subsystem, including but not limited to one or more cache memories (e.g., L2 cache 1828, L3 cache 1730, and L2 cache 1742), each cache memory being component-private or shared among any number of components (e.g., core 1720, core complex 1710, SIMD unit 1752, compute unit 1750, and graphics complex 1740).

[0234] Figure 17 The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 17 The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figure 17 The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figure 17 The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figure 17 The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figure 17 The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0235] Figure 18 A CPU 1800 according to at least one embodiment is illustrated. In at least one embodiment, the CPU 1800 was developed by AMD Inc. of Santa Clara, California. In at least one embodiment, the CPU 1800 can be configured to execute an application. In at least one embodiment, the CPU 1800 is configured to execute host control software, such as an operating system. In at least one embodiment, the CPU 1800 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1800 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1800 includes, but is not limited to, any number of core complexes 1810, architectures 1860, I / O interfaces 1870, and memory controllers AMAD80.

[0236] In at least one embodiment, the core complex 1810 includes, but is not limited to, cores 1820(1)-1820(4) and L3 cache 1830. In at least one embodiment, the core complex 1810 may include, but is not limited to, any combination of any number of cores 1820 and any number and type of cache. In at least one embodiment, the cores 1820 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 1820 is a CPU core.

[0237] In at least one embodiment, each core 1820 includes, but is not limited to, a fetch / decode unit 1822, an integer execution engine 1824, a floating-point execution engine 1826, and an L2 cache 1828. In at least one embodiment, the fetch / decode unit 1822 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 1824 and the floating-point execution engine 1826. In at least one embodiment, the fetch / decode unit 1822 may simultaneously dispatch one micro-instruction to the integer execution engine 1824 and another micro-instruction to the floating-point execution engine 1826. In at least one embodiment, the integer execution engine 1824 performs operations not limited to integer and memory operations. In at least one embodiment, the floating-point engine 1826 performs operations not limited to floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1822 dispatches micro-instructions to a single execution engine, which replaces both the integer execution engine 1824 and the floating-point execution engine 1826.

[0238] In at least one embodiment, each core 1820(i) can access an L2 cache 1828(i) included in core 1820(i), where i is an integer representing a specific instance of core 1820. In at least one embodiment, each core 1820 included in core complex 1810(j) is connected to other cores 1820 in core complex 1810(j) via an L3 cache 1830(j) included in core complex 1810(j), where j is an integer representing a specific instance of core complex 1810. In at least one embodiment, a core 1820 included in core complex 1810(j) can access all L3 caches 1830(j) included in core complex 1810(j), where j is an integer representing a specific instance of core complex 1810. In at least one embodiment, the L3 cache 1830 may include, but is not limited to, any number of slices.

[0239] In at least one embodiment, structure 1860 is a system interconnect that facilitates data and control transfers across core complexes 1810(1)-1810(N) (where N is a positive integer), I / O interface 1870, and memory controller 1880. In at least one embodiment, in addition to or instead of structure 1860, CPU 1800 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of components that may be directly or indirectly linked, either inside or outside CPU 1800. In at least one embodiment, I / O interface 1870 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1870. In at least one embodiment, peripheral devices coupled to I / O interface 1870 may include, but are not limited to, displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0240] In at least one embodiment, memory controller 1880 facilitates data transfer between CPU 1800 and system memory 1890. In at least one embodiment, core complex 1810 and graphics complex 1840 share system memory 1890. In at least one embodiment, CPU 1800 implements a memory subsystem, which includes, but is not limited to, any number and type of memory controllers 1880 and memory devices that may be dedicated to a component or shared among multiple components. In at least one embodiment, CPU 1800 implements a cache subsystem, which includes, but is not limited to, one or more cache memories (e.g., L2 cache 1828 and L3 cache 1830), each cache memory may be component-private or shared among any number of components (e.g., core 1820 and core complex 1810).

[0241] Figure 18 The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 18 The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figure 18 The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figure 18The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figure 18 The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figure 18 The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0242] Figure 19An exemplary accelerator integration slice 1990 according to at least one embodiment is illustrated. As used herein, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services for multiple graphics processing engines among multiple graphics acceleration modules. Each graphics processing engine may comprise a separate GPU. Optionally, the graphics processing engine may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0243] The application's effective address space 1982 within system memory 1914 stores process element 1983. In one embodiment, process element 1983 is stored in response to a GPU call 1981 from an application 1980 executing on processor 1907. Process element 1983 contains the processing state of the corresponding application 1980. A job descriptor (WD) 1984 contained in process element 1983 may be a single job requested by the application or may contain pointers to job queues. In at least one embodiment, WD 1984 is a pointer to a job request queue in the application's effective address space 1982.

[0244] The graphics acceleration module 1946 and / or individual graphics processing engines may be shared by all or some processes in the system. In at least one embodiment, infrastructure may be included for establishing a processing state and sending WD 1984 to the graphics acceleration module 1946 to begin operation in a virtualized environment.

[0245] In at least one embodiment, a dedicated process programming model is used for implementation. In this model, a single process owns the graphics acceleration module 1946 or an individual graphics processing engine. Since the graphics acceleration module 1946 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and the operating system initializes the accelerator integrated circuit for the owned partition when the graphics acceleration module 1946 is allocated.

[0246] During operation, the WD fetch unit 1991 in the accelerator integrated slice 1990 fetches the next WD 1984, which includes instructions for the work to be performed by one or more graphics processing engines of the graphics acceleration module 1946. Data from the WD 1984 can be stored in register 1945 and used by the memory management unit (MMU) 1939, interrupt management circuitry 1947, and / or environment management circuitry 1948, as shown. For example, one embodiment of the MMU 1939 includes segment / page roaming circuitry for accessing segment / page tables 1986 within the OS virtual address space 1985. The interrupt management circuitry 1947 can handle interrupt events (INT) 1992 received from the graphics acceleration module 1946. When performing graph operations, the effective address 1993 generated by the graphics processing engine is translated into an actual address by the MMU 1939.

[0247] In one embodiment, the same register set 1945 is copied for each graphics processing engine and / or graphics acceleration module 1946 and can be initialized by the hypervisor or operating system. Each of these copied registers can be included in the accelerator integration slice 1990. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0248] Table 1 - Registers for Supervisor Initialization

[0249]

[0250]

[0251] Table 2 shows exemplary registers that can be initialized by the operating system.

[0252] Table 2 - Operating System Initialization Registers

[0253] 1 Process and thread identification 2 Valid Address (EA) Environment Save / Restore Pointer 3 Virtual Address (VA) accelerator utilization record pointer 4 Virtual address (VA) stores segment table pointers 5 mask of authority 6 Job descriptor

[0254] In one embodiment, each WD 1984 is specific to a particular graphics acceleration module 1946 and / or a particular graphics processing engine. It contains all the information required for the graphics processing engine to perform its work or to do so, or it may be a pointer to a memory location where the application has established a command queue for the work to be done.

[0255] Figure 19 The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 19 The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43The process is described. In at least one embodiment, Figure 19 The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figure 19 The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figure 19 The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figure 19The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0256] Figures 20A-20B An exemplary graphics processor according to at least one embodiment herein is illustrated. In at least one embodiment, any exemplary graphics processor may be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuitry may be included in at least one embodiment, including additional graphics processor / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is used within a System-on-a-Chip (SoC).

[0257] Figure 20A An exemplary graphics processor 2010 of a SoC integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 20B An additional exemplary graphics processor 2040 of a SoC integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 20A The graphics processor 2010 is a low-power graphics processor core. In at least one embodiment, Figure 20B The graphics processor 2040 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 2010, 2040 may be... Figure 15 A variant of the 1510 graphics processor.

[0258] In at least one embodiment, the graphics processor 2010 includes a vertex processor 2005 and one or more fragment processors 2015A-2015N (e.g., 2015A, 2015B, 2015C, 2015D to 2015N-1 and 2015N). In at least one embodiment, the graphics processor 2010 may execute different shader programs via separate logic, such that the vertex processor 2005 is optimized to perform operations for the vertex shader program, while one or more fragment processors 2015A-2015N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 2005 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, the fragment processors 2015A-2015N use the primitive and vertex data generated by the vertex processor 2005 to generate framebuffers for display on a display device. In at least one embodiment, the fragment processors 2015A-2015N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0259] In at least one embodiment, the graphics processor 2010 additionally includes one or more MMUs 2020A-2020B, caches 2025A-2025B, and circuit interconnects 2030A-2030B. In at least one embodiment, one or more MMUs 2020A-2020B provide a virtual-to-physical address mapping for the graphics processor 2010, including for the vertex processor 2005 and / or fragment processors 2015A-2015N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 2025A-2025B. In at least one embodiment, one or more MMUs 2020A-2020B can be synchronized with other MMUs within the system, including with... Figure 15 One or more application processors 1505, graphics processors 1515, and / or video processors 1520 are associated with one or more MMUs, such that each processor 1505-1520 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2030A-2030B enable the graphics processor 2010 to be connected to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0260] In at least one embodiment, the graphics processor 2040 includes Figure 20AThe graphics processor 2010 includes one or more MMUs 2020A-2020B, caches 2025A-2025B, and circuit interconnects 2030A-2030B. In at least one embodiment, the graphics processor 2040 includes one or more shader cores 2055A-2055N (e.g., 2055A, 2055B, 2055C, 2055D, 2055E, 2055F, to 2055N-1 and 2055N) that provide a unified shader core architecture, wherein a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 2040 includes an inter-core task manager 2045 that acts as a thread dispatcher to assign execution threads to one or more shader cores 2055A-2055N and tile units 2058 to accelerate tile-based rendering operations, wherein rendering operations of a scene are subdivided in image space, for example, to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0261] Figures 20A-20B The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figures 20A-20B The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figures 20A-20B The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figures 20A-20B The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figures 20A-20B The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figures 20A-20B The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0262] Figure 21A A graphics core 2100 according to at least one embodiment is shown. In at least one embodiment, the graphics core 2100 may include... Figure 15 The graphics processor 1510 is located within it. In at least one embodiment, the graphics core 2100 may be... Figure 20BThe graphics core 2100 uses a unified shader core 2055A-2055N. In at least one embodiment, the graphics core 2100 includes a shared instruction cache 2102, texture units 2118, and cache / shared memory 2120, which are common to execution resources within the graphics core 2100. In at least one embodiment, the graphics core 2100 may include multiple slices 2101A-2101N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 2100. Slices 2101A-2101N may include supporting logic, including a local instruction cache 2104A-2104N, a thread scheduler 2106A-2106N, a thread dispatcher 2108A-2108N, and a set of registers 2110A-2110N. In at least one embodiment, slices 2101A-2101N may include a set of additional function units (AFU) 2112A-2112N, floating-point units (FPU) 2114A-2114N, integer arithmetic logic units (ALU) 2116A-2116N, address calculation units (ACU) 2113A-2113N, double-precision floating-point units (DPFPU) 2115A-2115N, and matrix processing units (MPU) 2117A-2117N. In at least one embodiment, graphics core 2100 is referred to as a computing unit or arithmetic unit.

[0263] In one embodiment, the FPU 2114A-2114N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2115A-2115N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 2116A-2116N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2117A-2117N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2117A-2117N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated Generalized Matrix-to-Matrix Multiplication (GEMM). In at least one embodiment, the AFU 2112A-2112N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0264] Figure 21BA general-purpose graphics processing unit (GPGPU) 2130 is illustrated in at least one embodiment. In at least one embodiment, the GPGPU 2130 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, the GPGPU 2130 can be configured to enable highly parallel computational operations to be performed by a GPU array. In at least one embodiment, the GPGPU 2130 can be directly linked to other instances of the GPGPU 2130 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, the GPGPU 2130 includes a host interface 2132 for connection to a host processor. In at least one embodiment, the host interface 2132 is a PCIe interface. In at least one embodiment, the host interface 2132 can be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 2130 receives commands from the host processor and uses a global scheduler 2134 to assign execution threads associated with those commands to a set of computational clusters 2136A-2136H. In at least one embodiment, computing clusters 2136A-2136H share cache memory 2138. In at least one embodiment, cache memory 2138 can be used as an advanced cache of cache memory within computing clusters 2136A-2136H.

[0265] In at least one embodiment, the GPGPU 2130 includes memory 2144A-2144B coupled to computing clusters 2136A-2136H via a set of memory controllers 2142A-2142B. In at least one embodiment, memory 2144A-2144B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0266] In at least one embodiment, computing clusters 2136A-2136H each include a set of graphics cores, such as Figure 21A The graphics core 2100 may include various types of integer and floating-point logic units, capable of performing computational operations at various precisions, including computations suitable for CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 2136A-2136H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0267] In at least one embodiment, multiple instances of GPGPU 2130 can be configured to operate as a computing cluster. The computing clusters 2136A-2136H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, the multiple instances of GPGPU 2130 communicate via host interface 2132. In at least one embodiment, GPGPU 2130 includes an I / O hub 2139 that couples GPGPU 2130 to GPU link 2140, enabling direct connection to other instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a dedicated GPU-to-GPU bridge, enabling communication and synchronization among the multiple instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, the multiple instances of GPGPU 2130 reside in a separate data processing system and communicate via a network device accessible via host interface 2132. In at least one embodiment, GPU link 2140 may be configured to connect to a host processor, supplementing or replacing host interface 2132. In at least one embodiment, GPGPU 2130 may be configured to execute CUDA programs.

[0268] Figures 21A-21B The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figures 21A-21B The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figures 21A-21B The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figures 21A-21B The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figures 21A-21B The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figures 21A-21B The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0269] Figure 22A A parallel processor 2200 according to at least one embodiment is shown. In at least one embodiment, various components of the parallel processor 2200 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or FPGAs.

[0270] In at least one embodiment, the parallel processor 2200 includes a parallel processing unit 2202. In at least one embodiment, the parallel processing unit 2202 includes an I / O unit 2204 that enables communication with other devices, including other instances of the parallel processing unit 2202. In at least one embodiment, the I / O unit 2204 can be directly connected to other devices. In at least one embodiment, the I / O unit 2204 is connected to other devices using a hub or switch interface (e.g., a memory hub 2205). In at least one embodiment, the connection between the memory hub 2205 and the I / O unit 2204 forms a communication link. In at least one embodiment, the I / O unit 2204 is connected to a host interface 2206 and a memory crossbar switch 2216, wherein the host interface 2206 receives commands for performing processing operations, and the memory crossbar switch 2216 receives commands for performing memory operations.

[0271] In at least one embodiment, when host interface 2206 receives a command buffer via I / O unit 2204, host interface 2206 can direct work operations to execute those commands to front end 2208. In at least one embodiment, front end 2208 is coupled to scheduler 2210, which is configured to assign commands or other work items to processing array 2212. In at least one embodiment, scheduler 2210 ensures that processing array 2212 is correctly configured and in an active state before assigning tasks to processing array 2212. In at least one embodiment, scheduler 2210 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2210 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, enabling fast preemption and environment switching of threads executing on processing array 2212. In at least one embodiment, host software can demonstrate workloads scheduled on processing array 2212 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed on the processing array 2212 by the scheduler 2210 logic within the microcontroller, which includes the scheduler 2210.

[0272] In at least one embodiment, the processing array 2212 may include up to "N" processing clusters (e.g., clusters 2214A, 2214B to 2214N). In at least one embodiment, each cluster 2214A-2214N of the processing array 2212 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2210 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2214A-2214N of the processing array 2212, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2210, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing array 2212. In at least one embodiment, different clusters 2214A-2214N of the processing array 2212 may be assigned to process different types of programs or to perform different types of computations.

[0273] In at least one embodiment, the processing array 2212 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 2212 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing array 2212 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0274] In at least one embodiment, the processing array 2212 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 2212 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 2212 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2202 may transfer data from system memory via I / O unit 2204 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2222) and then written back to system memory.

[0275] In at least one embodiment, when the parallel processing unit 2202 is used to perform graph processing, the scheduler 2210 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 2214A-2214N of the processing array 2212. In at least one embodiment, portions of the processing array 2212 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2214A-2214N may be stored in a buffer to allow intermediate data to be transferred between the clusters 2214A-2214N for further processing.

[0276] In at least one embodiment, the processing array 2212 may receive processing tasks to be executed via a scheduler 2210, which receives commands defining the processing tasks from the front end 2208. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2210 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2208. In at least one embodiment, the front end 2208 may be configured to ensure that the processing array 2212 is configured to be active before initiating a workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0277] In at least one embodiment, each of one or more instances of the parallel processing unit 2202 may be coupled to the parallel processor memory 2222. In at least one embodiment, the parallel processor memory 2222 may be accessed via a memory crossbar switch 2216, which may receive memory requests from the processing array 2212 and the I / O unit 2204. In at least one embodiment, the memory crossbar switch 2216 may be accessed via a memory interface 2218. In at least one embodiment, the memory interface 2218 may include a plurality of partition units (e.g., partition units 2220A, 2220B to 2220N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2222. In at least one embodiment, the plurality of partition units 2220A-2220N are configured to be equal to the number of memory units, such that the first partition unit 2220A has a corresponding first memory unit 2224A, the second partition unit 2220B has a corresponding memory unit 2224B, and the Nth partition unit 2220N has a corresponding Nth memory unit 2224N. In at least one embodiment, the number of partition units 2220A-2220N may not be equal to the number of memory devices.

[0278] In at least one embodiment, memory cells 2224A-2224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2224A-2224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 2224A-2224N, allowing partitioning cells 2220A-2220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2222. In at least one embodiment, local instances of the parallel processor memory 2222 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0279] In at least one embodiment, any of the clusters 2214A-2214N of the processing array 2212 can process data to be written to any memory cell 2224A-2224N within the parallel processor memory 2222. In at least one embodiment, the memory crossbar switch 2216 can be configured to transfer the output of each cluster 2214A-2214N to any partition cell 2220A-2220N or another cluster 2214A-2214N, and the clusters 2214A-2214N can perform further processing operations on the output. In at least one embodiment, each cluster 2214A-2214N can communicate with the memory interface 2218 via the memory crossbar switch 2216 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 2216 has a connection to the memory interface 2218 for communication with the I / O unit 2204, and a connection to a local instance of the parallel processor memory 2222, thereby enabling processing units within different processing clusters 2214A-2214N to communicate with system memory or other memory not local to the parallel processing unit 2202. In at least one embodiment, the memory crossbar switch 2216 may use virtual channels to separate traffic flows between clusters 2214A-2214N and partition units 2220A-2220N.

[0280] In at least one embodiment, multiple instances of the parallel processing unit 2202 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2202 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2202 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 2202 or the parallel processor 2200 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0281] Figure 22BA processing cluster 2294 according to at least one embodiment is illustrated. In at least one embodiment, the processing cluster 2294 is included within a parallel processing unit. In at least one embodiment, the processing cluster 2294 is an example of one of the processing clusters 2214A-2214N of FIG. 22. In at least one embodiment, the processing cluster 2294 can be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 2294.

[0282] In at least one embodiment, the operation of the processing cluster 2294 can be controlled by a pipeline manager 2232 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2232 receives instructions from the scheduler 2210 of FIG. 22 and manages the execution of these instructions via the graphics multiprocessor 2234 and / or texture unit 2236. In at least one embodiment, the graphics multiprocessor 2234 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2294 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2294 may include one or more instances of the graphics multiprocessor 2234. In at least one embodiment, the graphics multiprocessor 2234 can process data, and the data cross switch 2240 can be used to distribute the processed data to one of a number of possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2232 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data cross switch 2240.

[0283] In at least one embodiment, each graphics multiprocessor 2234 within the processing cluster 2294 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units (LSUs), etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0284] In at least one embodiment, instructions sent to the processing cluster 2294 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes programs on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2234. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2234, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2234.

[0285] In at least one embodiment, the graphics multiprocessor 2234 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2234 may forgo the internal cache and use a cache memory within the processing cluster 2294 (e.g., L1 cache 2248). In at least one embodiment, each graphics multiprocessor 2234 may also access partition units (e.g., Figure 22A The L2 cache is located within partition units 2220A-2220N, which are shared among all processing clusters 2294 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2234 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2202 can be used as global memory. In at least one embodiment, the processing cluster 2294 includes multiple instances of the graphics multiprocessor 2234, which can share common instructions and data that can be stored in the L1 cache 2248.

[0286] In at least one embodiment, each processing cluster 2294 may include an MMU 2245 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2245 may reside within the memory interface 2218 of FIG22. In at least one embodiment, the MMU 2245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more information about tiles) and optionally to cache line indices. In at least one embodiment, the MMU 2245 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 2234, the L1 cache 2248, or the processing cluster 2294. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0287] In at least one embodiment, the processing cluster 2294 may be configured such that each graphics multiprocessor 2234 is coupled to a texture unit 2236 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2234, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2234 outputs a processed task to a data crossover switch 2240 to provide the processed task to another processing cluster 2294 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossover switch 2216. In at least one embodiment, the pre-ROP unit 2242 is configured to receive data from the graphics multiprocessor 2234 and direct the data to a ROP unit that may be located together with partitioning units described herein (e.g., partitioning units 2220A-2220N of FIG. 22). In at least one embodiment, the PreROP unit 2242 may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0288] Figure 22C A graphics multiprocessor 2296 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2296 is... Figure 22BThe graphics multiprocessor 2234 is included. In at least one embodiment, the graphics multiprocessor 2296 is coupled to the pipeline manager 2232 of the processing cluster 2294. In at least one embodiment, the graphics multiprocessor 2296 has an execution pipeline including, but not limited to, an instruction cache 2252, an instruction unit 2254, an address mapping unit 2256, a register file 2258, one or more GPGPU cores 2262, and one or more LSUs 2266. The GPGPU cores 2262 and LSUs 2266 are coupled to cache memory 2272 and shared memory 2270 via memory and cache interconnect 2268.

[0289] In at least one embodiment, instruction cache 2252 receives a stream of instructions to be executed from pipeline manager 2232. In at least one embodiment, instructions are cached in instruction cache 2252 and dispatched to instruction unit 2254 for execution. In one embodiment, instruction unit 2254 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 2262. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2256 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by LSU 2266.

[0290] In at least one embodiment, register file 2258 provides a set of registers for functional units of graphics multiprocessor 2296. In at least one embodiment, register file 2258 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2296 (e.g., GPGPU core 2262, LSU 2266). In at least one embodiment, register file 2258 is partitioned among each functional unit, such that a dedicated portion of register file 2258 is allocated to each functional unit. In at least one embodiment, register file 2258 is partitioned among different thread groups being executed by graphics multiprocessor 2296.

[0291] In at least one embodiment, each of the GPGPU cores 2262 may include an FPU and / or an ALU for executing instructions of the graph multiprocessor 2296. The GPGPU cores 2262 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2208 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2296 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2262 may also include fixed-function or special-function logic.

[0292] In at least one embodiment, the GPGPU core 2262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2262 can physically execute SIMD4, SIMD8, and SIMD9 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0293] In at least one embodiment, the memory and cache interconnect 2268 is an interconnect network connecting each functional unit of the graphics multiprocessor 2296 to the register file 2258 and the shared memory 2270. In at least one embodiment, the memory and cache interconnect 2268 is a cross-switch interconnect that allows the LSU 2266 to perform load and store operations between the shared memory 2270 and the register file 2258. In at least one embodiment, the register file 2258 can operate at the same frequency as the GPGPU core 2262, resulting in very low latency for data transfer between the GPGPU core 2262 and the register file 2258. In at least one embodiment, the shared memory 2270 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2296. In at least one embodiment, the cache memory 2272 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 2236. In at least one embodiment, the shared memory 2270 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 2272, the thread executing on GPGPU core 2262 can also programmatically store data in shared memory.

[0294] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to the host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0295] Figures 22A-22C The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figures 22A-22C The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figures 22A-22CThe systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figures 22A-22C The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figures 22A-22C The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figures 22A-22CThe system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0296] Figure 23 A graphics processor 2300 according to at least one embodiment is illustrated. In at least one embodiment, the graphics processor 2300 includes a ring interconnect 2302, a pipeline front end 2304, a media engine 2337, and graphics cores 2380A-2380N. In at least one embodiment, the ring interconnect 2302 couples the graphics processor 2300 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2300 is one of many processors integrated within a multi-core processing system.

[0297] In at least one embodiment, the graphics processor 2300 receives multiple batches of commands via a ring interconnect 2302. In at least one embodiment, the input commands are interpreted by a command stream converter 2303 in a pipeline front-end 2304. In at least one embodiment, the graphics processor 2300 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 2380A-2380N. In at least one embodiment, for 3D geometry processing commands, the command stream converter 2303 provides commands to the geometry pipeline 2336. In at least one embodiment, for at least some media processing commands, the command stream converter 2303 provides commands to a video front-end 2334, which is coupled to a media engine 2337. In at least one embodiment, the media engine 2337 includes a video quality engine (VQE) 2330 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 2333 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2336 and the media engine 2337 each generate an execution thread for the thread execution resources provided by at least one graphics core 2380A.

[0298] In at least one embodiment, the graphics processor 2300 includes scalable thread execution resources characterized by modular graphics cores 2380A-2380N (sometimes referred to as core slices), each modular core having multiple sub-cores 2350A-2350N, 2360A-2360N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2300 may have any number of graphics cores 2380A to 2380N. In at least one embodiment, the graphics processor 2300 includes a graphics core 2380A having at least a first sub-core 2350A and a second sub-core 2360A. In at least one embodiment, the graphics processor 2300 is a low-power processor having a single sub-core (e.g., 2350A). In at least one embodiment, the graphics processor 2300 includes multiple graphics cores 2380A-2380N, each graphics core including a set of first sub-cores 2350A-2350N and a set of second sub-cores 2360A-2360N. In at least one embodiment, each of the first sub-cores 2350A-2350N includes at least a first set of execution units (EUs) 2352A-2352N and media / texture samplers 2354A-2354N. In at least one embodiment, each of the second sub-cores 2360A-2360N includes at least a second set of execution units 2362A-2362N and samplers 2364A-2364N. In at least one embodiment, each sub-core 2350A-2350N and 2360A-2360N shares a set of shared resources 2370A-2370N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0299] Figure 23 The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 23 The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figure 23 The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figure 23 The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figure 23 The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figure 23 The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0300] Figure 24A processor 2400 is illustrated according to at least one embodiment. In at least one embodiment, the processor 2400 may include, but is not limited to, logic circuitry for executing instructions. In at least one embodiment, the processor 2400 can execute instructions, including x86 instructions, ARM instructions, special-purpose instructions for ASICs, etc. In at least one embodiment, the processor 2410 may include registers for storing packaged data, such as the 64-bit wide MMX™ registers in an Intel microprocessor enabled by MMX technology in Santa Clara, California. In at least one embodiment, the MMX registers available in integer and floating-point forms can operate with packaged data elements accompanied by SIMD and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, the processor 2410 can execute instructions to accelerate CUAD programs.

[0301] In at least one embodiment, processor 2400 includes an ordered front end (“front end”) 2401 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2401 may include several units. In at least one embodiment, instruction prefetcher 2426 fetches instructions from memory and provides the instructions to instruction decoder 2428, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2428 decodes the received instructions into one or more operations, so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”), for execution. In at least one embodiment, instruction decoder 2428 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform the operations. In at least one embodiment, trace cache 2430 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 2434 for execution. In at least one embodiment, when trace cache 2430 encounters complex instructions, microcode ROM 2432 provides the micro-instructions required to complete the operation.

[0302] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2428 may access the microcode ROM 2432 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2428. In at least one embodiment, if multiple micro-instructions are required to complete an operation, the instructions may be stored in the microcode ROM 2432. In at least one embodiment, the trace cache 2430 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2432 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2432 has completed the micro-operation ordering of the instructions, the machine front end 2401 may resume fetching micro-operations from the trace cache 2430.

[0303] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2403 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. The out-of-order execution engine 2403 includes, but is not limited to, an allocator / register renamer 2440, a memory microinstruction queue 2442, an integer / floating-point microinstruction queue 2444, a memory scheduler 2446, a fast scheduler 2402, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2404, and a simple floating-point scheduler (“simple FP scheduler”) 2406. In at least one embodiment, the fast scheduler 2402, the slow / general-purpose floating-point scheduler 2404, and the simple floating-point scheduler 2406 are also collectively referred to as “microinstruction schedulers 2402, 2404, 2406”. The allocator / register renamer 2440 allocates the machine buffers and resources required for the sequential execution of each microinstruction. In at least one embodiment, the allocator / register renamer 2440 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2440 also assigns entries for each microinstruction in one of two microinstruction queues, memory microinstruction queue 2442 for memory operations and integer / floating-point microinstruction queue 2444 for non-memory operations, preceding the memory scheduler 2446 and microinstruction schedulers 2402, 2404, and 2406. In at least one embodiment, the microinstruction schedulers 2402, 2404, and 2406 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2402 of at least one embodiment can schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2404 and the simple floating-point scheduler 2406 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2402, 2404, and 2406 arbitrate the scheduling port to schedule microinstructions for execution.

[0304] In at least one embodiment, execution block 2411 includes, but is not limited to, integer register file / tribute network 2408, floating-point register file / tribute network (“FP register file / tribute network”) 2410, address generation units (“AGU”) 2412 and 2414, fast arithmetic logic units (“fast ALU”) 2416 and 2418, slow ALU 2420, floating-point ALU (“FP”) 2422, and floating-point movement unit (“FP movement”) 2424. In at least one embodiment, integer register file / tribute network 2408 and floating-point register file / bypass network 2410 are also referred to herein as “register files 2408, 2410”. In at least one embodiment, AGUS 2412 and 2414, fast ALU 2416 and 2418, slow ALU 2420, floating-point ALU 2422, and floating-point movement unit 2424 are also referred to herein as "execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424". In at least one embodiment, the execution block may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0305] In at least one embodiment, register files 2408, 2410 may be arranged between microinstruction schedulers 2402, 2404, 2406 and execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424. In at least one embodiment, integer register file / tribute network 2408 performs integer operations. In at least one embodiment, floating-point register file / tribute network 2410 performs floating-point operations. In at least one embodiment, each of register files 2408, 2410 may include, but is not limited to, a tribute network that can bypass or forward recently completed results not yet written to the register file to a new dependent object. In at least one embodiment, register files 2408, 2410 may communicate data with each other. In at least one embodiment, integer register file / tribute network 2408 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 2410 may include, but is not limited to, entries with a width of 128 bits, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0306] In at least one embodiment, execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424 can execute instructions. In at least one embodiment, register files 2408 and 2410 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2400 may include, but is not limited to, any number of execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424, and combinations thereof. In at least one embodiment, floating-point ALU 2422 and floating-point move unit 2424 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2422 may include, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to the fast ALUs 2416 and 2418. In at least one embodiment, the fast ALUs 2416 and 2418 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to the slow ALU 2420, because the slow ALU 2420 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by the ALUs 2412 and 2414. In at least one embodiment, the fast ALUs 2416, 2418, and 2420 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALUs 2416, 2418, and 2420 can be implemented to support various data bit sizes, including 16, 32, 128, 256, etc. In at least one embodiment, the floating-point ALU 2422 and the floating-point movement unit 2424 can be implemented to support a range of operands with various bit widths. In at least one embodiment, the floating-point ALU 2422 and the floating-point movement unit 2424 can operate on 128-bit wide packaged data operands in conjunction with SIMD and multimedia instructions.

[0307] In at least one embodiment, microinstruction schedulers 2402, 2404, and 2406 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2400, processor 2400 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences used for text string comparison operations.

[0308] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction that identifies operands. In at least one embodiment, a register may be one that can be used externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0309] Figure 24 The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 24 The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figure 24 The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figure 24The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figure 24 The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figure 24 The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0310] Figure 25A processor 2500 according to at least one embodiment is illustrated. In at least one embodiment, the processor 2500 includes, but is not limited to, one or more processor cores (cores) 2502A-2502N, an integrated memory controller 2514, and an integrated graphics processor 2508. In at least one embodiment, the processor 2500 may include additional cores up to and including additional processor cores 2502N, indicated by dashed boxes. In at least one embodiment, each processor core 2502A-2502N includes one or more internal cache units 2504A-2504N. In at least one embodiment, each processor core may also access one or more units 2506 of a shared cache. In at least one embodiment, one or more processor cores 2502A-2502N are referred to as one or more computing units or arithmetic units.

[0311] In at least one embodiment, internal cache units 2504A-2504N and shared cache unit 2506 represent a cache memory hierarchy within processor 2500. In at least one embodiment, cache memory units 2504A-2504N may include at least one level of instruction and data within each processor core, and one or more levels of cache in a shared intermediate cache, such as L2, L3, L4, or other levels of cache, wherein the highest level of cache is classified as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2506 and 2504A-2504N.

[0312] In at least one embodiment, the processor 2500 may further include a group of one or more bus controller units 2516 and a system agent core 2510. In at least one embodiment, one or more bus controller units 2516 manage a group of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2510 provides management functions for various processor components. In at least one embodiment, the system agent core 2510 includes one or more integrated memory controllers 2514 to manage access to various external memory devices (not shown).

[0313] In at least one embodiment, one or more processor cores 2502A-2502N include support for multi-threaded concurrent processing. In at least one embodiment, system agent core 2510 includes components for coordinating and operating processor cores 2502A-2502N during multi-threaded processing. In at least one embodiment, system agent core 2510 may additionally include a power control unit (PCU) including logic and components for regulating one or more power states of processor cores 2502A-2502N and graphics processor 2508.

[0314] In at least one embodiment, processor 2500 further includes graphics processor 2508 to perform graphics processing operations. In at least one embodiment, graphics processor 2508 is coupled to a shared cache unit 2506 and a system proxy core 2510 including one or more integrated memory controllers 2514. In at least one embodiment, system proxy core 2510 further includes a display controller 2511 for driving graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2511 may also be a separate module coupled to graphics processor 2508 via at least one interconnect, or it may be integrated within graphics processor 2508.

[0315] In at least one embodiment, ring-based interconnect unit 2512 is used to couple internal components of processor 2500. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, graphics processor 2508 is coupled to ring interconnect 2512 via I / O link 2513.

[0316] In at least one embodiment, I / O link 2513 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory module 2518 (e.g., eDRAM module). In at least one embodiment, each of processor cores 2502A-2502N and graphics processor 2508 uses embedded memory module 2518 as a shared LLC.

[0317] In at least one embodiment, processor cores 2502A-2502N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2502A-2502N are heterogeneous in terms of the ISA, with one or more processor cores 2502A-2502N executing a common instruction set, while one or more other processor cores 2502A-2502N execute a common instruction set or a subset of a different instruction set. In at least one embodiment, processor cores 2502A-2502N are heterogeneous in terms of microarchitecture, with one or more cores having relatively high power consumption coupled to one or more power cores having lower power consumption. In at least one embodiment, processor 2500 can be implemented on one or more chips or implemented as a SoC integrated circuit.

[0318] Figure 25 The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 25 The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figure 25 The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figure 25 The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figure 25 The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figure 25 The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0319] Figure 26 A graphics processing unit (GPU) core 2600 according to at least one embodiment described is illustrated. In at least one embodiment, the GPU core 2600 is included within a GPU core array. In at least one embodiment, the GPU core 2600 (sometimes referred to as a core slice) may be one or more GPU cores within a modular GPU. In at least one embodiment, the GPU core 2600 is an example of a GPU core slice, and the GPU described herein may include multiple GPU core slices based on target power and performance envelopes. In at least one embodiment, each GPU core 2600 may include a fixed-function block 2630, also referred to as a sub-slice, coupled to a plurality of sub-cores 2601A-2601F, which includes modules of general-purpose and fixed-function logic.

[0320] In at least one embodiment, the fixed-function block 2630 includes a geometry / fixed-function pipeline 2636, which, for example, may be shared by all sub-cores of the graphics processor 2600 in a lower-performance and / or lower-power graphics processor implementation. In at least one embodiment, the geometry / fixed-function pipeline 2636 includes a 3D fixed-function pipeline, a video front-end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0321] In at least one embodiment, fixed function block 2630 further includes a graphics SoC interface 2637, a graphics microcontroller 2638, and a media pipeline 2639. The graphics SoC interface 2637 provides an interface between the graphics core 2600 and other processor cores in the SoC integrated circuit system. In at least one embodiment, the graphics microcontroller 2638 is a programmable subprocessor configurable to manage various functions of the graphics processor 2600, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 2639 includes logic that facilitates decoding, encoding, preprocessing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 2639 implements media operations via requests for computation or sampling logic within subcores 2601-2601F.

[0322] In at least one embodiment, the SoC interface 2637 enables the graphics core 2600 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2637 also enables communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enables the use and / or implementation of global memory atoms that can be shared between the graphics core 2600 and the CPU within the SoC. In at least one embodiment, the SoC interface 2637 also implements power management control for the graphics core 2600 and enables interfacing between the clock domain of the graphics core 2600 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2637 enables the receipt of command buffers from a command stream converter and a global thread dispatcher, configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, when a media operation is to be performed, commands and instructions can be dispatched to media pipeline 2639, or when a graph processing operation is to be performed, they can be assigned to geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 2636, geometry and fixed function pipeline 2614).

[0323] In at least one embodiment, the graphics microcontroller 2638 can be configured to perform various scheduling and management tasks on the graphics core 2600. In at least one embodiment, the graphics microcontroller 2638 can perform graph and / or computation workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 2602A-2602F, 2604A-2604F in the sub-cores 2601A-2601F. In at least one embodiment, host software executing on the CPU core of the SoC including the graphics core 2600 can submit a workload of one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload should be run next, submitting the workload to a command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, the graphics microcontroller 2638 may also facilitate a low-power or idle state of the graphics core 2600, thereby providing the graphics core 2600 with the ability to save and restore registers across low-power state transitions within the graphics core 2600, independent of the operating system and / or the graphics driver software on the system.

[0324] In at least one embodiment, the graphics core 2600 may have more or fewer subcores than the illustrated subcores 2601A-2601F, up to N modular subcores. For each group of N subcores, in at least one embodiment, the graphics core 2600 may further include shared functional logic 2610, shared and / or cache memory 2612, geometry / fixed-function pipeline 2614, and additional fixed-function logic 2616 to accelerate various graphics and computational processing operations. In at least one embodiment, the shared functional logic 2610 may include logic units (e.g., samplers, mathematical and / or inter-thread communication logic) that can be shared by each of the N subcores within the graphics core 2600. The shared and / or cache memory 2612 may be an LLC of the N subcores 2601A-2601F within the graphics core 2600, and may also be used as shared memory accessible by multiple subcores. In at least one embodiment, a geometry / fixed function pipeline 2614 may be included to replace the geometry / fixed function pipeline 2636 within the fixed function block 2630, and may include the same or similar logic units.

[0325] In at least one embodiment, the graphics core 2600 includes additional fixed-function logic 2616, which may include various fixed-function acceleration logics for use by the graphics core 2600. In at least one embodiment, the additional fixed-function logic 2616 includes additional geometry pipelines for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and in the full geometry pipeline and culling pipeline within the geometry / fixed-function pipelines 2616, 2636, it is an additional geometry pipeline that can be included in the additional fixed-function logic 2616. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of the application, each with a separate environment. In at least one embodiment, position-only shading can hide long culling runs of discarded triangles, thereby allowing shading to be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed-function logic 2616 can execute the position shader in parallel with the main application and typically generates critical results faster than the full pipeline because the culling pipeline acquires and occludes the positional attributes of vertices without performing rasterization and rendering pixels to the framebuffer. In at least one embodiment, the culling pipeline can use the generated critical results to compute visibility information for all triangles, regardless of whether those triangles were culled. In at least one embodiment, the full pipeline (which may be referred to as the replay pipeline in this case) can consume visibility information to skip culled triangles and only occlude the visible triangles that are ultimately passed to the rasterization stage.

[0326] In at least one embodiment, the additional fixed-function logic 2616 may also include general target processing acceleration logic, such as fixed-function matrix multiplication logic, for implementing a decelerated CUAD program.

[0327] In at least one embodiment, each graphics subcore 2601A-2601F includes a set of execution resources that can be used to perform graph, media, and computational operations in response to requests from the graphics pipeline, media pipeline, or shader program. In at least one embodiment, the graphics subcore 2601A-2601F includes multiple EU arrays 2602A-2602F, 2604A-2604F, thread dispatch and inter-thread communication (TD / IC) logic 2603A-2603F, 3D (e.g., texture) samplers 2605A-2605F, media samplers 2606A-2606F, shader processors 2607A-2607F, and shared local memory (SLM) 2608A-2608F. Each of the EU arrays 2602A-2602F and 2604A-2604F contains multiple execution units, which are GUGPUs capable of servicing graphics, media, or computational operations, performing floating-point and integer / fixed-point logic operations, including graphics, media, or computational shader programs. In at least one embodiment, the TD / IC logic 2603A-2603F performs local thread dispatch and thread control operations for the execution units within the subcore and facilitates communication between threads executing on the execution units of the subcore. In at least one embodiment, the 3D samplers 2605A-2605F can read data associated with textures or other 3D graphics into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the sampling state and texture format configured and associated with a given texture. In at least one embodiment, the media samplers 2606A-2606F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics subcore 2601A-2601F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each subcore 2601A-2601F may utilize shared local memory 2608A-2608F within each subcore, enabling threads executing within a thread group to use a common pool of on-chip memory for execution.

[0328] Figure 26 The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 26 The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figure 26The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figure 26 The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figure 26 The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figure 26The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0329] Figure 27 A parallel processing unit (“PPU”) 2700 according to at least one embodiment is illustrated. In at least one embodiment, the PPU 2700 is configured with machine-readable code that, if executed by the PPU 2700, causes the PPU 2700 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 2700 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multi-threading as a latency-hiding technique designed to process computer-readable instructions (also known as machine-readable instructions or simple instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of an instruction set configured to be executed by the PPU 2700. In at least one embodiment, the PPU 2700 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data to generate two-dimensional (“2D”) image data for display on a display device, such as an LCD device. In at least one embodiment, the PPU 2700 is used to perform computations, such as linear algebra operations and machine learning operations. Figure 27 An example parallel processor is shown for illustrative purposes only and should be interpreted as a non-limiting example of a processor architecture implemented in at least one embodiment.

[0330] In at least one embodiment, one or more PPUs 2700 are configured to accelerate high-performance computing (“HPC”), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2700 are configured to accelerate CUDA programs. In at least one embodiment, the PPU 2700 includes, but is not limited to, I / O unit 2706, front-end unit 2710, scheduler unit 2712, job allocation unit 2714, hub 2716, crossbar switch (“Xbar”) 2720, one or more general-purpose processing clusters (“GPC”) 2718, and one or more partitioning units (“memory partitioning units”) 2722. In at least one embodiment, the PPU 2700 is connected to a host processor or other PPU 2700 via one or more high-speed GPU interconnects (“GPU interconnects”) 2708. In at least one embodiment, the PPU 2700 is connected to a host processor or other peripheral device via interconnect 2702. In one embodiment, the PPU 2700 is connected to local memory including one or more memory devices (“memory”) 2704. In at least one embodiment, the memory device 2704 includes, but is not limited to, one or more dynamic random access memory (“DRAM”) devices. In at least one embodiment, the one or more DRAM devices are configured and / or configurable as a high bandwidth memory (“HBM”) subsystem, and multiple DRAM dies are stacked within each device.

[0331] In at least one embodiment, the high-speed GPU interconnect 2708 may refer to a wire-based multi-channel communication link used by the system for scaling, and includes one or more PPUs 2700s (“CPUs”) coupled with one or more CPUs, supporting cache coherency between the PPUs 2700s and the CPUs, as well as CPU master control. In at least one embodiment, the high-speed GPU interconnect 2708 transmits data and / or commands to other units of the PPU 2700, such as one or more copy engines, video encoders, video decoders, power management units, and / or other components, via a hub 2716. Figure 27 Other components that may not be explicitly shown.

[0332] In at least one embodiment, the I / O unit 2706 is configured to access the host processor via the system bus 2702. Figure 27(Not shown) Sending and receiving communications (e.g., commands, data). In at least one embodiment, I / O unit 2706 communicates directly with the host processor via system bus 2702 or via one or more intermediate devices (e.g., memory bridges). In at least one embodiment, I / O unit 2706 may communicate with one or more other processors (e.g., one or more PPUs 2700) via system bus 2702. In at least one embodiment, I / O unit 2706 implements a PCIe interface for communication via the PCIe bus. In at least one embodiment, I / O unit 2706 implements an interface for communication with external devices.

[0333] In at least one embodiment, I / O unit 2706 decodes packets received via system bus 2702. In at least one embodiment, at least some packets represent commands configured to cause PPU 2700 to perform various operations. In at least one embodiment, I / O unit 2706 sends the decoded commands to various other units of PPU 2700 as specified by the commands. In at least one embodiment, the commands are sent to front-end unit 2710 and / or to hub 2716 or other units of PPU 2700, such as one or more copy engines, video encoders, video decoders, power management units, etc. Figure 27 (Not explicitly shown in the text). In at least one embodiment, I / O unit 2706 is configured to route communication between various logical units of PPU 2700.

[0334] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU 2700 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is a region in memory accessible (e.g., read / write) by both the host processor and the PPU 2700—the host interface unit can be configured to access a buffer in system memory connected to the system bus 2702 via memory requests transmitted through the system bus 2702 via the I / O unit 2706. In at least one embodiment, the host processor writes a command stream to the buffer and then sends a pointer indicating the start of the command stream to the PPU 2700, causing the front-end unit 2710 to receive pointers to one or more command streams and manage one or more command streams, read commands from the command streams, and forward the commands to the respective units of the PPU 2700.

[0335] In at least one embodiment, front-end unit 2710 is coupled to scheduler unit 2712, which configures various GPCs 2718 to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit 2712 is configured to track status information related to the various tasks managed by scheduler unit 2712, wherein the status information may indicate which GPC 2718 a task is assigned to, whether the task is active or inactive, the priority associated with the task, etc. In at least one embodiment, scheduler unit 2712 manages multiple tasks executed on one or more GPCs 2718.

[0336] In at least one embodiment, scheduler unit 2712 is coupled to job allocation unit 2714, which is configured to dispatch tasks for execution on GPC 2718. In at least one embodiment, job allocation unit 2714 tracks multiple scheduled tasks received from scheduler unit 2712 and manages a pool of pending tasks and an active task pool for each GPC 2718. In at least one embodiment, the pool of pending tasks includes multiple time slots (e.g., 32 time slots) containing tasks assigned to a particular GPC 2718; the active task pool may include multiple time slots (e.g., 4 time slots) for tasks actively processed by GPC 2718, such that as one of the GPCs 2718 completes its execution, that task is evicted from the active task pool of the GPC 2718, and one of other tasks is selected from the pool of pending tasks and scheduled for execution on the GPC 2718. In at least one embodiment, if an active task is idle on GPC 2718, for example while waiting for data dependencies to be resolved, the active task is evicted from GPC 2718 and returned to the pool of pending tasks, while another task in the pool of pending tasks is selected and scheduled to be executed on GPC 2718.

[0337] In at least one embodiment, the work allocation unit 2714 communicates with one or more GPCs 2718 via XBar 2720. In at least one embodiment, XBar 2720 is an interconnect network that couples a plurality of units of PPU 2700 to other units of PPU 2700, and can be configured to couple the work allocation unit 2714 to a specific GPC 2718. In at least one embodiment, other units of one or more PPUs 2700 can also be connected to XBar 2720 via hub 2716.

[0338] In at least one embodiment, tasks are managed by scheduler unit 2712 and assigned to one of GPCs 2718 by job allocation unit 2714. GPCs 2718 are configured to process tasks and produce results. In at least one embodiment, results may be consumed by other tasks in GPCs 2718, routed to different GPCs 2718 via XBar 2720, or stored in memory 2704. In at least one embodiment, results may be written to memory 2704 via partitioning unit 2722, which implements a memory interface for writing data to or reading data from memory 2704. In at least one embodiment, results may be transferred to another PPU 2700 or CPU via high-speed GPU interconnect 2708. In at least one embodiment, the PPU 2700 includes, but is not limited to, U partitioning units 2722, which is equal to the number of separate and distinct memory devices 2704 coupled to the PPU 2700.

[0339] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2700. In one embodiment, multiple computing applications are executed concurrently by the PPU 2700, and the PPU 2700 provides isolation, Quality of Service (“QoS”), and independent address spaces for the multiple computing applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 2700, and the driver core outputs the tasks to one or more streams processed by the PPU 2700. In at least one embodiment, each task includes one or more associated thread groups, which may be referred to as a warp. In at least one embodiment, a warp includes multiple associated threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperating thread may refer to multiple threads, including instructions for performing tasks and exchanging data via shared memory.

[0340] Figure 27 The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 27 The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figure 27The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figure 27 The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figure 27 The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figure 27The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0341] Figure 28 A GPC 2800 according to at least one embodiment is illustrated. In at least one embodiment, the GPC 2800 is Figure 27 The GPC 2718. In at least one embodiment, each GPC 2800 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2800 includes, but is not limited to, a pipeline manager 2802, a pre-raster operation unit (“PROP”) 2804, a raster engine 2808, a work assignment crossbar switch (“WDX”) 2816, a memory management unit (“MMU”) 2818, one or more data processing clusters (“DPC”) 2806, and any suitable combination of components.

[0342] In at least one embodiment, the operation of GPC 2800 is controlled by pipeline manager 2802. In at least one embodiment, pipeline manager 2802 manages the configuration of one or more DPCs 2806 to handle tasks assigned to GPC 2800. In at least one embodiment, pipeline manager 2802 configures at least one of one or more DPCs 2806 to implement at least a portion of the graphics rendering pipeline. In at least one embodiment, DPC 2806 is configured to execute vertex shader programs on programmable streaming multiprocessor (“SM”) 2814. In at least one embodiment, pipeline manager 2802 is configured to route packets received from the work allocation unit to appropriate logic units within GPC 2800, and in at least one embodiment, some packets may be routed to fixed-function hardware units in PROP 2804 and / or raster engine 2808, while other packets may be routed to DPC 2806 for processing by raw engine 2812 or SM 2814. In at least one embodiment, pipeline manager 2802 configures at least one of DPCs 2806 to implement a neural network model and / or computation pipeline. In at least one embodiment, pipeline manager 2802 configures at least one of DPCs 2806 to execute at least a portion of a CUDA program.

[0343] In at least one embodiment, the PROP unit 2804 is configured to route data generated by the raster engine 2808 and DPC 2806 to the raster operation (“ROP”) unit in the partition unit, for example, in conjunction with the above. Figure 27Memory partitioning unit 2722, etc., are described in more detail. In at least one embodiment, PROP unit 2804 is configured to perform optimizations for color blending, organize pixel data, perform address translation, etc. In at least one embodiment, raster engine 2808 includes, but is not limited to, multiple fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 2808 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are transmitted to the coarse raster engine to generate coverage information of basic primitives (e.g., x, y coverage masks of tiles); the output of the coarse raster engine is transmitted to the culling engine, in which fragments associated with primitives that fail the z-test are culled, and transmitted to the clipping engine, in which fragments located outside the view frustum are clipped. In at least one embodiment, the cropped and culled fragments are passed to a fine raster engine to generate properties of the pixel fragments based on a planar equation generated by the settings engine. In at least one embodiment, the output of the raster engine 2808 includes fragments that will be processed by any suitable entity (e.g., by a fragment shader implemented within the DPC 2806).

[0344] In at least one embodiment, each DPC 2806 included in the GPC 2800 includes, but is not limited to, an M-pipeline controller (“MPC”) 2810; a primitive engine 2812; one or more SMs 2814; and any suitable combination thereof. In at least one embodiment, the MPC 2810 controls the operation of the DPC 2806, routing packets received from the pipeline manager 2802 to the appropriate units within the DPC 2806. In at least one embodiment, packets associated with vertices are routed to the primitive engine 2812, which is configured to retrieve vertex attributes associated with vertices from memory; conversely, packets associated with shader programs may be sent to the SM 2814.

[0345] In at least one embodiment, the SM 2814 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, the SM 2814 is multithreaded and configured to execute multiple threads (e.g., 32 threads) from a specific thread group concurrently, and implements a Single Instruction, Multiple Data (“SIMD”) architecture, wherein each thread in a group of threads (e.g., a thread bundle) is configured to process a different dataset based on the same instruction set. In at least one embodiment, all threads in the thread group execute the same instructions. In at least one embodiment, the SM 2814 implements a Single Instruction, Multiple Thread (“SIMT”) architecture, wherein each thread in a group of threads is configured to process a different dataset based on the same instruction set, but wherein individual threads in the thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each thread bundle, thereby achieving concurrency between the thread bundle and serial execution within the thread bundle when threads in the thread bundle diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby ensuring equal concurrency among all threads within and between thread bundles. In at least one embodiment, an execution state is maintained for each individual thread, and threads executing the same instructions can be converged and executed in parallel to improve efficiency. The following is in conjunction with... Figure 29 At least one embodiment of SM 2814 is described in more detail.

[0346] In at least one embodiment, the MMU 2818 is integrated with the GPC 2800 and memory partitioning unit (e.g., Figure 27 The MMU 2818 provides an interface between partition units 2722 and provides virtual address to physical address translation, memory protection, and memory request arbitration. In at least one embodiment, the MMU 2818 provides one or more translation back buffers (“TLBs”) for performing virtual address to physical address translation in memory.

[0347] Figure 28 The logic and hardware architecture can be integrated into Figure 1-10 In the systems, processors, and architectures disclosed in [the document]. For example, Figure 28 The logic / hardware architecture within can execute at least part or all of the processes or APIs 300, 400, 500, 600, 700, 800, 900, 1000 and / or related to Figure 11-43 The process is described. In at least one embodiment, Figure 28 The systems or apparatus disclosed herein cause a processor to execute an application programming interface (API) to decompress and store information in one or more storage locations specified by a user. In at least one embodiment, Figure 28The disclosed system or apparatus causes a processor to execute instructions to decompress information based at least in part on one or more instructions of one or more decompression algorithms. In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 The described process, including at least part or all of one or more hardware decompression circuits, allows a processor to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, this is achieved by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about... Figure 11-43 In the described process, at least part or all of one or more hardware decompression circuits may be part of a data transmission module (e.g., a copy engine), and the decompression circuits decompress the data when it is transmitted to them. In at least one embodiment, by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding Figure 11-43 At least part or all of the process described in the text Figure 28 The disclosed system or apparatus divides compressed data into multiple parts, wherein each part is decompressed in parallel using multiple decompression circuits. In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause one or more hardware decompression circuits to decompress data compressed using known algorithms (e.g., deflate, LZ4, and Snappy). In at least one embodiment, by executing processes 300, 400, 500, 600, 700, 800, 900, 1000, and / or about Figure 11-43 In at least part or all of the described process, the processor executes instructions that cause the data transfer module (e.g., a replication engine) to decompress the data using one or more hardware decompression circuits when the data is transferred to the replication engine. In at least one embodiment, this is achieved by executing logic processes 300, 400, 500, 600, 700, 800, 900, 1000 and / or regarding... Figure 11-43 At least part or all of the process described Figure 28 The system or apparatus disclosed herein receives instructions for dividing compressed data into multiple parts, wherein, in response to receiving the instructions, multiple decompression circuits are used to decompress each of the multiple parts in parallel.

[0348] Figure 29A streaming multiprocessor (“SM”) 2900 according to at least one embodiment is shown. In at least one embodiment, the SM 2900 is Figure 28 SM 2814. In at least one embodiment, SM 2900 includes, but is not limited to, instruction cache 2902; one or more scheduler units 2904; register file 2908; one or more processing cores (“cores”) 2910; one or more special function units (“SFUs”) 2912; one or more load / store units (“LSUs”) 2914; interconnect network 2916; shared memory / Level 1 (“L1”) cache 2918; and any suitable combination thereof. In at least one embodiment, the work allocation unit schedules tasks to execute on a general-purpose processing cluster (“GPC”) of parallel processing units (“PPUs”), and each task is assigned to a specific data processing cluster (“DPC”) within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SMs 2900. In at least one embodiment, scheduler unit 2904 receives tasks from the work allocation unit and manages instruction scheduling for one or more thread blocks assigned to the SM 2900. In at least one embodiment, scheduler unit 2904 schedules thread blocks to execute as thread bundles of parallel threads, wherein each thread block is assigned at least one thread bundle. In at least one embodiment, each thread bundle executes a thread. In at least one embodiment, scheduler unit 2904 manages multiple different thread blocks, assigns thread bundles to different thread blocks, and then dispatches instructions from multiple different cooperative groups to various functional units (e.g., processing core 2910, SFU 2912, and LSU 2914) in each clock cycle. In at least one embodiment, SM 2900 includes one or more thread block clusters, wherein thread block clusters can provide local programming control with a larger granularity than a single thread block of a single streaming multiprocessor (SM). In at least one embodiment, thread block clusters (also referred to as “clusters”) enable multiple thread blocks running concurrently across streaming multiprocessors to synchronously and cooperatively acquire, exchange, or otherwise use data.

[0349] In at least one embodiment, a "cooperative group" can refer to a programming model used to organize groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling richer and more efficient parallel decompositions. In at least one embodiment, the cooperative startup API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, the API of a conventional programming model provides a single, simple construct for synchronizing cooperative threads: a barrier across all threads in a thread block (e.g., the `syncthreads()` function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than that of thread blocks and synchronize within the defined groups to achieve higher performance, design flexibility, and software reuse in the form of a set of group-wide functional interfaces. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at the sub-block and multi-block granularity and perform set operations, such as synchronizing threads within the cooperative group. In at least one embodiment, the sub-block granularity is as small as that of a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing library and utility functions to be safely synchronized in their local environment without having to make assumptions about convergence. In at least one embodiment, the cooperative group primitives enable new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across the entire thread block mesh.

[0350] In at least one embodiment, dispatch unit 2906 is configured to send instructions to one or more functional units, and scheduler unit 2904 includes, but is not limited to, two dispatch units 2906 that enable two different instructions from the same thread bundle to be dispatched in each clock cycle. In at least one embodiment, each scheduler unit 2904 includes a single dispatch unit 2906 or additional dispatch units 2906.

[0351] In at least one embodiment, each SM 2900 includes, but is not limited to, a register file 2908 that provides a set of registers for functional units of the SM 2900. In at least one embodiment, the register file 2908 is partitioned between each functional unit, thereby allocating a dedicated portion of the register file 2908 for each functional unit. In at least one embodiment, the register file 2908 is partitioned between different thread bundles executed by the SM 2900, and the register file 2908 provides temporary storage for operands connected to data paths of functional units. In at least one embodiment, each SM 2900 includes, but is not limited to, a plurality of L processing cores 2910. In at least one embodiment, the SM 2900 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 2910. In at least one embodiment, each processing core 2910 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, which includes, but is not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing core 2910 includes, but is not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores and 8 tensor cores.

[0352] In at least one embodiment, the tensor core is configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in the processing core 2910. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs matrix multiplication and accumulation operations D = A×B + C, where A, B, C, and D are 4×4 matrices.

[0353] In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating-point matrices, and accumulation matrices C and D are either 16-bit or 32-bit floating-point matrices. In at least one embodiment, the Tensor Core performs 32-bit floating-point accumulation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations to obtain a full-precision product, which is then accumulated with other intermediate multiplications using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the Tensor Core is used to perform matrix operations on larger two-dimensional or higher-dimensional matrices composed of these smaller components. In at least one embodiment, an API (such as the CUDA-C++ API) exposes specialized matrix loading, matrix multiplication and accumulation, and matrix storage operations to efficiently utilize the Tensor Core from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the thread bundle level interface assumes a 16×16 matrix spanning all 32 thread bundle threads.

[0354] In at least one embodiment, each SM 2900 includes, but is not limited to, M SFUs 2912 that perform special functions (e.g., attribute evaluation, inverse square root, etc.). In at least one embodiment, the SFUs 2912 include, but are not limited to, tree traversal units configured to traverse hierarchical tree data structures. In at least one embodiment, the SFUs 2912 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture units are configured to load texture maps (e.g., a 2D array of texture pixels) from memory and sample the texture maps to produce sampled texture values ​​for use by a shader program executed by the SM 2900. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 2918. In at least one embodiment, the texture units use mip-maps (e.g., texture maps with different levels of detail) to implement texture operations (such as filtering operations). In at least one embodiment, each SM 2900 includes, but is not limited to, two texture units.

[0355] In at least one embodiment, each SM 2900 includes, but is not limited to, N LSUs 2914 that implement load and store operations between the shared memory / L1 cache 2918 and the register file 2908. In at least one embodiment, each SM 2900 includes, but is not limited to, an interconnect network 2916 that connects each functional unit to the register file 2908, and the LSUs 2914 that connect to both the register file 2908 and the shared memory / L1 cache 2918. In at least one embodiment, the interconnect network 2916 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 2908 and to connect the LSUs 2914 to memory locations in both the register file 2908 and the shared memory / L1 cache 2918.

[0356] In at least one embodiment, the shared memory / L1 cache 2918 is an array of on-chip memory that, in at least one embodiment, allows data storage and communication between the SM 2900 and the primitive engine, as well as between threads within the SM 2900. In at least one embodiment, the shared memory / L1 cache 2918 includes, but is not limited to, a storage capacity of 128KB and is located on the path from the SM 2900 to the partition unit. In at least one embodiment, the shared memory / L1 cache 2918 is used for cache reads and writes. In at least one embodiment, one or more of the shared memory / L1 cache 2918, the L2 cache, and the memory are backup storage.

[0357] In at least one embodiment, combining data caching and shared memory functionality into a single memory block provides improved performance for both types of memory access. In at least one embodiment, the capacity is used by programs that do not use shared memory or is used as a cache; for example, if shared memory is configured to use half its capacity, texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 2918 enables the shared memory / L1 cache 2918 to be used as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, a simpler configuration can be used compared to graphics processing when configured for general-purpose parallel computing. In at least one embodiment, a simpler programming model is created by bypassing fixed-function GPUs. In at least one embodiment, in a general-purpose parallel computing configuration, the work allocation unit directly allocates and distributes blocks of threads to the DPC. In at least one embodiment, threads within a block execute the same program, using unique thread IDs in computation to ensure each thread produces a unique result, using an SM 2900 to execute the program and perform computations, using shared memory / L1 cache 2918 for communication between threads, and using an LSU 2914 to read and write global memory via shared memory / L1 cache 2918 and memory partitioning units. In at least one embodiment, when configured for general-purpose parallel computing, the SM 2900 writes commands to the scheduler unit 2904 that can be used to start new work on the DPC. In at least one embodiment, the SM 2900 includes one or more distributed shared memories (or distributed shared memory), enabling direct SM-to-SM operations, such as loading, storing, and executing atomic operations across memory blocks shared by multiple SMs.

[0358] In at least one embodiment, the SM 2900 includes one or more asynchronous execution functions, including a Tensor Memory Accelerator (TMA) unit that can transfer data blocks between global memory and shared memory. In at least one embodiment, one or more processors use or ac...

Claims

1. A processor, comprising: One or more circuits, said one or more circuits for executing an application programming interface (API) to decompress information and store it in one or more storage locations indicated by the user.

2. The processor of claim 1, further comprising a replication engine having data transmission circuitry facilitating data transmission between a source and a destination, wherein a portion of the replication engine is designated for performing decompression.

3. The processor of claim 1, wherein the information to be decompressed is compressed using at least one of the deflate compression algorithm, the LZ4 compression algorithm, or the Snappy compression algorithm.

4. The processor of claim 1, wherein the API decompresses information at least in part by transmitting compressed data to hardware circuitry dedicated solely to performing decompression.

5. The processor of claim 1, wherein the information is divided into multiple parts and distributed in multiple decompression circuits, the multiple decompression circuits performing decompression on each of the multiple parts in parallel.

6. The processor of claim 1, wherein the one or more circuits further execute an API to allocate the memory at the storage location based at least in part on an identification of whether the memory at the storage location indicated by the user is capable of storing the decompressed information.

7. The processor of claim 1, wherein the API enables the information to be decompressed at least in part by identifying whether the processor includes one or more decompression circuits for decompressing the information.

8. A system comprising: One or more processors having one or more circuits for executing an application programming interface (API) to decompress information and store it in one or more storage locations indicated by a user.

9. The system of claim 8, wherein the one or more processors further comprises a replication engine having data transmission circuitry that facilitates data transmission between a source and a destination, wherein a portion of the replication engine is designated to perform decompression.

10. The system of claim 8, wherein the information to be decompressed is compressed using at least one of the deflate compression algorithm, the LZ4 compression algorithm, or the Snappy compression algorithm.

11. The system of claim 8, wherein the API decompresses information at least in part by transmitting compressed data to hardware circuitry dedicated solely to performing decompression.

12. The system of claim 8, wherein the information is divided into multiple parts and distributed in multiple decompression circuits, the multiple decompression circuits performing decompression on each of the multiple parts in parallel.

13. The system of claim 8, wherein the one or more circuits further execute an API to allocate the memory at the storage location based at least in part on an identification of whether the memory at the storage location indicated by the user can store the decompressed information.

14. The system of claim 8, wherein the API enables the information to be decompressed at least in part by identifying whether the processor includes one or more decompression circuits for decompressing the information.

15. A method comprising: Execute the application programming interface (API) to decompress the information and store it in one or more storage locations specified by the user.

16. The method of claim 15, further comprising: The information to be decompressed is transmitted to a copy engine, which has a data transmission circuit that facilitates data transmission between the source and the destination. as well as The information is decompressed using a portion of the copy engine designated for performing the decompression.

17. The method of claim 15, further comprising: Identify whether the processor includes one or more decompression circuits; as well as The information is decompressed using the decompression circuit.

18. The method of claim 15, further comprising: Identify whether the memory at one or more storage locations is capable of storing the decompressed information; as well as Allocate the memory at one or more storage locations to receive the decompressed information.

19. The method of claim 15, wherein the information to be decompressed is compressed using at least one of the deflate compression algorithm, the LZ4 compression algorithm, or the Snappy compression algorithm.

20. The method of claim 15, further comprising: The information to be compressed is divided into multiple parts; The multiple components are distributed across multiple decompression circuits; as well as Each of the plurality of parts is decompressed in parallel using the plurality of decompression circuits.

Images