Microsystem module

Abstract

The invention belongs to the technical field of processor chip design, and particularly discloses a microsystem module which is mainly based on a multi-core DSP (digital signal processor) and a high-performance FPGA (field programmable gate array) dual-processor architecture, and comprises a multi-core DSP, an FPGA processor, a program memory, a data memory, an electronic resume memory and a reset chip, the core 1 and the core 2 are respectively connected with a program memory, the core 1 is connected with a data memory, and the core 1 is connected with other cores in the multi-core DSP processor; the FPGA processor is connected with a program memory and an electronic resume memory; and the reset chip is used for providing reset delay time and realizing under-voltage protection and timed monitoring of the system. According to the invention, the circuit architecture is subjected to heterogeneous integration through the SIP technology, the product performance can be improved, the system power consumption can be reduced, the system function density can be improved, the development requirements of miniaturization and light weight of intelligent electronic equipment can be met, the design cost can be reduced, and the development period can be shortened.

Description

Technical Field

[0001] This invention belongs to the field of processor chip design technology, and specifically discloses a microsystem module, which is mainly based on a dual-processor architecture of multi-core DSP and high-performance FPGA. Background Technology

[0002] With the increasing demand for real-time, large-scale data processing in fields such as radar, guidance, and satellite remote sensing, the application of high-performance, highly integrated information processing circuits is growing. The heterogeneous collaboration of multi-core DSPs and high-performance FPGAs effectively meets these characteristics and needs. The multi-core DSP provides large-scale parallel computing capabilities for signal processing algorithms, while the FPGA provides millions of gate-level logic units for data flow control and peripheral interface management. This architecture separates computation from control, improves resource utilization, and is widely used in various types of intelligent electronic systems, including real-time image processing and radar signal processing.

[0003] However, traditional PCB-level discrete component designs occupy a large amount of board space, making it difficult to achieve high integration and miniaturization of the system. In addition, even when using the same circuit architecture, the hardware and software adaptability and compatibility of the circuit are poor due to differences in product design requirements and design ideas, which increases design costs and design cycle. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention proposes a microsystem module comprising a multi-core DSP processor, an FPGA processor, a program memory, a data memory, an electronic history memory, and a reset chip. Cores 1 and 2 of the multi-core DSP processor are interconnected with the FPGA processor. Cores 1 and 2 are each connected to a program memory, and core 1 is connected to a data memory. Core 1 is also connected to the other cores in the multi-core DSP processor. The FPGA processor connects to both the program memory and the electronic history memory. The reset chip provides a reset delay time to enable system undervoltage protection and timing monitoring.

[0005] Furthermore, the FPGA processor has a configuration bank, an HR bank, an HP bank, and an MGT bank. The configuration bank and a dedicated pin are connected to a program memory, and the HR bank has pins connected to an electronic history memory.

[0006] Furthermore, the power supplies for the multi-core DSP processor, FPGA processor, program memory, data memory, electronic history memory, and reset chip are all independent of each other and are led out to the outside of the module package for external power supply.

[0007] Furthermore, the program memory is FLASH program memory, the data memory is SDRAM data memory, and the electronic record memory is EEPROM memory.

[0008] Furthermore, a high-temperature ceramic substrate is used for encapsulation.

[0009] Furthermore, a metal cover plate is attached to the ceramic tube shell.

[0010] Furthermore, a single-cavity, single-sided flat structure is adopted, with all bare chips positioned on the front side of the ceramic housing.

[0011] Furthermore, the multi-core DSP processor or FPGA processor is located in the center of the casing or near the interface.

[0012] Furthermore, the decoupling capacitors are placed near the power supply pins of the chip.

[0013] Furthermore, the back of the casing is sealed using a column-mounting method.

[0014] This invention integrates circuit architecture heterogeneously through SIP technology, which can improve product performance, reduce system power consumption, and increase system functional density, thereby meeting the development needs of miniaturization and lightweighting of intelligent electronic devices. At the same time, it reduces design costs, shortens development cycles, and meets the development ideas of generalization and modularization, which is conducive to the standardization and promotion of various miniaturized intelligent electronic devices. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structural composition of the present invention; Figure 2 This is a schematic diagram of the internal bare chip layout of the present invention; Figure 3 This is a block diagram of the internal circuit connection of a specific embodiment of the present invention; Figure 4 This is a perspective view of the external shape of the present invention; Figure 5 This is a side view of the external shape of the present invention. Detailed Implementation

[0016] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0017] In a specific embodiment of the present invention, an information processing SIP microsystem module based on a dual-processor architecture of multi-core DSP and high-performance FPGA is provided. Using SIP packaging technology, the minimum system such as multi-core DSP processor, high-performance FPGA processor, program memory, data memory, electronic history memory and reset chip are heterogeneously integrated to realize information processing and control of intelligent electronic devices, so as to achieve the goal of small size, high computing power and high reliability.

[0018] like Figure 1 As shown, within the SIP microsystem module, multiple bare dies are directly interconnected, integrating a multi-core DSP processor and its configuration FLASH program memory, SDRAM data memory, FPGA programmable processor and its configuration FLASH program memory, electronic history memory, and reset chip.

[0019] A multi-core DSP processor primarily provides high-speed data processing and instruction interaction, possessing multi-core parallel processing capabilities and inter-core data interaction capabilities. Core 1 and Core 2 achieve high-speed collaborative operation between the two processors through interconnection with the FPGA (such as the EMIF interface). This leverages the high efficiency of the DSP in fixed-point and floating-point operations while utilizing the FPGA to implement customizable logic and peripheral expansion.

[0020] Two FLASH program memories are used, one externally connected to core 1 and the other externally connected to core 2, enabling cores 1 and 2 to support FLASH boot mode. One SDRAM data memory is connected to core 1 to cache data. Other cores communicate with and boot from core 1 via the DSP processor's internal bus (such as the HPI interface), and are loaded through core 1 when needed. The interfaces of the multi-core DSP processor to the outside of the package mainly include: clock signal, configuration interface, test signal interface, reset signal interface, timer interface (which can be multiplexed as a GPIO port), JTAG debug interface, and power interface.

[0021] An FPGA programmable processor primarily implements functions such as system management, communication control, and interface expansion. It features a configuration bank, HR bank, HP bank, and MGT bank. The FPGA processor's configuration bank and dedicated pins connect to a FLASH program memory, with the FPGA acting as the master boot device.

[0022] In addition, the FPGA also has an EEPROM memory that can be used to record electronic history information such as the number of power-ups and power-up time of the product. The FPGA processor is interconnected with the DSP processor cores 1 and 2 to complete data and instruction interaction with the DSP. The I / O ports of the remaining banks are brought out outside the package for interface expansion. The interfaces brought out of the FPGA package mainly include: clock signal, configuration interface, reset signal interface, HR BANK I / O port, HP BANK I / O port, MGT BANK I / O port, JTAG debug interface, and power interface.

[0023] This invention's module incorporates a reset chip, providing stable reset delay time, system undervoltage protection, and timed monitoring for the microsystem. The chip's manual reset (MR) port, delay port, and reset output port are all exposed externally to the package. The reset time is configurable, and the system reset can be flexibly designed according to different application requirements.

[0024] In this invention, the power supplies for all DSP processors, FPGA processors, FLASH memory, SDRAM memory, and reset chips within the module are independent and led out to the outside of the module package, supporting external power supply. The module integrates a certain number of capacitors, compatible with energy storage, filtering, and decoupling, reducing power supply coupling and ripple noise, ensuring stable and reliable operation of the microsystem power network.

[0025] This invention encapsulates a dual-processor architecture's minimum circuit system into a microsystem module using SiP (System-in-Package) technology. The module packaging employs a high-temperature ceramic substrate and pillar mounting method, providing excellent hermeticity and reliability. A metal cover plate is attached to the ceramic housing for heat dissipation of critical components. The SiP microsystem internally uses eight bare chips of seven different types, along with several resistors and capacitors. The structure adopts a single-cavity, single-sided flat-layout design. All bare chips are arranged on the front side of the ceramic housing to reduce height. The bare chip layout is as follows: Figure 2 As shown.

[0026] Based on function and signal flow, the core processor is placed in the center of the package or near critical interfaces to reduce signal transmission delay and wiring length. Resistors are placed close to the chip based on function and connection to corresponding pins, while decoupling capacitors are placed near the chip's power pins. Pillars are used on the back of the package to reduce the risk of thermal fatigue failure due to the weight of the ceramic substrate.

[0027] This invention includes a large number of differential signals, high-speed signals, some single-ended control signals, clock signals, and power and ground. The BGA pin assignment distributes differential signals, high-speed signals, and clock signals in the peripheral area, while sufficient ground is arranged around each differential pair to provide both return paths and isolation. Differential signals and single-ended control signals of the same group are located in the same area. Other, smaller numbers of single-ended signals and power supplies are routed using proximity, selecting the nearest ball for lead-out. The power supply design uses a large-area plane and is arranged according to the voltage and current magnitudes, and the current-carrying capacity of the vias and balls.

[0028] In a specific embodiment of the present invention, such as Figure 3 As shown, a quad-core DSP processor FT-Q6713J / 500E with its BPI FLASH program memory configured for core 1 and core 2, an SDRAM data memory, an FPGA processor JFM7K325T with its configured QSPI FLASH program memory, an EEPROM memory, and a reset chip are packaged into an information processing SIP microsystem module.

[0029] The module is packaged in a CCGA841 package. The package structure consists of a ceramic housing, a ceramic housing cavity, a metal cover, and solder pillars. Its dimensions are 30mm*30mm*5.91mm, and it weighs approximately 19g. The pin pitch is 1mm. See the package diagram for details. Figure 4 , Figure 5 As shown.

[0030] The pin layout of the module encapsulation is shown in Table 1.

[0031] Table 1 External pinouts of a specific embodiment of the present invention This invention achieves minimal system heterogeneous integration for information processing, and is suitable for intelligent electronic devices that require high performance, high integration, and high reliability.

[0032] This invention includes a multi-core DSP processor and its FLASH program memory, SDRAM data memory, an FPGA programmable processor and its configuration FLASH program memory, EEPROM electronic history memory, and a reset chip. This allows the board-level schematic and PCB to only require designing the peripheral clock circuit, interface circuit, and power supply for this module, reducing design difficulty and risk, and shortening the design cycle.

[0033] This invention employs SiP (System-in-Package) technology to encapsulate the minimum system for information processing within a standard hermetically sealed ceramic package, resulting in excellent reliability. It not only solves the problem of limited PCB layout space but also effectively reduces crosstalk and transmission delay between high-speed signals due to the internal interconnection of most signals and shorter interconnections. This achieves high performance, high integration, and high reliability at the system level.

[0034] This invention can be widely applied to small-size, high-density intelligent electronic devices, enabling high-speed information processing, high-speed computation of large amounts of data, high-speed interaction of control commands, control via multiple communication interfaces, and flexible expansion via multiple interfaces. It features high integration, high performance, and high reliability. Specifically: 1. High integration: Compared with board-level discrete component design, this invention solves the layout constraint problem, reducing PCB layout space by about 60%~70% and significantly reducing the overall board weight. The board-level schematic and PCB design are simple, reducing the design difficulty and risk of the product and shortening the design cycle.

[0035] 2. High Performance: The hardware architecture of this invention can meet the high-computation and high-resource application requirements of most intelligent electronic devices. Because key signals are interconnected internally within modules with shorter wiring, problems such as coupling, crosstalk, and transmission delay between high-speed signals are effectively reduced, significantly lowering system power consumption.

[0036] 3. High Reliability: The present invention uses ceramic encapsulation, which has excellent sealing performance and can protect the internal chip from the influence of external environment such as moisture, dust and other contaminants. At the same time, the ceramic encapsulation material is extremely stable in terms of heat, chemicals and mechanics and has good heat dissipation performance, making it suitable for use in various harsh environments.

[0037] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A microsystem module, characterized in that, It includes a multi-core DSP processor, an FPGA processor, a program memory, a data memory, an electronic history memory, and a reset chip. Core 1 and Core 2 of the multi-core DSP processor are interconnected with the FPGA processor. Core 1 and Core 2 are each connected to a program memory. Core 1 is connected to a data memory and is connected to the other cores in the multi-core DSP processor. The FPGA processor is connected to the program memory and the electronic history memory. The reset chip is used to provide a reset delay time to realize system undervoltage protection and timed monitoring.

2. A microsystem module according to claim 1, characterized in that, The FPGA processor has a configuration bank, an HR bank, an HP bank, and an MGT bank. The configuration bank and a dedicated pin are connected to a program memory, while the HR bank has pins connected to an electronic history memory.

3. A microsystem module according to claim 1, characterized in that, The power supplies for the multi-core DSP processor, FPGA processor, program memory, data memory, electronic history memory, and reset chip are all independent and led out to the outside of the module package for external power supply.

4. A microsystem module according to claim 1, characterized in that, The program memory is FLASH program memory, the data memory is SDRAM data memory, and the electronic record memory is EEPROM memory.

5. A microsystem module according to claim 1, characterized in that, High-temperature ceramic substrates are used for encapsulation.

6. A microsystem module according to claim 5, characterized in that, A metal cover plate is attached to the ceramic tube shell.

7. A microsystem module according to claim 5, characterized in that, It adopts a single-cavity, single-sided flat structure, with all bare chips placed on the front of the ceramic housing.

8. A microsystem module according to claim 5, characterized in that, Multi-core DSP processors or FPGA processors are located in the center of the casing or near the interface.

9. A microsystem module according to claim 5, characterized in that, The decoupling capacitor is placed near the power supply pin of the chip.

10. A microsystem module according to claim 5, characterized in that, The back of the casing is sealed using a column-mounting method.

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