Novel verification method for low-power-consumption verification of MCU (Microprogrammed Control Unit) chip

Abstract

The invention discloses a novel MCU chip low-power-consumption verification verification method, which comprises the following steps: S1, simulating an initial power-down state of a chip according to a UPF file, simulating power-on reset through a verification platform, and performing use case configuration according to a low-power-consumption scene of the chip to enable a processor to enter a sleep state; s2, adding an SV checker file in the verification platform, and judging the state of a subsystem through log information printed in the SV checker file during low-power-consumption verification of the chip; s3, in the deep sleep mode, the output end of the power gate control module uses an isolation unit to maintain the determined level output; when the subsystem is powered down, a signal of a power-down domain is changed into an x state and is changed into a clamping value after passing through the isolation unit, and a stable level is output. According to the method, the efficiency and correctness of low-power-consumption verification of the chip are further improved.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and specifically to a novel verification method for low-power MCU chip verification. Background Technology

[0002] In modern chip design, low-power verification is a crucial step in ensuring that chips operate efficiently in real-world applications. With the proliferation of electronic devices, especially mobile devices and Internet of Things (IoT) devices, battery life and power management have become paramount. Low-power verification not only extends battery life but also improves device performance, reduces heat generation, and enhances user experience. Therefore, optimizing power consumption and conducting rigorous low-power verification are essential during chip design and manufacturing.

[0003] However, existing traditional power consumption verification methods rely on complex simulation tools and a large amount of manual intervention, requiring significant time and resources, and are inefficient and prone to errors. For example, low-power design strategies typically include clock gating, power gating, and power compression. Low-power verification needs to ensure that the chip's functionality is not affected when it enters a low-power mode. We need to configure stimuli in software to put the system into sleep mode, observe the transitions of the finite state machine in power control, and check the clock enable operations before and after power-on / power-off. These can usually only be checked from simulation waveforms. There are many similar checks, which makes our chip low-power verification work very complex and tedious. Therefore, it is essential to develop an automated and intelligent low-power verification method. Summary of the Invention

[0004] To address the aforementioned issues, the purpose of this invention is to propose a novel verification method for low-power MCU chips. This method verifies the low-power MCU chip verification results simply by adding an SV checker file to monitor internal signals, thus simplifying the tedious process of reading verification results during chip verification.

[0005] This was achieved through the following technical solutions: A novel verification method for low-power MCU chip verification includes the following steps: S1. Simulate the chip's initial power-down state based on the UPF file, and simulate power-on reset through the verification platform. Then, configure test cases according to the chip's low-power scenario to put the processor into a sleep state. When the test case configuration scenario is a light sleep mode, the verification platform simulates the generation of a wake-up stimulus signal, the subsystem jumps from light sleep to wake-up state, and the processor recovers from sleep state to normal state. When the test case configuration scenario is a deep sleep mode, the verification platform simulates the generation of a wake-up stimulus signal, the subsystem jumps from deep sleep to wake-up state, and the processor recovers from sleep state to normal state. S2. Add an SV checker file to the verification platform. When performing low-power chip verification, when the SV checker file... When the low-power indicator signal "sleeping" goes high in the log information printed in the checker file, it indicates that the subsystem has entered a shallow sleep mode. When the low-power indicator signal "sleeping" goes low, it indicates that the subsystem has been woken up from the shallow sleep mode. S3. In deep sleep mode, the output of the power gating module uses an isolation unit to maintain a defined output level. When the subsystem loses power, the signal in the power-down domain becomes an "x-state," which, after passing through the isolation unit, becomes a clamping value, outputting a stable level and eliminating "x-state" interference. This invention's method can further improve the efficiency and correctness of chip verification.

[0006] Preferably, in step S1, after the processor recovers from sleep mode to normal mode, it will either restart or continue executing instructions from the previously saved instruction address. By restarting the processor or continuing execution from the previously saved instruction address after the processor recovers to normal mode, the continuity and accuracy of program execution can be ensured.

[0007] Preferably, in step S2, the SV checker file is used to check the clock shutdown status in light sleep mode and the isolation value in deep sleep mode by printing log information. By adding the SV checker file to the verification platform, the low-power verification results can be verified.

[0008] Preferably, in step S2, after the subsystem enters the light sleep mode, upon triggering the next rising edge of the clock, it is determined whether the clock enable signal for detecting the subsystem status is turned off and whether the clock signal is controlled by the clock enable signal. If the verification result does not meet expectations, log information indicating an error is printed. Checking the low-power verification result through log information further improves verification efficiency.

[0009] Preferably, in step S2, after the subsystem is reawakened, it is checked whether the corresponding clock enable signal is normally turned on and whether the clock signal is normal, and the verification result is checked through log information to see if it meets expectations. Checking the verification result through log information simplifies the tedious process of reading verification results in chip verification.

[0010] Preferably, in step S2, the log information is used to indicate whether the waveform results of each detection signal are consistent with the expected results of the corresponding clock enable signal and clock signal. Printing the log information can improve the efficiency of verification.

[0011] Preferably, in step S3, in the verification platform, after the subsystem enters deep sleep mode, it monitors whether the clamp values ​​output by the power_on enable signal and the isolate control signal are consistent with the expected values. If they are inconsistent, it prints log information indicating an error. By monitoring whether the clamp values ​​output by the power_on enable signal and the isolate control signal are consistent with the expected values, the low-power verification results can be checked more accurately.

[0012] Preferably, in step S3, the isolation unit is used to force-clamp the output to a defined safe logic value when the subsystem loses power. The isolation unit prevents the logic of other parts that are not powered off from being affected when the power is turned off.

[0013] The beneficial effects of this invention compared to the prior art are: The technical solution of this invention proposes a method to verify the low-power verification results of MCU chips by simply adding SV checker files to monitor internal signals. This simplifies the tedious process of reading verification results in chip verification, reduces manual intervention, and further improves the efficiency and accuracy of chip verification. Attached Figure Description

[0014] Figure 1 A flowchart of a verification method for low-power verification of a novel MCU chip; Figure 2 This is a signal timing diagram for light sleep mode; Figure 3 This is a timing diagram of signals during deep sleep. Detailed Implementation

[0015] The following will refer to the appendices in the embodiments of the present invention. Figures 1-3 The technical solutions in the embodiments of the present invention will be described in detail below.

[0016] like Figure 1The diagram shows a flowchart of a novel low-power verification method for MCU chips. First, the initial power-down state of the chip is simulated based on a UPF file, and then a power-on reset is simulated using a verification platform. Next, test cases are configured according to the chip's low-power scenarios to put the processor into a sleep state. When the test case configuration scenario is a light sleep mode, the verification platform simulates a wake-up stimulus signal, causing the subsystem to transition from light sleep to wake-up, and the processor to return to normal operation. When the test case configuration scenario is a deep sleep mode, the verification platform simulates a wake-up stimulus signal, causing the subsystem to transition from deep sleep to wake-up, and the processor to return to normal operation. An SV checker file is added to the verification platform; during low-power verification, the subsystem state is determined by the log information printed in the SV checker file. In deep sleep mode, the output of the power gating module uses an isolation unit to maintain a defined output level. When the subsystem loses power, the signal in the power-down domain becomes an "x" state, which, after passing through the isolation unit, becomes a clamp value, outputting a stable level, thereby further improving the efficiency and correctness of the low-power verification. UPF stands for Unified Power Activation. Format, or Uniform Power Format, is a language standard used to describe the intended power consumption of a chip; SV checker, short for SystemVerilogchecker, is a code file written in the SystemVerilog language used to check the correctness of design behavior.

[0017] The method specifically includes the following steps: S1. Simulate the initial power-down state of the chip according to the UPF file, and simulate power-on reset through the verification platform. Then, configure test cases according to the low-power scenario of the chip to put the processor into a sleep state. When the test case configuration scenario is light sleep mode, the verification platform simulates the generation of a wake-up stimulus signal. After the state machine of the power management unit receives the wake-up stimulus signal, the subsystem jumps from light sleep to wake-up state, the processor recovers from sleep state to normal state, and restarts or continues to execute instructions from the previously saved instruction address to perform subsequent operations, completing one light sleep process. When the test case configuration scenario is deep sleep mode, the verification platform simulates the generation of a wake-up stimulus signal. After the state machine of the power management unit receives the wake-up stimulus signal, the subsystem jumps from deep sleep to wake-up state, the processor recovers from sleep state to normal state, and restarts or continues to execute instructions from the previously saved instruction address to perform subsequent operations. At the same time, after the chip is powered on, according to the parameter configuration defined in the UPF file, power is restored to the power-down subsystem to complete one deep sleep process.

[0018] S2. Add an SV checker file to the verification platform. When performing low-power verification of the chip, if the low-power indicator signal sleeping signal in the log information printed in the SV checker file goes high, it indicates that the subsystem has entered a shallow sleep mode. If the low-power indicator signal sleeping signal goes low, it indicates that the subsystem has been woken up from the shallow sleep mode.

[0019] In this embodiment, in step S2, when determining the use case configuration scenario mode, the SV checker file is written. The SV checker file is used to check the clock shutdown status in the light sleep mode and the isolation value in the deep sleep mode by printing log information. The log information is used to indicate whether the waveform results of each detection signal are consistent with the expected results of the corresponding clock enable signal and clock signal. By adding the SV checker file, the verification results of low power consumption can be verified, thereby improving the efficiency of verification.

[0020] like Figure 2 The diagram shows the signal timing in light sleep mode. The timing diagrams of each signal in the diagram represent the signal level changes of the subsystem when entering and exiting light sleep mode. Among them, Clock is the system clock signal, which is a periodically changing square wave signal used to synchronize timing components in the verification platform; sleeping is a low power indicator signal used to determine the current state of the subsystem; uart_clk_en is an arbitrary clock enable signal used to control whether the corresponding clock signal uart_clk is valid; xxx_clk_en and xxx_clk represent the level changes of the other clock enable signals and the corresponding clock signals, respectively.

[0021] In this embodiment, in step S2, after the subsystem enters a light sleep mode, when triggered by the next rising edge of the clock, it is determined whether the clock enable signal for detecting the subsystem status is turned off and whether the clock signal is controlled by the clock enable signal. If the clock enable signal is turned off and the clock signal is controlled by the clock enable signal, the verification result meets expectations, and log information indicating correctness is printed. If the clock enable signal is not turned off and the clock signal is not controlled by the clock enable signal, the verification result does not meet expectations, and log information indicating error is printed. When the subsystem is reawakened, it is checked whether the corresponding clock enable signal is normally turned on and whether the clock signal is normal, and the verification result is checked through the log information to see if it meets expectations. This invention can check whether the verification result meets expectations through only the log information, simplifying the tediousness of reading the verification result in chip verification work and further improving the verification efficiency.

[0022] S3. When performing isolation value checks in deep sleep mode, the output of the power gating module uses an isolation unit to maintain a defined output level. When the subsystem is powered down in deep sleep mode, the signal in the power-down domain will become an x-state. After passing through the isolation unit, it will become a clamping value, outputting a stable level to eliminate x-state interference. The isolation unit is used to force the output to a defined safe logic value when the subsystem is powered down, so as to prevent the logic of other parts that are not powered down from being affected when the power is turned off.

[0023] like Figure 3 The diagram shows the signal timing in deep sleep mode. The timing diagrams of each signal in the diagram represent the level changes of the power_on enable signal and the isolate control signal when they output clamp values ​​through the isolation unit in deep sleep mode. Among them, signal_befor_isolate represents the output state when the isolate control signal has not passed through the isolation unit, signal_after_isolate represents the output state when the isolate control signal has passed through the isolation unit, and power downindeced x state represents the unknown state caused by power failure.

[0024] In this embodiment, in step S3, when the subsystem enters deep sleep mode in the verification platform, the clamping values ​​output by the power_on enable signal and the isolate control signal are monitored to determine whether x-state interference has been eliminated. If the output clamping value is consistent with the expected value, a correct log message is printed, indicating that x-state interference has been eliminated. If the output clamping value is inconsistent with the expected value, an incorrect log message is printed, indicating that x-state interference has not been eliminated. Thus, by monitoring whether the clamping values ​​output by the power_on enable signal and the isolate control signal are consistent with the expected value, the low-power verification results can be checked more accurately.

[0025] In summary, this invention proposes a method to verify the low-power verification results of MCU chips by simply adding SV checker files to monitor internal signals. This simplifies the tedious process of reading verification results in chip verification, reduces manual intervention, and further improves the efficiency and accuracy of chip verification, demonstrating significant progress.

[0026] The above embodiments are merely illustrative of the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solutions based on the technical concept proposed in this invention shall fall within the scope of protection of this invention.

Claims

1. A novel verification method for low-power MCU chip verification, characterized in that, The method includes the following steps: S1. Simulate the initial power-down state of the chip based on the UPF file, and simulate power-on reset through the verification platform. Then, configure test cases according to the low-power scenario of the chip to put the processor into a sleep state. When the test case configuration scenario is light sleep mode, the verification platform simulates the generation of a wake-up stimulus signal, the subsystem jumps from light sleep to wake-up state, and the processor recovers from sleep state to normal state. When the test case configuration scenario is deep sleep mode, the verification platform simulates the generation of a wake-up stimulus signal, the subsystem jumps from deep sleep to wake-up state, and the processor recovers from sleep state to normal state. S2. Add an SV checker file to the verification platform. When performing low-power verification of the chip, if the low-power indicator signal sleeping signal in the log information printed in the SV checker file goes high, it indicates that the subsystem has entered a shallow sleep mode. If the low-power indicator signal sleeping signal goes low, it indicates that the subsystem has been woken up from the shallow sleep mode. S3. In deep sleep mode, the output of the power gating module uses an isolation unit to maintain a fixed output level. When the subsystem loses power, the signal in the power-down domain will become an x-state. After passing through the isolation unit, it will become a clamp value and output a stable level to eliminate x-state interference.

2. The verification method for low-power verification of a novel MCU chip according to claim 1, characterized in that, In step S1, after the processor recovers from sleep state to normal state, it will either restart or continue executing instructions from the previously saved instruction address.

3. The verification method for low-power verification of a novel MCU chip according to claim 1, characterized in that, In step S2, the SV checker file is used to check the clock shutdown status in light sleep mode and the isolation value in deep sleep mode by printing log information.

4. The verification method for low-power verification of a novel MCU chip according to claim 1, characterized in that, In step S2, after the subsystem enters the light sleep mode, when triggered by the next rising edge of the clock, it is determined whether the clock enable signal for detecting the subsystem status is turned off and whether the clock signal is controlled by the clock enable signal. If the verification result does not meet expectations, log information indicating an error is printed.

5. The verification method for low-power verification of a novel MCU chip according to claim 1, characterized in that, In step S2, after the subsystem is reawakened, check whether the corresponding clock enable signal is turned on normally and whether the clock signal is normal, and check whether the verification result meets expectations through log information.

6. The verification method for low-power verification of a novel MCU chip according to claim 1, characterized in that, In step S2, the log information is used to indicate whether the waveform results of each detection signal are consistent with the expected results of the corresponding clock enable signal and clock signal.

7. The verification method for low-power verification of a novel MCU chip according to claim 1, characterized in that, In step S3, on the verification platform, after the subsystem enters deep sleep mode, the clamping values ​​of the power_on enable signal and isolate control signal output are monitored to see if they are consistent with the expected values. If they are inconsistent, log information indicating an error is printed.

8. The verification method for low-power verification of a novel MCU chip according to claim 1, characterized in that, In step S3, the isolation unit is used to force the output to a defined safe logic value when the subsystem loses power.

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