Programmable wide-range input and output buffer

Abstract

The invention discloses a programmable wide-range input / output buffer, which is realized by adopting a 1.8 V I / O device based on a 28nm process node, and has excellent voltage compatibility and protocol adaptability. The buffer supports 37 mainstream level protocols in a range of 1.2 V to 3.3 V, and covers three types of interface standards of single-ended, pseudo-differential and fully-differential. Differentiated input structures are configured for single-ended protocols of different voltage intervals; multiplexing the same input buffer core for a pseudo-differential protocol and a low-voltage fully-differential protocol, and assisting with a reference voltage selection mechanism; designing a special high-voltage tolerance input unit for the high-voltage differential signal; and a unified reconfigurable driving module is constructed at the output end, so that single-ended / pseudo-differential output can be realized, and various fully differential signals can be synthesized through an anti-phase structure. The universality, the integration level and the flexibility of the FPGA I / O unit are remarkably improved, the area overhead and the power consumption of a chip are effectively reduced, and the FPGA I / O unit is suitable for wide application scenes of high-performance programmable logic devices.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a programmable wide-range input / output buffer. Background Technology

[0002] As semiconductor processes continue to shrink, advanced FPGA chips commonly employ deep submicron and even nanometer-level process nodes (such as 28nm and below), resulting in a continuous decrease in their core voltage (typically ≤1.0V), and a trend towards lower voltage for their supporting I / O devices (such as 1.8V). However, as a highly flexible and general-purpose platform, FPGAs often need to interconnect with various external devices. These devices use complex voltage standards, a wide voltage range (from 1.2V to 3.3V), and diverse protocols, including single-ended, pseudo-differential, and fully differential transmission methods.

[0003] Traditional FPGA I / O buffers often employ fixed-structure designs, making it difficult to simultaneously ensure high and low voltage compatibility and multi-protocol support. Designing a dedicated buffer for each protocol would drastically increase the I / O unit area and wiring complexity, hindering high-density integration. Furthermore, directly using high-voltage signals in advanced processes can easily lead to decreased device reliability or even damage. Therefore, there is an urgent need for a new I / O buffer architecture that can leverage the advantages of low-voltage devices while safely supporting protocols across a wide voltage range.

[0004] While some wide-voltage I / O designs exist in the current technology, they generally suffer from the following problems:

[0005] (1) The input structure is not properly categorized according to protocol type, resulting in low resource utilization;

[0006] (2) Lack of effective support for high-speed differential protocols such as TMDS and LVDS;

[0007] (3) The output driver structure is simple and cannot be flexibly reconfigured to adapt to different protocol requirements;

[0008] (4) Mode switching depends on external components and has a low degree of automation.

[0009] Therefore, how to improve the versatility, flexibility and integration of FPGA I / O units while ensuring device safety has become a key technical challenge that urgently needs to be solved. Summary of the Invention

[0010] This invention aims to address at least one of the technical problems existing in the prior art. To this end, this invention proposes a programmable wide-range input / output buffer, based on a 28nm process and using 1.8V I / O devices. This programmable wide-range input / output buffer can support 37 commonly used level protocols within the range of 1.2V–3.3V, covering three major categories of interface standards: single-ended, pseudo-differential, and fully differential, while ensuring device reliability. This significantly improves the versatility, flexibility, and integration efficiency of FPGA I / O units.

[0011] According to a first aspect of the present invention, a programmable wide-range input / output buffer is used in a field-programmable gate array (FPGA), characterized in that it is based on a 28nm CMOS process, employs 1.8VI / O devices, and supports 37 level protocols within a voltage range of 1.2V-3.3V, including single-ended protocols, pseudo-differential protocols, and fully differential protocols; wherein, the buffer comprises:

[0012] The input buffer module is configured to select one of several input structures based on the protocol type to receive and process input signals;

[0013] The output driver module is configured to reconstruct the output driver type according to the protocol type in order to generate and output signals that conform to the protocol requirements;

[0014] The control logic module, coupled to the input buffer module and the output driver module, is configured to receive a protocol selection signal from the FPGA configuration register and generate configuration instructions based on the protocol selection signal.

[0015] The control logic module first configures the input structure of the input buffer module based on the configuration instruction. The input buffer module processes the input signal and generates a buffered signal according to the selected input structure. Then, the control logic module configures the output drive type of the output drive module based on the same configuration instruction. The output drive module uses the buffered signal or an independent data signal to generate an output signal, thereby achieving multi-protocol compatibility and dynamic protocol switching.

[0016] The programmable wide-range input / output buffer according to embodiments of the present invention has at least the following beneficial effects: It possesses excellent voltage compatibility and protocol adaptability. It supports 37 mainstream level protocols within the 1.2V-3.3V range, covering three major interface standards: single-ended, pseudo-differential, and fully differential. Through systematic classification and electrical characteristic analysis, a hierarchical architecture design is proposed: differentiated input structures are configured for single-ended protocols in different voltage ranges; the same input buffer core is reused for pseudo-differential and low-voltage fully differential protocols, supplemented by a reference voltage selection mechanism; a dedicated high-voltage tolerant input unit is designed for high-voltage differential signals; and a unified reconfigurable driver module is constructed at the output end, enabling both single-ended / pseudo-differential output and the synthesis of various fully differential signals through an inverting structure. This solution significantly improves the versatility, integration, and flexibility of FPGA I / O units, effectively reducing chip area overhead and power consumption, and is suitable for a wide range of applications of high-performance programmable logic devices.

[0017] According to some embodiments of the present invention, the input buffer module includes:

[0018] The first input structure, used to support single-ended protocols below 1.8V, includes LVCMOS12, LVCMOS15, LVCMOS18 and MOBILE_DDR, and adopts a traditional CMOS input structure;

[0019] The second input structure is used to support single-ended protocols from 2.5V to 3.3V, including LVTTL, LVCMOS25, LVCMOS33 and PCI33_3, and adopts a voltage-enhanced input structure;

[0020] The third input structure, a shared differential input structure, is used to support pseudo-differential protocols and fully differential protocols below 2.5V, including HSUL_12, HSTL_I, HSTL_II, SSTL series, DIFF-HSTL, DIFF-SSTL and DIFF-MOBILE_DDR. Mode switching is achieved by selecting whether to connect the reference voltage VREF.

[0021] The fourth input structure is an independent high-voltage differential input structure used to support the TMDS_33 protocol, which has higher differential and common-mode voltage withstand capability.

[0022] According to some embodiments of the present invention, the output driving module includes:

[0023] A programmable single-ended driver unit is configured to generate an output level conforming to a single-ended or pseudo-differential classification protocol based on a protocol type selection signal, wherein the protocol type includes LVCMOS, LVTTL, HSTL, SSTL, and HSUL;

[0024] For protocols requiring differential output, the programmable single-ended driver unit is followed by an inverter to generate complementary signals, forming differential pairs to implement DIFF-HSTL, DIFF-SSTL, and DIFF-MOBILE_DDR protocols.

[0025] According to some embodiments of the present invention, the output driving module further includes a dedicated fully differential output driving unit for supporting standard differential protocols, including BLVDS_25, LVDS_25, MINI_LVDS_25, PPDS_25, RPDS_25 and TMDS_33. The dedicated fully differential output driving unit has low voltage swing, constant current source driving characteristics, and built-in termination matching resistor or adjustable bias circuit.

[0026] According to some embodiments of the present invention, the control logic module is further configured to automatically configure the input structure type of the input buffer module, the output drive strength of the output drive module, the reference voltage connection method and the terminal impedance matching parameters, and realize one-click protocol switching based on the protocol selection signal.

[0027] According to some embodiments of the present invention, the voltage-enhanced input structure employs cascaded gate or local thick oxide device technology, enabling a 1.8V device to safely carry input signals up to 3.3V, preventing device breakdown.

[0028] According to some embodiments of the present invention, the programmable single-ended drive unit has a multi-level drive intensity adjustment function, supporting output current settings of 4mA, 8mA, 12mA and 16mA to meet the signal drive requirements under different load conditions.

[0029] According to some embodiments of the present invention, the dedicated fully differential output drive unit adopts a constant current source structure for LVDS protocols, with an output current of 3.5mA. Paired with a 100Ω terminating resistor, it achieves a differential voltage swing of 350mV and supports Gbps-level high-speed data transmission.

[0030] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0031] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0032] Figure 1 This is a schematic diagram of the FPGA structure provided in an embodiment of the present invention;

[0033] Figure 2 An overall structural diagram of the programmable logic function block provided for the implementation of this invention;

[0034] Figure 3 This is a schematic diagram of a complete functional I / O module provided in an embodiment of the present invention. Detailed Implementation

[0035] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0036] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0037] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0038] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0039] To address the shortcomings of existing technologies, embodiments of the present invention provide a programmable wide-range input / output buffer based on a 28nm process and using 1.8V I / O devices. This buffer supports 37 commonly used level protocols within the range of 1.2V–3.3V, while ensuring device reliability. It covers three major categories of interface standards: single-ended, pseudo-differential, and fully differential, significantly improving the versatility, flexibility, and integration efficiency of FPGA I / O units.

[0040] Based on the aforementioned programmable wide-range input / output buffer, in order to meet the requirements of hierarchical, modular, and reconfigurable I / O buffers, the input protocols are divided into four categories according to the commonalities of their electrical characteristics, corresponding to four input structures. The buffer scheme is as follows:

[0041] 1. For single-ended protocols below 1.8V (LVCMOS12 / 15 / 18, MOBILE_DDR), a traditional CMOS input buffer is used, which has a simple structure and low power consumption;

[0042] 2. For 2.5V-3.3V single-ended protocols (LVTTL, LVCMOS25 / 33, PCI33_3), a voltage-enhanced input structure is adopted. Through cascaded transistors or local thick oxide layer design, 1.8V devices can safely withstand input voltages up to 3.3V.

[0043] 3. The pseudo-differential protocol (HSUL_12, HSTL_I / II, SSTL) and the fully differential protocol below 2.5V (DIFF-HSTL / SSTL / MOBILE_DDR) share a set of differential input cores. The reference voltage VREF (usually half of VCCO) is connected by a switch to achieve function multiplexing.

[0044] 4. For the TMDS_33 protocol, since its differential mode voltage can reach over 400mV and its common mode voltage is close to 1.7V, which is much higher than the conventional differential level, a dedicated high-voltage differential input structure is designed, which has a higher dynamic range and noise suppression capability.

[0045] Based on the above four protocols, a programmable single-ended driver unit is first constructed, which supports multiple levels of drive strength adjustment (such as 4 / 8 / 12 / 16mA) and can be adapted to various single-ended and pseudo-differential protocols such as LVCMOS, LVTTL, HSTL, and SSTL.

[0046] For protocols that require differential output (such as DIFF-HSTL and DIFF-SSTL), an inverting path is added to the single-ended driver to form a complementary output pair, eliminating the need for an additional dedicated differential driver.

[0047] For standard high-speed differential protocols (such as LVDS, BLVDS, TMDS, etc.), a dedicated fully differential output driver unit is configured, using constant current source drive and built-in termination matching or bias circuit to ensure high-speed signal integrity.

[0048] The control logic module receives the protocol selection signal from the FPGA configuration register and automatically configures parameters such as input buffer type, reference voltage access status, output drive strength, and whether the terminating resistor is enabled or not, realizing the function of "one-click switching" of protocols, which greatly simplifies user operation.

[0049] Preferably, another embodiment of the present invention provides a schematic diagram of an FPGA structure, such as... Figure 1As shown, each row of logic resources contains an equal number of stacked modules. By dividing the stacked modules, the large-scale FPGA is decomposed into thousands of small-scale devices, and then a hierarchical approach is used for divide-and-conquer. On the other hand, since these stackable modules containing different combinations of programmable logic resources have the same length and width dimensions and compatible module ports on the physical layout, the advantage of this architecture is that during the overall architecture design process, the number of rows and columns of stacked modules and the proportion of each type can be reasonably set according to the application field and requirements of the designed FPGA, so as to realize arbitrary expansion of chip scale and form a series of products with the same design platform but different application objects.

[0050] like Figure 2 As shown, Configurable Logic Blocks (CLBs) are connected to a switch matrix, and each CLB unit contains two slices. These two slices are not directly connected but have two independent carry chains. Therefore, the slice is an important module for implementing logical operations. It mainly consists of a function generator and registers that can be configured to multiple modes, as well as some necessary multiplexers, carry and control mechanisms. The function generator can be configured as a multi-input lookup table (LUT), a shift register chain (SRL), or a distributed memory (RAM, ROM) to implement specific logical functions; while the configurable registers can be configured for asynchronous / synchronous reset, set, and store functions.

[0051] Figure 3 The diagram shows a relatively complete I / O module, which includes input / output buffers, a programmable delay unit and its self-calibration circuit, input / output logic and a configurable input serial-to-parallel / output parallel-to-serial converter, a first-in-first-out unit, and a clock adjustment circuit.

[0052] This invention is based on a 28nm CMOS process node and uses a 1.8V I / O device library design. Its core objective is to achieve compatibility with 37 voltage level protocols within a single I / O buffer, spanning from 1.2V to 3.3V. The entire buffer consists of five core parts: an input buffer selection module, an output driver reconfiguration module, mode control logic, a reference voltage generation unit, and a termination matching network. Dynamic protocol switching is achieved through on-chip configuration registers.

[0053] The I / O power supply is isolated from the core power supply, and Vccio supports programmable adjustment from 1.2V to 3.3V to ensure that the input and output signals match the external system voltage. All I / O pins integrate ±8kV HBM and ±2kV MM protection circuits, with a 100Ω current-limiting resistor in series at the input and a clamping diode in parallel at the output.

[0054] For protocols such as LVCMOS12 (1.2V), LVCMOS15 (1.5V), LVCMOS18 (1.8V), and MOBILE_DDR (1.8V), a traditional CMOS input structure is adopted:

[0055] Circuit topology: P-type MOSFETs and N-type MOSFETs form a complementary input pair. The gate is directly connected to the external input signal IN, and the drain is connected to a Schmitt trigger for signal shaping. The output is buffered and then sent to the FPGA internal logic.

[0056] Threshold voltage adaptation: By adjusting the width-to-length ratio of the PMOS / NMOS, the input high and low level thresholds are made to meet the specifications of various protocols. For example, for LVCMOS12, Vih = 0.7 × Vccio (0.84V) and Vil = 0.3 × Vccio (0.36V).

[0057] For high-voltage protocols such as LVTTL (3.3V), LVCMOS25 (2.5V), LVCMOS33 (3.3V), and PCI33_3 (3.3V), a voltage-enhanced stacking structure is adopted.

[0058] NMOS transistors M1 and M2 are connected in series, and PMOS transistors M3 and M4 are connected in series. Voltage divider resistors R1 and R2 are connected to the power supply terminals to divide the 3.3V input voltage to 1.65V before driving the gates of the stacked transistors, ensuring that each device can withstand a voltage ≤1.8V. When the input IN = 3.3V, the gate of M1 is connected to Vccio through R1, and the gate of M2 is connected to the divided 1.65V. M1 is turned on, and M2 is turned off, with the input signal transmitted internally through the drain of M1. When IN = 0V, M3 / M4 are turned on according to similar logic to prevent overvoltage damage.

[0059] For high-speed differential signals (1.65V common-mode voltage, ±400mV differential-mode swing) of TMDS_33 (3.3V, HDMI / DVI protocol), a wide dynamic range differential input pair is designed: a low-noise operational amplifier (OPAMP) is used as the core comparator, the input stage uses a PMOS differential pair (to improve the common-mode rejection ratio), the tail current source is adjustable (100μA–500μA), supports data transmission up to 3.4Gbps, and meets the HDMI 2.0 standard.

[0060] Furthermore, a push-pull output stage is adopted, consisting of PMOS pull-up transistors and NMOS pull-down transistors. The drive strength switching (4mA / 8mA / 12mA / 16mA) is achieved by connecting multiple sets of transistors in parallel (e.g., 4 sets). The number of transistors on is configured through the mode control logic (300). For example, LVCMOS18 (1.8V) selects 2 sets of transistors (8mA), with an output swing of 0V–1.8V; LVTTL (3.3V) selects 4 sets of transistors (16mA), with an output swing of 0V–3.3V, and the rise / fall time (Tr / Tf) is controlled within 2ns–5ns.

[0061] The single-ended drive is extended to differential output through the inverter module to support protocols such as DIFF-LVCMOS and DIFF-HSTL. The input data DATA_IN is divided into two paths: positive (directly driving OUT+) and negative (driving OUT- via inverter). The inverter delay is matched (≤100ps) and the differential signal phase difference is ≤5°. It can be applied to the DIFF-LVCMOS25 protocol with OUT+ and OUT- output swing of 0V–2.5V, differential voltage swing ≥500mV, and supports 500Mbps data transmission.

[0062] For high-speed differential protocols (LVDS_25, BLVDS_25, TMDS_33, MINI_LVDS_25), a constant current source drive structure is designed, employing a 3.5mA constant current source. The current direction (inflow / outflow terminating resistor) is controlled by a switching transistor. The output differential pairs OUT+ and OUT- are connected to 100Ω on-chip terminating resistors, with a differential swing of 350mV (typical value), a common-mode voltage of 1.25V, and support for a maximum data rate of 2.5Gbps. Increasing the constant current source current to 6mA, terminating the resistor to 50Ω, and achieving a differential swing of 600mV meets the requirements of high-speed HDMI video transmission.

[0063] This invention, through FPGA hardware acceleration, a configurable interface, and a standardized adaptation layer, achieves efficient acquisition and unified output of data from multiple protocols, including Modbus RTU, DL / T645, and IEC61850, in a 110kV substation scenario. Test results show that the system conversion delay is ≤1ms, data accuracy is 100%, and it can stably support advanced applications such as demand-side response and load forecasting, verifying the engineering practicality and advanced nature of this invention.

[0064] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0065] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0066] The above is a detailed description of the preferred embodiments of this application. However, this application is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A programmable wide-range input / output buffer for field-programmable gate arrays, characterized in that, Based on 28nm CMOS technology and employing 1.8VI / O devices, it supports 37 voltage level protocols within a range of 1.2V-3.3V, including single-ended, pseudo-differential, and fully differential protocols; wherein, the buffer includes: The input buffer module is configured to select one of several input structures based on the protocol type to receive and process input signals; The output driver module is configured to reconstruct the output driver type according to the protocol type in order to generate and output signals that conform to the protocol requirements; The control logic module, coupled to the input buffer module and the output driver module, is configured to receive a protocol selection signal from the FPGA configuration register and generate configuration instructions based on the protocol selection signal. The control logic module first configures the input structure of the input buffer module based on the configuration instruction. The input buffer module processes the input signal and generates a buffered signal according to the selected input structure. Then, the control logic module configures the output drive type of the output drive module based on the same configuration instruction. The output drive module uses the buffered signal or an independent data signal to generate an output signal, thereby achieving multi-protocol compatibility and dynamic protocol switching.

2. The input / output buffer according to claim 1, characterized in that, The input buffer module includes: The first input structure, used to support single-ended protocols below 1.8V, includes LVCMOS12, LVCMOS15, LVCMOS18 and MOBILE_DDR, and adopts a traditional CMOS input structure; The second input structure is used to support single-ended protocols from 2.5V to 3.3V, including LVTTL, LVCMOS25, LVCMOS33 and PCI33_3, and adopts a voltage-enhanced input structure; The third input structure, a shared differential input structure, is used to support pseudo-differential protocols and fully differential protocols below 2.5V, including HSUL_12, HSTL_I, HSTL_II, SSTL series, DIFF-HSTL, DIFF-SSTL and DIFF-MOBILE_DDR. Mode switching is achieved by selecting whether to connect the reference voltage VREF. The fourth input structure is an independent high-voltage differential input structure used to support the TMDS_33 protocol, which has higher differential and common-mode voltage withstand capability.

3. The input / output buffer according to claim 1, characterized in that, The output driver module includes: A programmable single-ended driver unit is configured to generate an output level conforming to a single-ended or pseudo-differential classification protocol based on a protocol type selection signal, wherein the protocol type includes LVCMOS, LVTTL, HSTL, SSTL, and HSUL; For protocols requiring differential output, the programmable single-ended driver unit is followed by an inverter to generate complementary signals, forming differential pairs to implement DIFF-HSTL, DIFF-SSTL, and DIFF-MOBILE_DDR protocols.

4. The input / output buffer according to claim 1, characterized in that, The output drive module also includes a dedicated fully differential output drive unit for supporting standard differential protocols, including BLVDS_25, LVDS_25, MINI_LVDS_25, PPDS_25, RPDS_25 and TMDS_33. The dedicated fully differential output drive unit has low voltage swing, constant current source drive characteristics, and built-in termination matching resistor or adjustable bias circuit.

5. The input / output buffer according to claim 1, characterized in that, The control logic module is further configured to automatically configure the input structure type of the input buffer module, the output drive strength of the output drive module, the reference voltage connection method and the terminal impedance matching parameters, and realize one-click protocol switching based on the protocol selection signal.

6. The input / output buffer according to claim 2, characterized in that, The voltage-enhanced input structure employs cascaded gate or local thick oxide device technology, enabling a 1.8V device to safely carry input signals up to 3.3V, preventing device breakdown.

7. The input / output buffer according to claim 3, characterized in that, The programmable single-ended drive unit has a multi-level drive intensity adjustment function, supporting output current settings of 4mA, 8mA, 12mA and 16mA to meet the signal drive requirements under different load conditions.

8. The input / output buffer according to claim 4, characterized in that, The dedicated fully differential output driver unit adopts a constant current source structure for LVDS protocols, with an output current of 3.5mA. Paired with a 100Ω terminating resistor, it achieves a differential voltage swing of 350mV and supports Gbps-level high-speed data transmission.

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