Silicon carbide device and forming method thereof

Abstract

The invention provides a silicon carbide device and a forming method thereof, and the silicon carbide device comprises a silicon carbide substrate, the surface of which is provided with a silicon carbide epitaxial layer; the well regions are located in the silicon carbide epitaxial layer, and the top surfaces of the well regions are flush with the top surface of the silicon carbide epitaxial layer; the doped regions are located between the adjacent well regions, and the doping type of the doped regions is the same as that of the well regions; and the gate structure is located on the surface of the silicon carbide epitaxial layer, and the gate structure at least partially covers the well region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a silicon carbide device and a method for forming the same. Background Technology

[0002] Power electronic power converters, as crucial devices for electrical energy utilization, play a vital role in production and daily life. The core of a power electronic power converter is the power semiconductor device, which largely determines its performance. Currently, most power semiconductor devices are made of Si semiconductor material, whose characteristics are approaching their theoretical limits, becoming a bottleneck for the further development of power electronic power converters. Compared to Si power devices, SiC power devices possess superior characteristics: SiC power devices have higher switching speeds, can operate at higher junction temperatures, and can simultaneously achieve high frequency, high voltage, and high current. These characteristics can significantly improve the performance of semiconductor power converters, achieving higher energy conversion efficiency, higher power density, and reduced system costs.

[0003] Current SiC MOSFET structures still have drawbacks. Therefore, it is necessary to provide more effective and reliable technical solutions to improve the reliability and performance of SiC MOSFET structures. Summary of the Invention

[0004] This application provides a silicon carbide device and a method for forming the same, thereby improving the reliability and performance of SiC MOSFET structures.

[0005] One aspect of this application provides a method for forming a silicon carbide device, comprising: providing a silicon carbide substrate, wherein a silicon carbide epitaxial layer is formed on the surface of the silicon carbide substrate; forming a plurality of well regions in the silicon carbide epitaxial layer, wherein the top surface of the well regions is flush with the top surface of the silicon carbide epitaxial layer; forming doped regions between adjacent well regions, wherein the doping type of the doped regions is the same as the doping type of the well regions; and forming a gate structure on the surface of the silicon carbide epitaxial layer, wherein the gate structure at least partially covers the well regions.

[0006] In some embodiments of this application, the spacing between the well region and the doped region is 0.1 to 2 micrometers.

[0007] In some embodiments of this application, the cross-section of the region between the doped region and the well region is rectangular.

[0008] In some embodiments of this application, the cross-section of the region between the doped region and the well region is L-shaped.

[0009] In some embodiments of this application, the cross-section of the region between the doped region and the well region is stepped.

[0010] In some embodiments of this application, the well region surrounds both sides and part of the bottom of the doped region.

[0011] In some embodiments of this application, trenches are formed in the gate structure to separate the gate structure and expose at least a portion of the doped region.

[0012] Another aspect of this application provides a silicon carbide device, comprising: a silicon carbide substrate having a silicon carbide epitaxial layer formed on its surface; a plurality of well regions located in the silicon carbide epitaxial layer, the top surface of the well regions being flush with the top surface of the silicon carbide epitaxial layer; doped regions located between adjacent well regions, the doping type of the doped regions being the same as that of the well regions; and a gate structure located on the surface of the silicon carbide epitaxial layer, the gate structure at least partially covering the well regions.

[0013] In some embodiments of this application, the spacing between the well region and the doped region is 0.1 to 2 micrometers.

[0014] In some embodiments of this application, the cross-section of the region between the doped region and the well region is rectangular.

[0015] In some embodiments of this application, the cross-section of the region between the doped region and the well region is L-shaped.

[0016] In some embodiments of this application, the cross-section of the region between the doped region and the well region is stepped.

[0017] In some embodiments of this application, the well region surrounds both sides and part of the bottom of the doped region.

[0018] In some embodiments of this application, trenches are formed in the gate structure to separate the gate structure and expose at least a portion of the doped region.

[0019] This application provides a silicon carbide device and a method for forming the same, thereby improving the reliability and performance of SiC MOSFET structures. Attached Figure Description

[0020] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0021] in:

[0022] Figure 1This is a schematic diagram of the structure of the silicon carbide device described in some embodiments of this application;

[0023] Figure 2 This is a schematic diagram of the structure of the silicon carbide device described in other embodiments of this application;

[0024] Figure 3 This is a schematic diagram of the structure of the silicon carbide device described in other embodiments of this application;

[0025] Figure 4 This is a schematic diagram of the structure of the silicon carbide device described in other embodiments of this application;

[0026] Figure 5 This is a schematic diagram of the structure of a silicon carbide device described in other embodiments of this application. Detailed Implementation

[0027] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0028] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0029] Figure 1 The accompanying drawings are schematic diagrams illustrating the structure of silicon carbide devices according to some embodiments of this application. The structure of the silicon carbide devices according to the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0030] Some embodiments of this application provide a silicon carbide device, see reference. Figure 1 As shown, the system includes: a silicon carbide substrate 100, on which a silicon carbide epitaxial layer 110 is formed; a plurality of well regions 120 located in the silicon carbide epitaxial layer 110, the top surface of the well regions 120 being flush with the top surface of the silicon carbide epitaxial layer 110; doped regions 130 located between adjacent well regions 120, the doping type of the doped regions 130 being the same as the doping type of the well regions 120; and a gate structure 140 located on the surface of the silicon carbide epitaxial layer 110, the gate structure 140 at least partially covering the well regions 120.

[0031] The silicon carbide device described in this application embodiment is a SiC planar MOSFET. The silicon carbide substrate 100 is made of silicon carbide, and the silicon carbide epitaxial layer 110 is also made of silicon carbide. In some embodiments of this application, the silicon carbide substrate 100 and the silicon carbide epitaxial layer 110 may contain doped ions, such as N-type doped ions. The well region 120 may be formed by ion implantation in the silicon carbide epitaxial layer 110. The doping type of the well region 120 is opposite to that of the silicon carbide epitaxial layer 110, for example, P-type. The doping concentration of the well region 120 is higher than that of the silicon carbide epitaxial layer 110. There may be multiple well regions 120; only two are shown here as an example.

[0032] Continue to refer to Figure 1 As shown, an active region 121 and a body region 122 are formed in the well region 120. The top surfaces of the source region 121 and the body region 122 are flush with the top surface of the silicon carbide epitaxial layer 110, and the bottom surfaces of the source region 121 and the body region 122 are flush with but higher than the bottom surface of the well region 120. The doping concentration of the source region 121 and the body region 122 is greater than the doping concentration of the well region 120. The doping concentration of the source region 121 is opposite to that of the well region 120, for example, it is N-type. The doping concentration of the body region 122 is the same as that of the well region 120, for example, it is P-type.

[0033] In this embodiment, the doped region 130 is located between adjacent well regions 120, and the doping type of the doped region 130 is the same as that of the well region 120. The region between adjacent well regions 120 is the JFET region. The technical solution of this application sets the doped region 130 in the JFET region, and the well region 120 and the doped region 130 constitute the JFET structure. The size and implantation morphology of the JFET structure are adjusted so that the JFET is a normally on device and the maximum saturation current is a specific value. The MOS current needs to reach the drain terminal through the JFET channel. Thus, during the MOS short-circuit test, the maximum saturation current will be limited by the JFET saturation current. In addition, optionally, voltage control can be applied to the doped region 130 to improve both turn-off leakage and short-circuit.

[0034] In some embodiments of this application, the well region 120 and the doped region 130 have the same doping concentration. The doping concentration of the doped region 130 is, for example, 1E11 to 9E13 atoms per cubic meter.

[0035] Continue to refer to Figure 1 As shown, in some embodiments of this application, the spacing D between the well region 120 and the doped region 130 is 0.1 to 2 micrometers. Adjusting the spacing D can adjust the turn-off voltage of the JFET.

[0036] Continue to refer to Figure 1 As shown, in some embodiments of this application, the longitudinal cross-sectional shape of the well region 120 is rectangular, and the longitudinal cross-sectional shape of the doped region 130 is also rectangular, so that the cross-section of the region between the doped region 130 and the well region 120 is rectangular.

[0037] Continue to refer to Figure 1 As shown, in some embodiments of this application, a trench 150 is formed in the gate structure 140 to separate the gate structure 140 and expose at least a portion of the doped region 130. The trench 150 separates the gate structure 140 into two, which can reduce CrSS, improve short-circuit capability, and mitigate HTGB failure. The trench 150 also exposes at least a portion of the doped region 130, facilitating the subsequent formation of contact structures electrically connecting the doped region 130.

[0038] In some embodiments of this application, the silicon carbide device further includes: an interlayer dielectric layer covering the surface of the silicon carbide epitaxial layer 110, the gate structure 140, and filling the trench 150; a source metal layer covering the interlayer dielectric layer and penetrating the interlayer dielectric layer to electrically connect the source region 121 and the body region 122; a contact structure located at the position of the trench 150, penetrating the interlayer dielectric layer to electrically connect the doped region 130; and a drain metal layer located on the back side of the silicon carbide substrate 100. The contact structure and the source metal layer are avoided and not connected to each other.

[0039] Figure 2 This is a schematic diagram of the structure of a silicon carbide device according to other embodiments of this application. It should be noted that... Figure 2 The illustrated embodiments and Figure 1 The identical parts in the illustrated embodiments will not be described again; only the different parts will be explained.

[0040] refer to Figure 2 As shown, in some other embodiments of this application, the longitudinal cross-sectional shape of the well region 120 is rectangular, the longitudinal cross-sectional shape of the doped region 130 is convex, and the lower part of the doped region 130 extends below the well region 120, so that the cross-section of the region between the doped region 130 and the well region 120 is L-shaped.

[0041] Figure 3 This is a schematic diagram of the structure of a silicon carbide device according to other embodiments of this application. It should be noted that... Figure 3 The illustrated embodiments and Figure 1 The identical parts in the illustrated embodiments will not be described again; only the different parts will be explained.

[0042] refer to Figure 3As shown, in some other embodiments of this application, the longitudinal cross-sectional shape of the well region 120 is a rectangle with one corner missing, and the longitudinal cross-sectional shape of the doped region 130 is T-shaped, with both sides of the doped region 130 engaging with the sidewalls of the well region 120, thereby making the cross-section of the region between the doped region 130 and the well region 120 stepped.

[0043] Figure 4 This is a schematic diagram of the structure of a silicon carbide device according to other embodiments of this application. It should be noted that... Figure 4 The illustrated embodiments and Figure 1 The identical parts in the illustrated embodiments will not be described again; only the different parts will be explained.

[0044] refer to Figure 4 As shown, in some other embodiments of this application, the longitudinal cross-sectional shape of the well region 120 is a rectangle with a missing corner, and the longitudinal cross-sectional shape of the doped region 130 is rectangular, with both sides of the doped region 130 matching the missing corner of the well region 120, thereby making the well region 120 surround both sides and part of the bottom of the doped region 130.

[0045] Figure 5 This is a schematic diagram of the structure of a silicon carbide device according to other embodiments of this application. It should be noted that... Figure 5 The illustrated embodiments and Figure 4 The identical parts in the illustrated embodiments will not be described again; only the different parts will be explained.

[0046] refer to Figure 4 and Figure 5 As shown, Figure 4 The trench 150 exposes a portion of the doped region 130, while Figure 5 In this process, the trench 150 exposes the entire doped region 130.

[0047] This application provides a silicon carbide device that can improve the reliability and performance of SiC MOSFET structures.

[0048] Some embodiments of this application also provide a method for forming a silicon carbide device, see reference. Figure 1 As shown, the method includes: providing a silicon carbide substrate 100, on the surface of which a silicon carbide epitaxial layer 110 is formed; forming a plurality of well regions 120 in the silicon carbide epitaxial layer 110, the top surface of the well regions 120 being flush with the top surface of the silicon carbide epitaxial layer 110; forming doped regions 130 between adjacent well regions 120, the doping type of the doped regions 130 being the same as the doping type of the well regions 120; and forming a gate structure 140 on the surface of the silicon carbide epitaxial layer 110, the gate structure 140 at least partially covering the well regions 120.

[0049] The silicon carbide device described in this application embodiment is a SiC planar MOSFET. The silicon carbide substrate 100 is made of silicon carbide, and the silicon carbide epitaxial layer 110 is also made of silicon carbide. In some embodiments of this application, the silicon carbide substrate 100 and the silicon carbide epitaxial layer 110 may contain doped ions, such as N-type doped ions. The well region 120 may be formed by ion implantation in the silicon carbide epitaxial layer 110. The doping type of the well region 120 is opposite to that of the silicon carbide epitaxial layer 110, for example, P-type. The doping concentration of the well region 120 is higher than that of the silicon carbide epitaxial layer 110. There may be multiple well regions 120; only two are shown here as an example.

[0050] Continue to refer to Figure 1 As shown, an active region 121 and a body region 122 are formed in the well region 120, and the gate structure 140 also covers a portion of the source region 121. The top surfaces of the source region 121 and the body region 122 are flush with the top surface of the silicon carbide epitaxial layer 110, and the bottom surfaces of the source region 121 and the body region 122 are flush with and higher than the bottom surface of the well region 120. The doping concentration of the source region 121 and the body region 122 is greater than the doping concentration of the well region 120. The doping concentration of the source region 121 is opposite to that of the well region 120, for example, it is N-type. The doping concentration of the body region 122 is the same as that of the well region 120, for example, it is P-type.

[0051] In this embodiment, the doped region 130 is located between adjacent well regions 120, and the doping type of the doped region 130 is the same as that of the well region 120. The region between adjacent well regions 120 is the JFET region. The technical solution of this application sets the doped region 130 in the JFET region, and the well region 120 and the doped region 130 constitute the JFET structure. The size and implantation morphology of the JFET structure are adjusted so that the JFET is a normally on device and the maximum saturation current is a specific value. The MOS current needs to reach the drain terminal through the JFET channel. Thus, during the MOS short-circuit test, the maximum saturation current will be limited by the JFET saturation current. In addition, optionally, voltage control can be applied to the doped region 130 to improve both turn-off leakage and short-circuit.

[0052] In some embodiments of this application, the well region 120 and the doped region 130 have the same doping concentration. The doping concentration of the doped region 130 is, for example, 1E11 to 9E13 atoms per cubic meter.

[0053] Continue to refer to Figure 1 As shown, in some embodiments of this application, the spacing D between the well region 120 and the doped region 130 is 0.1 to 2 micrometers. Adjusting the spacing D can adjust the turn-off voltage of the JFET.

[0054] Continue to refer to Figure 1 As shown, in some embodiments of this application, the longitudinal cross-sectional shape of the well region 120 is rectangular, and the longitudinal cross-sectional shape of the doped region 130 is also rectangular, so that the cross-section of the region between the doped region 130 and the well region 120 is rectangular.

[0055] Continue to refer to Figure 1 As shown, in some embodiments of this application, a trench 150 is formed in the gate structure 140 to separate the gate structure 140 and expose at least a portion of the doped region 130. The trench 150 separates the gate structure 140 into two, which can reduce CrSS, improve short-circuit capability, and mitigate HTGB failure. The trench 150 also exposes at least a portion of the doped region 130, facilitating the subsequent formation of contact structures electrically connecting the doped region 130.

[0056] In some embodiments of this application, the silicon carbide device further includes: an interlayer dielectric layer covering the surface of the silicon carbide epitaxial layer 110, the gate structure 140, and filling the trench 150; a source metal layer covering the interlayer dielectric layer and penetrating the interlayer dielectric layer to electrically connect the source region 121 and the body region 122; a contact structure located at the position of the trench 150, penetrating the interlayer dielectric layer to electrically connect the doped region 130; and a drain metal layer located on the back side of the silicon carbide substrate 100. The contact structure and the source metal layer are avoided and not connected to each other.

[0057] refer to Figure 2 As shown, in some other embodiments of this application, the longitudinal cross-sectional shape of the well region 120 is rectangular, the longitudinal cross-sectional shape of the doped region 130 is convex, and the lower part of the doped region 130 extends below the well region 120, so that the cross-section of the region between the doped region 130 and the well region 120 is L-shaped.

[0058] refer to Figure 3 As shown, in some other embodiments of this application, the longitudinal cross-sectional shape of the well region 120 is a rectangle with one corner missing, and the longitudinal cross-sectional shape of the doped region 130 is T-shaped, with both sides of the doped region 130 engaging with the sidewalls of the well region 120, thereby making the cross-section of the region between the doped region 130 and the well region 120 stepped.

[0059] refer to Figure 4 As shown, in some other embodiments of this application, the longitudinal cross-sectional shape of the well region 120 is a rectangle with a missing corner, and the longitudinal cross-sectional shape of the doped region 130 is rectangular, with both sides of the doped region 130 matching the missing corner of the well region 120, thereby making the well region 120 surround both sides and part of the bottom of the doped region 130.

[0060] refer to Figure 4 and Figure 5 As shown, Figure 4 The trench 150 exposes a portion of the doped region 130, while Figure 5 In this process, the trench 150 exposes the entire doped region 130.

[0061] This application provides a silicon carbide device and a method for forming the same, which can improve the reliability and performance of SiC MOSFET structures.

[0062] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0063] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0064] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0065] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0066] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a silicon carbide device, characterized in that, include: A silicon carbide substrate is provided, wherein a silicon carbide epitaxial layer is formed on the surface of the silicon carbide substrate; A plurality of well regions are formed in the silicon carbide epitaxial layer, and the top surface of the well regions is flush with the top surface of the silicon carbide epitaxial layer; Doped regions are formed between adjacent well regions, wherein the doping type of the doped regions is the same as that of the well regions; A gate structure is formed on the surface of the silicon carbide epitaxial layer, the gate structure at least partially covering the well region.

2. The method for forming a silicon carbide device as described in claim 1, characterized in that, The spacing between the well region and the doped region is 0.1 to 2 micrometers.

3. The method for forming a silicon carbide device as described in claim 1, characterized in that, The cross-section of the region between the doped region and the well region is rectangular.

4. The method for forming a silicon carbide device as described in claim 1, characterized in that, The cross-section of the region between the doped region and the well region is L-shaped.

5. The method for forming a silicon carbide device as described in claim 1, characterized in that, The cross-section of the region between the doped region and the well region is stepped.

6. The method for forming a silicon carbide device as described in claim 1, characterized in that, The well region surrounds both sides and part of the bottom of the doped region.

7. The method for forming a silicon carbide device as described in claim 1, characterized in that, The gate structure has trenches that separate the gate structure and expose at least a portion of the doped region.

8. A silicon carbide device, characterized in that, include: A silicon carbide substrate, wherein a silicon carbide epitaxial layer is formed on the surface of the silicon carbide substrate; Several well regions are located in the silicon carbide epitaxial layer, and the top surface of the well regions is flush with the top surface of the silicon carbide epitaxial layer; A doped region is located between adjacent well regions, and the doping type of the doped region is the same as that of the well region. A gate structure is located on the surface of the silicon carbide epitaxial layer, and the gate structure at least partially covers the well region.

9. The silicon carbide device as described in claim 8, characterized in that, The spacing between the well region and the doped region is 0.1 to 2 micrometers.

10. The silicon carbide device as described in claim 8, characterized in that, The cross-section of the region between the doped region and the well region is rectangular.

11. The silicon carbide device as described in claim 8, characterized in that, The cross-section of the region between the doped region and the well region is L-shaped.

12. The silicon carbide device as described in claim 8, characterized in that, The cross-section of the region between the doped region and the well region is stepped.

13. The silicon carbide device as described in claim 8, characterized in that, The well region surrounds both sides and part of the bottom of the doped region.

14. The silicon carbide device as described in claim 8, characterized in that, The gate structure has trenches that separate the gate structure and expose at least a portion of the doped region.

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