Semiconductor device having floating electrode structure

Abstract

A semiconductor device is provided. The semiconductor device includes: a substrate; the drift region and the main body region are arranged at the upper part of the substrate; a field oxide layer on the drift region of the substrate; a gate electrode vertically overlapping a portion of the drift region and a portion of the body region, the gate electrode including a first extension on the field oxide layer; a source region on a first side of the gate electrode in the body region of the substrate; a drain region on a first side of the field oxide layer within the drift region of the substrate; and a floating electrode structure on the field oxide layer, the floating electrode structure including lower electrodes spaced apart from each other, an insulating layer covering top surfaces of the lower electrodes, and upper electrodes each vertically overlapping a portion of a corresponding one of the lower electrodes.

Description

Cross-reference to related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0134272, filed with the Korean Intellectual Property Office on October 2, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This application relates to a semiconductor device. Background Technology

[0003] With the development of the electronics industry and the demands of users, electronic devices are becoming increasingly compact, lightweight, and multifunctional. Correspondingly, the demand for power MOS transistors is also growing, whereas in the past, power MOS transistors were typically integrated with various semiconductor devices onto separate chips. As an example of a power MOS transistor, the laterally diffused metal-oxide-semiconductor (LDMOS) transistor is used as a semiconductor device capable of operating at high voltages. To achieve high-voltage operation, the LDMOS transistor needs to have a sufficient breakdown voltage. Summary of the Invention

[0004] This disclosure provides a semiconductor device with excellent electrical operation characteristics.

[0005] According to one aspect of this disclosure, a semiconductor device is provided. The semiconductor device includes: a substrate; a drift region and a body region formed on the upper portion of the substrate, wherein the drift region has a first conductivity type and the body region has a second conductivity type; a field oxide layer disposed on the drift region of the substrate; a gate electrode disposed on the substrate and vertically overlapping a portion of the drift region and a portion of the body region, the gate electrode including a first extension disposed on the field oxide layer; a source region disposed on a first side of the gate electrode in the body region of the substrate; a drain region disposed on a first side of the field oxide layer within the drift region of the substrate; and a floating electrode structure disposed on the field oxide layer between the gate electrode and the drain region, the floating electrode structure including: a plurality of lower electrodes spaced apart from each other along a first horizontal direction on a top upper surface of the field oxide layer; an insulating layer covering the top surface of the plurality of lower electrodes; and a plurality of upper electrodes vertically overlapping a portion of each of the plurality of lower electrodes on the insulating layer.

[0006] According to another aspect of this disclosure, a semiconductor device is provided. The semiconductor device includes: a substrate; a drift region and a body region formed on the upper portion of the substrate, wherein the drift region has a first conductivity type and the body region has a second conductivity type; a field oxide layer disposed on the drift region of the substrate; a gate electrode disposed on the substrate and arranged to vertically overlap a portion of the drift region and a portion of the body region; a source region disposed on a first side of the gate electrode in the body region of the substrate; a drain region disposed on a first side of the field oxide layer within the drift region of the substrate; a floating electrode structure disposed on the field oxide layer between the gate electrode and the drain region, the floating electrode structure including: a plurality of lower electrodes spaced apart from each other along a first horizontal direction on the top upper surface of the field oxide layer by a first spacing distance; a plurality of upper electrodes offset relative to each of the plurality of lower electrodes in the first horizontal direction, and the plurality of upper electrodes spaced apart from each other in the first horizontal direction by a second spacing distance equal to the first spacing distance; and an insulating layer disposed between the plurality of lower electrodes and the plurality of upper electrodes.

[0007] According to another aspect of this disclosure, a semiconductor device is provided. The semiconductor device includes: a flash memory cell disposed on a first region of a substrate; and a metal-oxide-semiconductor (MOS) transistor disposed on a second region of the substrate, wherein the MOS transistor includes a drift region and a body region formed in an upper portion of the substrate, the drift region having a first conductivity type and the body region having a second conductivity type; a field oxide layer disposed on the drift region of the substrate; a gate electrode disposed on the substrate and arranged to vertically overlap a portion of the drift region and a portion of the body region; a source region disposed on a first side of the gate electrode in the body region of the substrate; a drain region disposed on a first side of the field oxide layer within the drift region of the substrate; and a floating electrode structure disposed on the field oxide layer and between the gate electrode and the drain region, the floating electrode structure including: a plurality of lower electrodes disposed spaced apart on a top surface of the field oxide layer; an insulating layer covering the top surface of the plurality of lower electrodes; and a plurality of upper electrodes vertically overlapping a portion of each of the plurality of lower electrodes on the insulating layer. Attached Figure Description

[0008] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a schematic perspective view of a semiconductor device according to an embodiment;

[0010] Figure 2 It shows Figure 1 A cross-sectional view of a portion of the first region in the image;

[0011] Figure 3 It shows Figure 1A cross-sectional view of a portion of the second region;

[0012] Figure 4 yes Figure 3 A magnified view of part of EN in the image;

[0013] Figure 5 yes Figure 3 A schematic layout diagram of the floating electrode structure in the diagram;

[0014] Figure 6 This is a schematic diagram illustrating a method for driving a semiconductor device according to an embodiment;

[0015] Figure 7 This is a cross-sectional view of a semiconductor device according to an embodiment;

[0016] Figure 8 yes Figure 7 A magnified view of part of EN in the image;

[0017] Figure 9 This is a cross-sectional view of a semiconductor device according to an embodiment;

[0018] Figure 10 yes Figure 9 A magnified view of part of EN in the image;

[0019] Figure 11 This is a cross-sectional view of a semiconductor device according to an embodiment;

[0020] Figure 12 yes Figure 11 A magnified view of part of EN in the image;

[0021] Figure 13 This is a cross-sectional view of a semiconductor device according to an embodiment;

[0022] Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A and Figure 23B This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0023] Figure 1 This is a schematic perspective view of a semiconductor device 100 according to an embodiment. Figure 2 It shows Figure 1 A cross-sectional view of a portion of the first region R1 in the image, and Figure 3 It shows Figure 1 A cross-sectional view of a portion of the second region R2 in the diagram. Figure 4 yes Figure 3 Enlarged view of part EN in the image. Figure 5 yes Figure 3 A schematic layout diagram of the floating electrode structure 160 in the middle.

[0024] refer to Figures 1 to 5 The semiconductor device 100 may include a flash memory cell FC formed in a first region R1 of the substrate 110 and a metal-oxide-semiconductor (MOS) transistor HVTR formed in a second region R2 of the substrate 110.

[0025] Flash memory cells FC can be arranged on the first region R1 of substrate 110 and can form an embedded flash memory device.

[0026] Substrate 110 may include a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In some embodiments, a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate may be used as substrate 110.

[0027] A device isolation layer 122 can be formed on the substrate 110. In one embodiment, the device isolation layer 122 can be formed by oxidizing a portion of the substrate 110 using a localized oxidation of silicon (LOCOS) method. In other embodiments, the device isolation layer 122 can be formed by removing a portion of the substrate 110 to form a device isolation trench, and then filling the device isolation trench with silicon oxide.

[0028] The flash memory cell FC may include a tunnel insulating layer 132, a floating gate electrode 134, a barrier insulating layer 136 and a control gate electrode 138 arranged sequentially on a substrate 110.

[0029] In one embodiment, the tunnel insulating layer 132 may be disposed on the top surface of the substrate 110. In another embodiment, the tunnel insulating layer 132 may include silicon oxide.

[0030] In one embodiment, the floating gate electrode 134 may be disposed on the tunnel insulating layer 132. In another embodiment, the floating gate electrode 134 may comprise doped polysilicon.

[0031] In one embodiment, the barrier insulating layer 136 may be disposed on the top upper surface of the floating gate electrode 134. In another embodiment, the barrier insulating layer 136 may comprise silicon oxide or a high-k dielectric material. In some embodiments, the barrier insulating layer 136 may be conformally formed on both the top surface of the floating gate electrode 134 and the top surface of the substrate 110.

[0032] In some other embodiments, the barrier insulating layer 136 can be formed by oxidizing a portion of the floating gate electrode 134 in a localized oxidation of silicon (LOCOS) manner. In this case, the barrier insulating layer 136 can be disposed on the upper surface of the floating gate electrode 134, and optionally, an insulating pad can also be conformally disposed on the barrier insulating layer 136, the sidewalls of the floating gate electrode 134, and the top surface of the substrate 110.

[0033] In one embodiment, the control gate electrode 138 may be disposed on the barrier insulating layer 136. In some embodiments, the control gate electrode 138 may comprise doped polysilicon.

[0034] In one embodiment, a first spacer 142 may also be arranged on the sidewall of the floating gate electrode 134 and the sidewall of the control gate electrode 138. The first spacer 142 may include silicon nitride or silicon oxynitride.

[0035] The flash memory cell FC may also include a pair of impurity regions SD, which are disposed on both sides of the floating gate electrode 134 (or on both sides of the control gate electrode 138) and located on the upper part of the substrate 110. The pair of impurity regions SD may be the source region and the drain region of the flash memory cell FC.

[0036] In an implementation, the flash memory cell FC can be configured to store data such that electrons tunnel through a channel region defined on the substrate 110 by applying a voltage to the control gate electrode 138, and the electrons are stored in the floating gate electrode 134. Figure 2 The illustration shows a flash memory cell FC comprising only a floating gate electrode 134 and a control gate electrode 138 disposed between a pair of impurity regions SD. However, in some embodiments, multiple flash memory cells FC may form a memory string, and in this case, multiple gate stacks (each gate stack consisting of a floating gate electrode 134 and a control gate electrode 138) may be spaced apart between a pair of impurity regions SD.

[0037] The MOS transistor HVTR can be disposed on the second region R2 of the substrate 110. The MOS transistor HVTR may include a gate electrode 154 and a floating electrode structure 160 disposed on the second region R2 of the substrate 110.

[0038] A drift region 112 having a first conductivity type and a well region 114 having a second conductivity type can be disposed on a second region R2 of the substrate 110. The drift region 112 and the well region 114 can be arranged side by side in the lateral direction. A body region 116 having a second conductivity type can be disposed in the well region 114.

[0039] In some embodiments, the first conductivity type can be n-type, and the second conductivity type can be p-type. In this case, the MOS transistor HVTR can be referred to as an n-type lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor. In other embodiments, the first conductivity type can be p-type, and the second conductivity type can be n-type. In this case, the MOS transistor HVTR can be referred to as a p-type LDMOS transistor.

[0040] A field oxide layer 124 can be disposed on the drift region 112. The field oxide layer 124 can be formed by oxidizing a portion of the substrate 110 in a LOCOS manner. The field oxide layer 124 can be formed by oxidizing a portion of the substrate 110, and the top surface of the field oxide layer 124 can be disposed at a vertical height higher than the top surface of the substrate 110 adjacent to the field oxide layer 124.

[0041] Source region 118A and body contact region 118B can be arranged in the portion of body region 116 adjacent to the top surface of substrate 110. Source region 118A can be a region doped with a high concentration of impurities of a first conductivity type, and body contact region 118B can be a region doped with a high concentration of impurities of a second conductivity type. Source region 118A and body contact region 118B can be arranged adjacent to each other.

[0042] Drain region 118C may be disposed in the portion of drift region 112 adjacent to the top surface of substrate 110. In some embodiments, drain region 118C may be disposed on one side of field oxide layer 124. In some embodiments, drain region 118C may be a region doped with a high concentration of impurities of a first conductivity type.

[0043] A gate insulating layer 152 may be disposed on the top surface of the substrate 110. The gate insulating layer 152 may be disposed to overlap a portion of the body region 116 and a portion of the drift region 112. The gate insulating layer 152 may contact the sidewalls of the field oxide layer 124. In some embodiments, the gate insulating layer 152 may comprise silicon oxide.

[0044] A gate electrode 154 may be disposed on the gate insulating layer 152. The gate electrode 154 may be disposed to overlap with a portion of the body region 116 and a portion of the drift region 112. In some embodiments, the gate electrode 154 may comprise polysilicon.

[0045] In some embodiments, the gate electrode 154 may include a first extension E1. The first extension E1 may indicate a portion of the gate electrode 154 disposed on the top surface of the field oxide layer 124. That is, the first extension E1 may indicate a portion of the gate electrode 154 that vertically overlaps with the field oxide layer 124.

[0046] In some embodiments, the gate electrode 154 can be formed simultaneously with the control gate electrode 138 of the flash memory cell FC. For example, a second gate electrode layer 138L can be formed on the first region R1 and the second region R2 of the substrate 110 (see [link to documentation]). Figure 20A and Figure 20B Then, the second gate electrode layer 138L can be patterned using a mask pattern to form a control gate electrode 138 on the first region R1 and a gate electrode 154 on the second region R2.

[0047] The second spacer 144 can be disposed on any sidewall of the gate electrode 154. The second spacer 144 may include silicon nitride or silicon oxynitride.

[0048] The floating electrode structure 160 can be disposed on the field oxide layer 124. In some embodiments, the floating electrode structure 160 can be spaced apart from the gate electrode 154 in the first horizontal direction X. For example, the floating electrode structure 160 can be disposed spaced apart from the first extension E1 of the gate electrode 154 in the first horizontal direction X.

[0049] The floating electrode structure 160 may include a plurality of lower electrodes 162, an insulating layer 164, and a plurality of upper electrodes 166.

[0050] In some embodiments, the plurality of lower electrodes 162 may be spaced apart from each other in a first horizontal direction X. For example, the plurality of lower electrodes 162 may be spaced apart from each other to have a constant first spacing distance sd1. For example, two adjacent lower electrodes 162 of the plurality of lower electrodes 162 may be arranged to be spaced apart from each other by the first spacing distance sd1.

[0051] In some embodiments, the bottom surfaces of the plurality of lower electrodes 162 may be disposed on and in contact with the top surface of the field oxide layer 124. The top surfaces of the plurality of lower electrodes 162 may be disposed at the same vertical height. In some embodiments, each of the plurality of lower electrodes 162 may have a rectangular vertical cross-section.

[0052] In some embodiments, the plurality of lower electrodes 162 may include polycrystalline silicon.

[0053] In some embodiments, the insulating layer 164 may be disposed on the top surface and sidewalls of the plurality of lower electrodes 162. In some embodiments, such as Figure 3As shown, the insulating layer 164 can extend to the top surface of the field oxide layer 124.

[0054] In some configurations, the insulating layer 164 may include silicon oxide or a high-k dielectric material.

[0055] Multiple upper electrodes 166 can be arranged on the insulating layer 164 and can be arranged to be offset relative to multiple lower electrodes 162 in a first horizontal direction X. Here, the expression "arranged in the first horizontal direction X" and "offset" can mean arranged at predetermined distances. For example, the multiple upper electrodes 166 can be arranged on multiple lower electrodes 162 respectively, and the sidewall of each of the multiple upper electrodes 166 can be arranged at a position spaced apart from the sidewall of the corresponding lower electrode 162 along the first horizontal direction X. Each of the multiple upper electrodes 166 can vertically overlap a portion of each of the multiple lower electrodes 162.

[0056] In some embodiments, the plurality of upper electrodes 166 may be spaced apart from each other in a first horizontal direction X. For example, the plurality of upper electrodes 166 may be spaced apart from each other with a constant second spacing distance sd2, and the second spacing distance sd2 may be substantially equal to the first spacing distance sd1. For example, two adjacent upper electrodes 166 may be spaced apart from each other by a second spacing distance sd2 that is substantially the same as the first spacing distance sd1.

[0057] Here, the statement that the second spacing distance sd2 is essentially the same as the first spacing distance sd1 can mean that, taking into account the process errors or tolerances that may occur during the formation of the multiple lower electrodes 162 and multiple upper electrodes 166, they may have a difference of 5% or less or 10% or less relative to each other.

[0058] In some embodiments, each of the plurality of upper electrodes 166 may have an inverted L-shaped vertical cross-section. For example, as... Figure 3 As shown, each of the plurality of upper electrodes 166 may have a flat top surface and a bottom surface with a step (or height difference). Furthermore, each of the plurality of upper electrodes 166 may have a top surface arranged at the same vertical height. In some embodiments, the plurality of upper electrodes 166 may comprise polycrystalline silicon.

[0059] In some embodiments, each of the plurality of upper electrodes 166 may include a first portion P1 and a second portion P2. The first portion P1 may refer to a portion of the upper electrode 166 disposed on the top surface of the corresponding lower electrode 162. A first portion 164_1 of the insulating layer 164 may be disposed between the bottom surface of the first portion P1 and the lower electrode 162. The second portion P2 may refer to a portion of the upper electrode 166 disposed on the sidewall of the corresponding lower electrode 162. The second portion P2 may be integrally connected to the first portion P1. A second portion 164_2 of the insulating layer 164 may be disposed between the sidewall of the second portion P2 and the lower electrode 162, and between the bottom surface of the second portion P2 and the top surface of the field oxide layer 124.

[0060] In some embodiments, the top surface of the second part P2 may be arranged at the same vertical height as the top surface of the first part P1, while the bottom surface of the second part P2 may be arranged at a lower vertical height than the bottom surface of the first part P1.

[0061] In some embodiments, the sidewall of the second portion P2 may be spaced apart from the adjacent lower electrode 162 by a third spacing distance sd3 in the first horizontal direction X. The third spacing distance sd3 may be smaller than the first spacing distance sd1 or the second spacing distance sd2. In some embodiments, the third spacing distance sd3 may be in the range of 20% to 80%, 30% to 70%, or 40% to 60% of the first spacing distance sd1 or the second spacing distance sd2.

[0062] In some embodiments, since the plurality of upper electrodes 166 are arranged to be offset relative to the plurality of lower electrodes 162, a lower electrode 162 and a corresponding upper electrode 166 (e.g., a first electrode stack including a first lower electrode and a first upper electrode on the first lower electrode) can be arranged to be spaced apart from another lower electrode 162 adjacent thereto and another upper electrode 166 corresponding to that other lower electrode 162 (e.g., a second electrode stack including a second lower electrode and a second upper electrode on the second lower electrode) by a third spacing distance sd3. For example, the sidewall of the second portion P2 of another upper electrode (e.g., the second upper electrode) can be arranged to be spaced apart from the sidewall of the lower electrode (e.g., the first lower electrode) by a third spacing distance sd3. Therefore, even if the minimum spacing allowed by the design rules is a first spacing distance sd1 or a second spacing distance sd2, the first electrode stack and the second electrode stack can be spaced apart from each other by a third spacing distance sd3 smaller than the first spacing distance sd1 or the second spacing distance sd2.

[0063] In some embodiments, multiple lower electrodes 162 can be formed simultaneously during the formation of the floating gate electrode 134 of the flash memory cell FC. For example, a first gate electrode layer 134L can be formed on a first region R1 and a second region R2 of the substrate 110 (see [link to documentation]). Figure 18A and Figure 18B Then, a mask pattern is used to pattern the first gate electrode layer 134L to form a floating gate electrode 134 on the first region R1 and a plurality of lower electrodes 162 on the second region R2.

[0064] In some embodiments, multiple upper electrodes 166 can be formed simultaneously during the formation of the control gate electrode 138 of the flash memory cell FC. For example, a second gate electrode layer 138L can be formed on the first region R1 and the second region R2 of the substrate 110 (see [link to documentation]). Figure 20A and Figure 20B Then, the second gate electrode layer 138L can be patterned using a mask pattern to form a control gate electrode 138 on the first region R1 and a gate electrode 154 and a plurality of upper electrodes 166 on the second region R2.

[0065] According to the implementation, the gaps between multiple electrodes can be minimized without being limited by minimum design rules, and the electric field concentrated at the edge of the gate electrode 154 can be effectively dispersed through the coupling effect between the upper electrode 166 and the lower electrode 162, thereby enabling the semiconductor device 100 to have a high breakdown voltage. Furthermore, the floating electrode structure 160 can be formed simultaneously during the fabrication of the floating gate electrode 134 and the control gate electrode 138 of the embedded flash memory device. Accordingly, the number of process steps in fabricating the semiconductor device 100 can be reduced.

[0066] Figure 6 This is a schematic diagram illustrating a method for driving a semiconductor device 100 according to an embodiment.

[0067] refer to Figure 6 When the MOS transistor HVTR is turned on, the source voltage V_S can be applied to the source region 118A and the body contact region 118B, the drain voltage V_D can be applied to the drain region 118C, and the gate voltage V_G can be applied to the gate electrode 154. In this case, the floating electrode structure 160 can be configured to float without receiving a separate voltage.

[0068] According to the embodiment, since the floating electrode structure 160 is formed as a double-layer structure including multiple lower electrodes 162 and multiple upper electrodes 166, the gap between the multiple electrodes can be minimized without being limited by minimum design rules. Furthermore, the electric field concentration phenomenon between the gate electrode 154 and the drain region 118C can be mitigated or reduced by the additional coupling effect between the multiple lower electrodes 162 and the multiple upper electrodes 166. Therefore, the semiconductor device 100 can have an excellent or relatively high breakdown voltage.

[0069] For example, using reference Figure 6The described semiconductor device 100 was subjected to simulation testing. As a comparative example, a semiconductor device with a floating electrode structure including only a plurality of lower electrodes 162 was used.

[0070] Compared to the comparative example, the breakdown voltage of the semiconductor device according to the embodiment is improved, approximately 107% of the breakdown voltage of the semiconductor device according to the comparative example. Furthermore, the on-resistance of the semiconductor device according to the embodiment is reduced by approximately 13% compared to the on-resistance of the semiconductor device according to the comparative example. Therefore, by ensuring a predetermined breakdown voltage while simultaneously reducing resistance, an LDMOS device with improved operating speed can be realized.

[0071] Figure 7 This shows a cross-sectional view of the semiconductor device 100A according to an embodiment, and Figure 8 yes Figure 7 Enlarged view of part EN in the image.

[0072] refer to Figure 7 and Figure 8 The insulating layer 164 of the floating electrode structure 160 may be disposed only on the top surface and sidewall of the lower electrode 162. The insulating layer 164 may include a first portion 164_1 and a second portion 164_2, and the first portion 164_1 of the insulating layer 164 may be disposed between the bottom surface of the first portion P1 of the upper electrode 166 and the top surface of the lower electrode 162. The second portion 164_2 of the insulating layer 164 may be disposed between the sidewall of the second portion P2 of the upper electrode 166 and the sidewall of the lower electrode 162.

[0073] The insulating layer 164 may not be disposed between the top surface of the field oxide layer 124 and the bottom surface of the second portion P2 of the upper electrode 166, and the bottom surface of the second portion P2 of the upper electrode 166 may be in contact with the top surface of the field oxide layer 124.

[0074] Figure 9 This shows a cross-sectional view of the semiconductor device 100B according to an embodiment, and Figure 10 yes Figure 9 Enlarged view of part EN in the image.

[0075] refer to Figure 9 and Figure 10 The second portion P2 of each of the plurality of upper electrodes 166 may extend into the groove 124R formed above the field oxide layer 124, and the bottom surface of the second portion P2 may be arranged at a vertical height below the bottom surface of the plurality of lower electrodes 162.

[0076] In some embodiments, the flash memory cell FC can be formed during the formation of the plurality of lower electrodes 162 and insulating layer 164, or on the first region R1 (see [link to documentation]). Figure 2 During the process, some portions of the upper part of the field oxide layer 124 are removed to form a groove 124R above the field oxide layer 124. In this case, a portion of the plurality of upper electrodes 166, i.e. the bottom of the second portion P2, can be formed to fill the interior of the groove 124R.

[0077] In some embodiments, the top surface of the first portion P1 of the plurality of upper electrodes 166 may have a curved top surface, such that the top surface of the first portion P1 is arranged at a higher vertical height than the top surface of the second portion P2.

[0078] Figure 11 This shows a cross-sectional view of the semiconductor device 100C according to an embodiment, and Figure 12 yes Figure 11 Enlarged view of part EN in the image.

[0079] refer to Figure 11 and Figure 12 The floating electrode structure 160 may further include an edge electrode 162E disposed between a plurality of lower electrodes 162 and a gate electrode 154. The edge electrode 162E may be spaced apart from the plurality of lower electrodes 162 by a first spacing distance sd1. The top surface and sidewalls of the edge electrode 162E may be covered by an insulating layer 164, and the edge electrode 162E may be connected to and adjacent to the first extension E1 of the gate electrode 154, with the insulating layer 164 between the edge electrode 162E and the gate electrode 154.

[0080] The gate electrode 154 may also include a second extension E2. The second extension E2 may indicate a portion of the gate electrode 154 disposed on the top surface of the floating electrode structure 160 (e.g., the top surface of the edge electrode 162E). The second extension E2 may be disposed on the top surface of the edge electrode 162E and may be disposed at a higher vertical height than the first extension E1.

[0081] In some embodiments, the top surface of the second extension E2 may be arranged at the same vertical height as the top surfaces of the plurality of upper electrodes 166.

[0082] When semiconductor device 100C is turned on, the gate voltage V_G (see...) Figure 6 An electrode 154 can be applied to the gate electrode 154, and the edge electrode 162E can be floated.

[0083] Figure 13 This is a cross-sectional view of a semiconductor device 100D according to an embodiment.

[0084] refer to Figure 13The floating electrode structure 160 may include a plurality of lower electrodes 162, an insulating layer 164 disposed on the top surface and sidewalls of the plurality of lower electrodes 162 and filling the space between the plurality of lower electrodes 162, and a plurality of upper electrodes 166 disposed on the insulating layer 164.

[0085] In some embodiments, the insulating layer 164 may have a flat top while filling the space between the plurality of lower electrodes 162. In an example embodiment, the plurality of upper electrodes 166 may be arranged to be offset relative to the plurality of lower electrodes 162 in a first horizontal direction X. Each of the plurality of upper electrodes 166 may vertically overlap at least a portion of the plurality of lower electrodes 162.

[0086] In some implementations, such as Figure 13 As shown, an upper electrode 166 can be arranged to partially vertically overlap with two adjacent lower electrodes 162, and a lower electrode 162 can be arranged to partially vertically overlap with two adjacent upper electrodes 166.

[0087] In some embodiments, each of the plurality of lower electrodes 162 may have a rectangular vertical cross section, and each of the plurality of upper electrodes 166 may have a rectangular vertical cross section.

[0088] Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A and Figure 23B This is a cross-sectional view showing a method for manufacturing a semiconductor device 100 according to an embodiment.

[0089] refer to Figure 14A and Figure 14B The drift region 112 and the well region 114 can be formed by implanting impurity ions into the second region R2 of the substrate 110. In some embodiments, the drift region 112 can be formed by implanting a first conductivity type (e.g., n-type) impurity, and the well region 114 can be formed by implanting a second conductivity type (e.g., p-type) impurity.

[0090] refer to Figure 15A and Figure 15B Hard mask patterns M10 can be formed on a first region R1 and a second region R2 of the substrate 110, respectively. In some embodiments, the hard mask pattern M10 may include silicon nitride. The hard mask pattern M10 may include a first opening H1 and a second opening H2, wherein the first opening H1 is used to expose a portion of the top surface of the substrate 110 on the first region R1, and the second opening H2 is used to expose a portion of the top surface of the substrate 110 on the second region R2.

[0091] refer to Figure 16A and Figure 16B The top surface of the substrate 110 exposed by the first opening H1 and the second opening H2 can be oxidized to form a device isolation layer 122 and a field oxide layer 124 in the first opening H1 and the second opening H2, respectively.

[0092] In some embodiments, the oxidation process used to form the device isolation layer 122 and the field oxide layer 124 can be a thermal oxidation process or a plasma-assisted oxidation process.

[0093] In some embodiments, a portion of the substrate 110 is consumed during the formation of the device isolation layer 122 and the field oxide layer 124, such that the bottom surface of each of the device isolation layer 122 and the field oxide layer 124 can protrude from the substrate 110. For example, the portion of the top surface of the substrate 110 that contacts the device isolation layer 122 can be positioned at a lower vertical height than the portion of the top surface of the substrate 110 covered by the hard mask pattern M10.

[0094] refer to Figure 17A and Figure 17B The hard mask pattern M10 can be removed from the first region R1 and the second region R2.

[0095] refer to Figure 18A and Figure 18B A tunnel insulating layer 132 can be formed on a first region R1 of the substrate 110. For example, the tunnel insulating layer 132 can be formed using silicon oxide. In some embodiments, the tunnel insulating layer 132 can be formed by an oxidation process on the top surface of the substrate 110, or by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0096] Subsequently, a first gate electrode layer 134L can be formed on the first region R1 and the second region R2 of the substrate 110. In some embodiments, the first gate electrode layer 134L can be formed using polysilicon via CVD or ALD processes.

[0097] The first gate electrode layer 134L can be disposed on the tunnel insulating layer 132 and the device isolation layer 122 on the first region R1, and the first gate electrode layer 134L can be disposed on the top surface of the substrate 110 and the field oxide layer 124 on the second region R2.

[0098] refer to Figure 19A and Figure 19B A mask pattern can be formed on the first gate electrode layer 134L, and the first gate electrode layer 134L can be patterned using the mask pattern to form a floating gate electrode 134 on the first region R1 and a plurality of lower electrodes 162 on the second region R2.

[0099] In some embodiments, the plurality of lower electrodes 162 may be arranged to be spaced apart from each other by a first spacing distance sd1.

[0100] Subsequently, a barrier insulating layer 136 can be formed on the floating gate electrode 134 in the first region R1, an insulating layer 164 can be formed on the plurality of lower electrodes 162 in the second region R2, and a gate insulating layer 152 can be formed on the top surface of the substrate 110 in the second region R2.

[0101] In some embodiments, the barrier insulating layer 136 may include silicon oxide or a high-k dielectric material. In some embodiments, the insulating layer 164 may include silicon oxide or a high-k dielectric material. In some embodiments, the gate insulating layer 152 may include silicon oxide.

[0102] In some embodiments, the insulating layer 164 may be formed simultaneously with the process of forming the barrier insulating layer 136. In other embodiments, the process for forming the insulating layer 164 may be performed before or after the process of forming the barrier insulating layer 136.

[0103] In some embodiments, the gate insulating layer 152 may be formed simultaneously with the process of forming the barrier insulating layer 136. In other embodiments, the process for forming the gate insulating layer 152 may be performed before or after the process of forming the barrier insulating layer 136.

[0104] refer to Figure 20A and Figure 20B The second gate electrode layer 138L can be formed on the barrier insulating layer 136 on the first region R1, and the second gate electrode layer 138L can be formed on the gate insulating layer 152 and the insulating layer 164 on the second region R2.

[0105] In some embodiments, the second gate electrode layer 138L can be formed using polysilicon via CVD or ALD processes.

[0106] refer to Figure 21A and Figure 21BA mask pattern can be formed on the second gate electrode layer 138L. The second gate electrode layer 138L can be patterned by using the mask pattern as an etching mask. A control gate electrode 138 is formed on the first region R1, and a gate electrode 154 and a plurality of upper electrodes 166 are formed on the second region R2.

[0107] In some embodiments, the control gate electrode 138 may be formed on the barrier insulating layer 136 on the first region R1, and the gate electrode 154 may be formed on the gate insulating layer 152 on the second region R2.

[0108] In some embodiments, a plurality of upper electrodes 166 may be arranged on an insulating layer 164 and may be arranged to be offset relative to a plurality of lower electrodes 162 in a first horizontal direction X. The plurality of upper electrodes 166 may be spaced apart from each other in the first horizontal direction X by a second spacing distance sd2, which is substantially the same as the first spacing distance sd1. In some other embodiments, the second spacing distance sd2 may be greater than the first spacing distance sd1; and in some other embodiments, the second spacing distance sd2 may be less than the first spacing distance sd1.

[0109] In some embodiments, the sidewall of an upper electrode may be arranged to be spaced apart from the sidewall of a lower electrode by a third spacing distance sd3. The third spacing distance sd3 may be less than the first spacing distance sd1 or the second spacing distance sd2. Even if the minimum spacing distance allowed by the design rules is the first spacing distance sd1 or the second spacing distance sd2, a first electrode stack including a lower electrode and an upper electrode may be spaced apart from a second electrode stack including another lower electrode and another upper electrode by a third spacing distance sd3 less than the first spacing distance sd1 or the second spacing distance sd2.

[0110] refer to Figure 22A and Figure 22B A first spacer 142 can be formed on the sidewall of the control gate electrode 138 in the first region R1, a second spacer 144 can be formed on the sidewall of the gate electrode 154 in the second region R2, and a third spacer 146 can be formed on the sidewall of each of the plurality of upper electrodes 166.

[0111] refer to Figure 23A and Figure 23B The host region 116 can be formed by implanting impurity ions into the second region R2 of the substrate 110. In some embodiments, the host region 116 may be formed adjacent to one side of the gate electrode 154.

[0112] Then, the source region 118A, the body contact region 118B, and the drain region 118C can be formed by implanting impurity ions into the second region R2 of the substrate 110. In some embodiments, the source region 118A and the drain region 118C can be formed by implanting a first conductivity type impurity (e.g., an n-type impurity) into the substrate 110, and the body contact region 118B can be formed by implanting a second conductivity type impurity (e.g., a p-type impurity) into the substrate 110.

[0113] Subsequently, impurity ions can be implanted into the first region R1 of the substrate 110 to form the impurity region SD.

[0114] Semiconductor device 100 can be formed by performing the above process.

[0115] In the method of manufacturing the semiconductor device 100 according to the embodiment, the flash memory cell FC and the MOS transistor HVTR can be formed using the same process. For example, the floating gate electrode 134 of the flash memory cell FC and the lower electrode 162 of the MOS transistor HVTR can be formed in the same manufacturing process, and the control gate electrode 138 of the flash memory cell FC and the gate electrode 154 and upper electrode 166 of the MOS transistor HVTR can be formed in the same manufacturing process. Accordingly, the number of manufacturing processes for the semiconductor device 100 can be reduced.

[0116] Furthermore, the floating electrode structure 160 includes a plurality of lower electrodes 162 and a plurality of upper electrodes 166 offset relative to the plurality of lower electrodes 162. Accordingly, the gap between the plurality of electrodes can be minimized without being constrained by minimum design rules. Through the coupling effect between the lower electrodes 162 and the upper electrodes 166, the electric field concentrated at the edge of the gate electrode 154 can be effectively dispersed, thereby enabling the semiconductor device 100 to have a high breakdown voltage.

[0117] According to this disclosure, a floating electrode structure is disposed on a field oxide layer, and the floating electrode structure includes a plurality of lower electrodes and a plurality of upper electrodes offset relative to the plurality of lower electrodes. Accordingly, the gap between the plurality of electrodes can be minimized without being constrained by minimum design rules, and the electric field concentrated at the edge of the gate electrode can be effectively dispersed through the coupling effect between the upper and lower electrodes, thereby enabling the semiconductor device to have a high breakdown voltage. Furthermore, the floating electrode structure can be formed simultaneously during the fabrication of the floating gate electrode and the control gate electrode of the embedded flash memory device. Accordingly, the number of process steps in fabricating the semiconductor device can be reduced.

[0118] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of any claims that may be made. In a single implementation, specific features described in the context of a standalone implementation may also be combined. Conversely, different features described in a single implementation context may also be implemented individually in multiple implementations, or in appropriate sub-combinations. Furthermore, although features may be described above as functioning in certain combinations, in some cases one or more features may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

Claims

1. A semiconductor device, comprising: Substrate; A drift region and a body region are located on the upper part of the substrate, wherein the drift region has a first conductivity type and the body region has a second conductivity type; A field oxide layer is applied to the drift region of the substrate. A gate electrode is provided on the substrate and vertically overlaps with a portion of the drift region and a portion of the body region, the gate electrode including a first extension on the field oxide layer; The source region is located on the first side of the gate electrode in the main region of the substrate; A drain region, on a first side of the field oxide layer within the drift region of the substrate; and A floating electrode structure, situated on the field oxide layer between the gate electrode and the drain region, the floating electrode structure comprising: Multiple lower electrodes are spaced apart from each other along a first horizontal direction on the top surface of the field oxide layer. An insulating layer covers the top surface of the plurality of lower electrodes, and Multiple upper electrodes are located on the insulating layer, and each upper electrode vertically overlaps a portion of a corresponding lower electrode among the multiple lower electrodes.

2. The semiconductor device according to claim 1, wherein, Each of the plurality of lower electrodes has a rectangular vertical cross-section, and Each of the plurality of upper electrodes has an inverted L-shaped vertical cross-section.

3. The semiconductor device according to claim 1, wherein, Each of the plurality of upper electrodes includes: The first part is on the top surface of a corresponding lower electrode among the plurality of lower electrodes; and The second part is integrally connected to the first part on the sidewall of a corresponding lower electrode among the plurality of lower electrodes.

4. The semiconductor device according to claim 3, wherein, The top surface of the first part is coplanar with the top surface of the second part, and The vertical height of the bottom surface of the first part is higher than the vertical height of the bottom surface of the second part.

5. The semiconductor device according to claim 3, wherein, The plurality of lower electrodes includes a first lower electrode and a second lower electrode adjacent to the first lower electrode, and The plurality of upper electrodes includes a first upper electrode on the first lower electrode and a second upper electrode on the second lower electrode, and The first lower electrode and the second lower electrode are spaced apart by a first interval distance in the first horizontal direction. The first upper electrode and the second upper electrode are spaced apart by a second interval distance in the first horizontal direction, and The second interval distance is equal to the first interval distance.

6. The semiconductor device according to claim 3, wherein, The plurality of lower electrodes includes a first lower electrode and a second lower electrode adjacent to the first lower electrode, and The plurality of upper electrodes includes a first upper electrode on the first lower electrode and a second upper electrode on the second lower electrode, and The first lower electrode and the second lower electrode are spaced apart by a first interval distance in the first horizontal direction. The first upper electrode and the second upper electrode are spaced apart by a second interval distance in the first horizontal direction. The second upper electrode and the first lower electrode are spaced apart by a third interval distance in the first horizontal direction, and The third interval distance is less than the first interval distance or the second interval distance.

7. The semiconductor device according to claim 3, wherein, The bottom surface of each of the plurality of lower electrodes is in contact with the top surface of the field oxide layer. The first portion of the insulating layer lies between the bottom surface of the first portion of each of the plurality of upper electrodes and the top surface of each of the plurality of lower electrodes, and The second portion of the insulating layer is located between the bottom surface of the second portion of each of the plurality of upper electrodes and the top surface of the field oxide layer.

8. The semiconductor device according to claim 1, wherein, The field oxide layer comprises a localized oxide of silicon LOCOS.

9. The semiconductor device according to claim 1, wherein, The source region has the first conductivity type, and The drain region has the first conductivity type.

10. The semiconductor device according to claim 1, wherein, The top surfaces of the plurality of upper electrodes are at the same vertical height.

11. The semiconductor device according to claim 1, wherein, The floating electrode structure is configured to float based on the gate voltage applied to the gate electrode.

12. The semiconductor device according to claim 1, wherein, The gate electrode and the floating electrode structure are spaced apart in the first horizontal direction.

13. The semiconductor device according to claim 1, wherein, The floating electrode structure includes: An edge electrode, located between the plurality of lower electrodes and the gate electrode, is adjacent to the first extension of the gate electrode, and The gate electrode includes a second extension on the top surface of the edge electrode, which has a vertical height higher than the first extension.

14. The semiconductor device according to claim 13, wherein, The top surface of the second extension of the gate electrode is at the same vertical height as the top surfaces of the plurality of upper electrodes.

15. A semiconductor device, comprising: Substrate; A drift region and a body region are located on the upper part of the substrate, wherein the drift region has a first conductivity type and the body region has a second conductivity type; A field oxide layer is applied to the drift region of the substrate. A gate electrode is located on the substrate and vertically overlaps with a portion of the drift region and a portion of the body region. The source region is located on the first side of the gate electrode in the main region of the substrate; A drain region, on a first side of the field oxide layer within the drift region of the substrate; and A floating electrode structure, situated on the field oxide layer and between the gate electrode and the drain region, the floating electrode structure comprising: Multiple lower electrodes are spaced apart from each other by a first interval distance along a first horizontal direction on the top surface of the field oxide layer. A plurality of upper electrodes, each upper electrode offset relative to a corresponding lower electrode in a first horizontal direction, the plurality of upper electrodes being spaced apart from each other in the first horizontal direction by a second interval equal to the first interval distance, and An insulating layer is provided between the plurality of lower electrodes and the plurality of upper electrodes.

16. The semiconductor device according to claim 15, wherein, Each of the plurality of upper electrodes includes: The first part is on the top surface of a corresponding lower electrode among the plurality of lower electrodes; and The second part is integrally connected to the first part on the sidewall of a corresponding lower electrode among the plurality of lower electrodes.

17. The semiconductor device according to claim 16, wherein, The first portion of each of the plurality of upper electrodes vertically overlaps with at least a portion of a corresponding lower electrode of the plurality of lower electrodes.

18. The semiconductor device of claim 15, wherein Each of the plurality of lower electrodes has a rectangular vertical cross-section, and Each of the plurality of upper electrodes has an inverted L-shaped vertical cross-section.

19. A semiconductor device, comprising: Flash memory cells are located on a first region of the substrate; as well as Metal-oxide-semiconductor (MOS) transistors, on a second region of the substrate, The MOS transistor includes: A drift region and a body region are located on the upper part of the substrate, wherein the drift region has a first conductivity type and the body region has a second conductivity type. A field oxide layer is applied to the drift region of the substrate. A gate electrode is located on the substrate and vertically overlaps with a portion of the drift region and a portion of the body region. The source region is located on the first side of the gate electrode within the main region of the substrate. The drain region is located on the first side of the field oxide layer within the drift region of the substrate, and A floating electrode structure, situated on the field oxide layer and between the gate electrode and the drain region, the floating electrode structure comprising: Multiple lower electrodes are spaced apart on the top surface of the field oxide layer; An insulating layer covering the top surface of the plurality of lower electrodes; and Multiple upper electrodes are located on the insulating layer, and each upper electrode vertically overlaps a portion of a corresponding lower electrode among the multiple lower electrodes.

20. The semiconductor device according to claim 19, wherein, The plurality of lower electrodes includes a first lower electrode and a second lower electrode adjacent to the first lower electrode, and The plurality of upper electrodes includes a first upper electrode on the first lower electrode and a second upper electrode on the second lower electrode. The first lower electrode and the second lower electrode are spaced apart by a first interval distance in the first horizontal direction. The first upper electrode and the second upper electrode are spaced apart by a second interval distance in the first horizontal direction, and the second interval distance is equal to the first interval distance. The second upper electrode and the first upper electrode are spaced apart by a third interval distance in the first horizontal direction, and The third interval distance is less than the first interval distance.

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