Method for improving interface between silicon nitride layer and top oxide layer in SONOS device and SONOS device
By retaining the top oxide layer until the later stage of photoresist formation during SONOS device fabrication and combining dry and wet etching to remove the silicon nitride layer step by step, the problem of interface contamination and damage between the silicon nitride layer and the top oxide layer is solved, and the stability and consistency of the device's threshold voltage window are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-29
- Publication Date
- 2026-04-03
AI Technical Summary
In the current manufacturing process of SONOS devices, the interface between the silicon nitride layer and the top oxide layer is easily affected by the photoresist material and the etching process, resulting in interface contamination and damage, which affects the stability and consistency of the device threshold voltage window.
In the partitioning process, the top oxide layer is retained as a sacrificial oxide layer until the later stages of photoresist formation, etching, and resist removal. The silicon nitride layer in the non-control gate region is removed step by step by dry and wet etching to ensure that the photoresist material does not directly contact the silicon nitride layer. Finally, the top oxide layer is removed by wet etching at the end to achieve interface stability.
It improves the interface quality between the silicon nitride layer and the top oxide layer, reduces the risk of interface contamination and damage, enhances the stability and consistency of the device threshold voltage window, and strengthens the programming and erasing characteristics of SONOS devices.
Smart Images
Figure CN121793418A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor memory device manufacturing technology, and more specifically to a method for improving the interface between the silicon nitride layer and the top oxide layer in a SONOS device, and the SONOS device obtained by the method. Background Technology
[0002] SONOS devices, as charge-trapping non-volatile memory structures, typically consist of an ONO stacked dielectric structure formed on a semiconductor substrate, comprising a tunneling oxide layer, a silicon nitride storage layer, and a top oxide layer, with a gate structure formed on top to achieve charge injection, storage, and release. Since key electrical parameters such as programming and erasing characteristics, threshold voltage window, and consistency are closely related to the interface quality of the ONO stacked dielectric layers, consistently obtaining a high-quality silicon nitride layer-top oxide layer interface during manufacturing, while avoiding contamination or damage, has always been a crucial concern in SONOS process integration.
[0003] In typical SONOS or similar processes, to achieve structural differences between different regions (such as the control gate region and the non-control gate region), it is usually necessary to define and etch the ONO stack dielectric structure using photolithography, and then remove part of the dielectric layer in the non-control gate region to meet the needs of subsequent device isolation, interconnection, or other structure formation. Especially in the non-control gate region, the bottom oxide layer often includes not only a tunneling oxide layer, but may also form a combination structure of pad oxide layer and tunneling oxide layer. Therefore, during the removal process, it is necessary to ensure etching selectivity and termination control, while avoiding unnecessary exposure, contamination, or etching damage to the ONO stack in the control gate region.
[0004] In existing process practices, common technical problems include: during photoresist coating, development, etching, and resist removal, if the silicon nitride layer in the control gate region is directly exposed and in contact with the photoresist material or its residue at certain stages, or is affected by plasma and chemical systems during etching and resist removal, organic residues, plasma damage, or surface roughening can easily be introduced onto the silicon nitride surface. Simultaneously, the silicon nitride layer in the control gate region will lose some thickness, leading to a narrowing of the device threshold voltage window and increased volatility. Furthermore, in the non-control gate region, if there is a lack of clear termination layer control and zoned removal strategies when removing the silicon nitride layer and the bottom oxide layer, over-etching, residue, or uneven removal of the bottom oxide layer may occur, affecting the consistency and yield of subsequent structures. Summary of the Invention
[0005] To address the interface contamination and damage issues that easily occur in the partitioning process of SONOS devices, and the resulting threshold voltage window fluctuations, this invention provides a method and a SONOS device for improving the interface between the silicon nitride layer and the top oxide layer. This method focuses on partitioning the control gate region and the non-control gate region. After forming the bottom oxide layer and depositing the silicon nitride and top oxide layers, the top oxide layer is used to isolate the silicon nitride layer in the control gate region during photoresist formation, top oxide layer etching, and resist removal steps. This prevents the photoresist material and its residue from directly contacting the silicon nitride layer in the control gate region and avoids premature removal of the top oxide layer, which would cause subsequent photolithography steps to directly affect the silicon nitride layer. This reduces the adverse effects on the silicon nitride layer surface, stabilizes the interface quality between the silicon nitride layer and the top oxide layer, and improves the threshold voltage window of the device.
[0006] According to a first aspect of the present invention, a method for improving the interface between the silicon nitride layer and the top oxide layer in a SONOS device is provided, comprising the following steps: Define a control gate region and a non-control gate region on a semiconductor substrate; A bottom oxide layer is formed on the semiconductor substrate. The bottom oxide layer is a tunneling oxide layer in the control gate region and includes a pad oxide layer and a tunneling oxide layer formed on the pad oxide layer in the non-control gate region. A silicon nitride layer and a top oxide layer are sequentially formed on the bottom oxide layer of the control gate region and the non-control gate region; A photoresist pattern is formed on the top oxide layer, and the top oxide layer is etched using the photoresist pattern as a mask to expose the silicon nitride layer in the non-control gate region. Remove the silicon nitride layer from the non-control gate region; Remove the photoresist pattern; The top oxide layer is removed in the control gate region, and the tunneling oxide layer and the pad oxide layer are removed in the non-control gate region.
[0007] In some technical solutions, during the process of forming the photoresist pattern, etching the top oxide layer using the photoresist pattern as a mask, and removing the photoresist pattern, the top oxide layer continuously covers the silicon nitride layer of the control gate region, so that the top oxide layer always separates the photoresist pattern from the silicon nitride layer of the control gate region.
[0008] In some technical solutions, the method further includes one or more of the following process limitations: (1) The step of etching the top oxide layer using the photoresist pattern as a mask includes dry etching, wherein the dry etching is used to remove the top oxide layer in the non-control gate region, and further etch the silicon nitride layer into the non-control gate region and the etching terminates in the silicon nitride layer. (2) The step of removing the silicon nitride layer in the non-controlled gate region includes wet etching to remove the remaining silicon nitride layer in the non-controlled gate region, and using the bottom oxide layer as the etching termination layer when etching the silicon nitride layer. (3) The step of removing the photoresist pattern includes dry removal and wet immersion washing; (4) The step of removing the top oxide layer in the control gate region and removing the tunneling oxide layer and the pad oxide layer in the non-control gate region includes wet etching.
[0009] In some technical solutions, the dry etching in (1) includes etching the top oxide layer and part of the silicon nitride layer using fluorine-containing plasma; The wet etching in (2) includes etching the remaining silicon nitride layer in the non-controlled gate region using a phosphoric acid system; The dry removal method in (3) includes plasma degumming, and the wet immersion washing method includes wet soaking cleaning; The wet etching in (4) includes etching silicon oxide with a fluorine-containing solution.
[0010] In some technical solutions, a removal step for removing the top oxide layer is not performed before the photoresist pattern is formed.
[0011] In some technical solutions, the forming process of each layer satisfies one or more of the following: The tunneling oxide layer in the bottom oxide layer is formed by thermal oxidation, and the pad oxide layer in the non-control gate region is formed by thermal oxidation and / or chemical vapor deposition. Both the silicon nitride layer and the top oxide layer are formed by high-pressure chemical vapor deposition.
[0012] In some technical solutions, in the step of etching the top oxide layer using the photoresist pattern as a mask, an opening is formed in the non-control gate region, and the opening is defined by the photoresist pattern.
[0013] In some technical solutions, the top oxide layer is a silicon oxide layer, and the top oxide layer is a sacrificial oxide layer that is temporarily retained during the method process and removed in subsequent steps; and the tunneling oxide layer and the pad oxide layer in the bottom oxide layer are both silicon oxide layers.
[0014] According to a second aspect of the present invention, a SONOS device is further provided, comprising a semiconductor substrate and a control gate region and a non-control gate region located on the semiconductor substrate, wherein the control gate region includes a tunneling oxide layer, a silicon nitride layer formed on the tunneling oxide layer, and a top oxide layer located on the silicon nitride layer; the non-control gate region includes a pad oxide layer, a tunneling oxide layer formed on the pad oxide layer, a silicon nitride layer formed on the tunneling oxide layer, and a top oxide layer located on the silicon nitride layer; wherein the SONOS device is manufactured by the method described above.
[0015] In some technical solutions, the top oxide layer covers the silicon nitride layer in the control gate region, so that the silicon nitride layer in the control gate region is always separated from the material forming the photoresist pattern by the top oxide layer, thereby improving the threshold voltage window of the SONOS device.
[0016] The present invention, by adopting the above technical solution, has at least the following technical effects: 1. This invention positions the top oxide layer as a sacrificial oxide layer temporarily retained during the partitioning process and removed in subsequent steps. By controlling the retention timing of the top oxide layer, it continuously covers the silicon nitride layer of the control gate region during photoresist formation, top oxide layer etching using photoresist as a mask, and photoresist removal steps. This avoids direct contact between the photoresist material and its residues and the silicon nitride layer of the control gate region from the process path, and avoids the risk of surface contamination, chemical erosion, or plasma damage introduced by subsequent photolithography steps directly acting on the silicon nitride layer after the top oxide layer is removed in advance. This helps to maintain the stability of the surface state of the silicon nitride layer in the control gate region, makes the interface between the silicon nitride layer and the top oxide layer more uniform, reduces silicon nitride layer loss, and thus improves the threshold voltage window at the device level.
[0017] 2. Regarding the opening and removal process of the non-controlled gate region, this invention separates the etching of the top oxide layer, the removal of the silicon nitride layer, and the removal of the bottom oxide layer into steps. It can also combine dry etching, wet etching, and wet immersion etching processes, as well as the control of the etching termination layer, to make the removal of dielectric materials in the non-controlled gate region more controllable, reduce the risk of over-etching, residue, or uneven removal, and thus improve the consistency of subsequent structures and manufacturing yield.
[0018] In summary, by suppressing interface contamination and damage and improving the controllability of the partitioning removal process, this invention can improve the threshold voltage window at the device level, enhance the repeatability and reliability of SONOS device programming and erasing characteristics, and is more suitable for implementation in existing SONOS process platforms. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 Here is a flow chart of the existing ONO loop process; Figure 2 This is a process flow diagram of the improved ONO loop of the present invention; Figure 3 correspond Figure 1 and Figure 2 The post-deposition structure of ONO in the middle (ONO dep); Figure 4 correspond Figure 1 Structure after top oxide layer removal (HTO removal); Figure 5 correspond Figure 1 Photolithography and post-etching structure (ONO PH & etch); Figure 6 correspond Figure 1 Structure after wet etching of the bottom oxide layer (ONO wet dip). Figure 7 correspond Figure 1 The structure after photoresist removal and wet rinsing (ONO PR dry & wet dip). Figure 8 correspond Figure 2 The photolithography and etching structure (ONO PH & etch, stopped within the nitride); Figure 9 correspond Figure 2 The structure after removing silicon nitride by wet etching (Wet etch); Figure 10 correspond Figure 2 The structure after photoresist removal and wet rinsing (ONO PR dry & wet dip). Detailed Implementation
[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.
[0022] To keep the drawings concise, each figure only schematically shows the parts relevant to the invention, and these do not represent the actual structure of the product. Furthermore, to facilitate understanding, in some figures, only one of components with the same structure or function is schematically depicted, or only one is labeled. In this document, "one" not only means "only one," but can also mean "more than one."
[0023] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0024] Unless otherwise specified, the methods described in the following embodiments are generally performed under conventional conditions. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as are familiar to those skilled in the art. Furthermore, any methods and materials similar to or equivalent to those described herein may be applied to the methods of this invention. The preferred embodiments and materials described herein are for illustrative purposes only.
[0025] In the SONOS flash products addressed in this case, it is usually necessary to form two types of structures on the same wafer: the control gate region (CG region) and the non-control gate region (non-CG region). The CG region corresponds to the core area of the memory cell and needs to retain and ensure the interface quality of the bottom oxide layer, silicon nitride layer and top oxide layer (ONO stack). The non-CG region often needs to open and remove part of the dielectric layer according to subsequent isolation or other structural requirements.
[0026] like Figure 1 As shown, the existing ONO loop first completes ONO deposition, then removes the top oxide layer, and then removes the relevant layers of the non-CG region through photolithography, etching, and immersion etching, thereby realizing the structural difference between the CG region and the non-CG region on the same wafer. Figures 3 to 7 Corresponding to Figure 1 Profile status of key nodes in the middle: Figure 3 This is the structure after ONO deposition (ONO dep). Figure 4 The structure after top oxide layer removal (HTO removal). Figure 5 The structure is formed by photolithography and etching (ONO PH & etch). Figure 6 The structure after wet etching of the bottom oxide layer (ONO wet dip). Figure 7 The structure after photoresist removal and wet rinsing (ONO PRdry & wet dip).
[0027] Specifically Figure 3At this point, an ONO stack has been formed on the semiconductor substrate: the bottom oxide layer in the CG region can generally be considered as a tunneling oxide layer; in the non-CG region, a combination of pad oxide and tunneling oxide may also be stacked, above which is a silicon nitride layer, and above that is a top oxide layer. This cross-sectional view shows that the CG region and the non-CG region are still in a uniform stacked state with the same shape and layer at this time, and subsequent differentiation needs to be created by partitioning openings and partition removal.
[0028] Then enter Figure 4 This step occurs before partitioning photolithography, which means that the top oxide layer is removed in advance. Subsequently, a series of steps such as photoresist formation and development, etching and photoresist removal will inevitably follow, which poses a risk to the interface quality between the silicon nitride layer and the top oxide layer.
[0029] Then Figure 5 At this point, a photoresist pattern has been formed on the wafer surface, and the corresponding area is etched using the photoresist pattern as a mask. In this step, the silicon nitride layer in the non-CG area is removed, and the bottom oxide layer is used as the etching termination layer.
[0030] then Figure 6 In non-CG areas, the underlying oxide layer is further removed by wet etching.
[0031] Until Figure 7 After completing the partition etching, the photoresist is removed by dry method and then cleaned by wet immersion.
[0032] It can be seen that the existing process has the following defects: First, when the top oxide layer is removed in the early stage of the process, the silicon nitride layer in the CG region is prone to direct contact with the photoresist material or its residue in subsequent photolithography and etching, resist removal and cleaning steps, thereby affecting the interface quality of the silicon nitride layer.
[0033] Secondly, during processes such as photolithography, etching, resist removal, and cleaning, the existing process directly affects the silicon nitride layer, which leads to unnecessary damage to the silicon nitride layer and further deteriorates the storage window.
[0034] Based on this, this application provides a method for improving the interface between the silicon nitride layer and the top oxide layer in a SONOS device. The core concept is that after ONO deposition, the top oxide layer is no longer removed first. Instead, the top oxide layer is used as a sacrificial oxide layer in the partitioning lithography, etching, and resist removal steps, so that the photoresist material and its residue always act on the top oxide layer rather than directly on the silicon nitride layer in the CG region during the above stages. The specific process flow is as follows: Figure 2As shown: First, ONO deposition (ONOdep) is performed; then, photolithography (ONO PH) and etching (ONO etch) are performed directly, opening up the non-CG region and etching the top oxide layer; then, the remaining silicon nitride layer in the non-CG region is removed by wet etching (Wet etch, remove nitride); then, dry photoresist removal is performed in conjunction with wet rinsing (ONO PR dry & wet dip); finally, a wet etching step (ONOwet dip) is performed to remove the top oxide layer in the CG region and remove the tunnel oxide layer and pad oxide layer in the non-CG region.
[0035] In practice, a control gate region (CG region) and a non-control gate region (non-CG region) can be defined on the semiconductor substrate first. Then, a bottom oxide layer is formed on the semiconductor substrate. The bottom oxide layer in the CG region is a tunneling oxide layer; the bottom oxide layer in the non-CG region includes a pad oxide layer and a tunneling oxide layer formed on the pad oxide layer. Specifically, the tunneling oxide layer is formed by thermal oxidation, and the pad oxide layer is formed by thermal oxidation and / or chemical vapor deposition.
[0036] After forming the bottom oxide layer, a silicon nitride layer and a top oxide layer are sequentially formed on the bottom oxide layer in the CG region and the non-CG region, thereby obtaining an ONO stacked structure. The silicon nitride layer and the top oxide layer can be formed, for example, by high-pressure chemical vapor deposition; and in this embodiment, the top oxide layer is preferably a silicon oxide layer, serving as a sacrificial oxide layer temporarily retained and removed in subsequent steps. The cross-sectional morphology at this stage can be seen in [reference needed]. Figure 3 It shows that, from bottom to top, the semiconductor substrate consists of a bottom oxide layer, a silicon nitride layer, and a top oxide layer. The bottom oxide layer in the non-CG region is a superposition structure of a pad oxide layer and a tunnel oxide layer, while the CG region corresponds to a tunnel oxide layer.
[0037] One of the key improvements in this embodiment is that the removal step for the top oxide layer is not performed before forming the photoresist pattern. In other words, compared to existing processes that remove the entire top oxide layer before partitioning photolithography, this embodiment retains the top oxide layer after partitioning photolithography, etching, and photoresist stripping steps. Thus, when forming the photoresist pattern subsequently, the photoresist directly interacts with the top oxide layer instead of the silicon nitride layer, thereby avoiding direct contact between the photoresist and its residues with the silicon nitride layer in the CG region along the process contact path, providing a process starting point for subsequent interface stability.
[0038] In practice, a photoresist pattern is formed on the top oxide layer, and the top oxide layer is etched using the photoresist pattern as a mask to expose the silicon nitride layer in the non-CG regions. Figure 8This can be understood as follows: the photoresist pattern is retained only in the CG region or otherwise creates openings in the non-CG region, thereby removing the top oxide layer in the non-CG region during the etching step. Specifically, the openings formed in the non-CG region are defined by the photoresist pattern, therefore the size, location, and morphology of the openings are mainly determined by the photoresist pattern. Further, the etching step of the top oxide layer includes dry etching, which not only removes the top oxide layer in the non-CG region but also further etches into the silicon nitride layer in the non-CG region and terminates within the silicon nitride layer; in a preferred embodiment, this dry etching can employ fluorine-containing plasma to etch the top oxide layer and part of the silicon nitride layer. Thus, Figure 8 The cross-sectional state shown is as follows: the top oxide layer of the non-CG region is removed and an opening is formed, and part of the silicon nitride layer is etched off above the non-CG region but still remains, while the top oxide layer of the CG region is still retained on the silicon nitride layer.
[0039] In practice, after completing the dry etching process described above, the remaining silicon nitride layer in the non-CG regions can be further removed, exposing the non-CG regions to the bottom oxide layer. Correspondingly... Figure 9 This step involves removing the silicon nitride layer in the non-CG regions down to the surface of the bottom oxide layer, while the CG regions retain the stacked state of the top oxide layer, silicon nitride layer, and tunnel oxide layer. The removal of the silicon nitride layer in the non-CG regions includes wet etching to remove the remaining silicon nitride layer in the non-CG regions, with the bottom oxide layer serving as the etching termination layer during the etching process. In a preferred embodiment, this wet etching can employ a phosphoric acid system to etch the remaining silicon nitride layer in the non-CG regions. This step-by-step combination of dry etching to first open and etch the silicon nitride layer, followed by wet etching to remove the remaining silicon nitride, ensures controllability in the opening formation and pattern transfer of the non-CG regions. Furthermore, it allows for a clear termination interface at the bottom oxide layer during the final removal of the silicon nitride layer, thereby reducing the risk of over-etching and uneven removal.
[0040] In practice, after removing the silicon nitride layer in the non-CG areas, the photoresist pattern is removed, followed by wet immersion cleaning to remove etching byproducts and residues. Figure 10This can be understood as follows: after the photoresist is removed, the non-CG region has exposed the bottom oxide layer, while the top oxide layer of the CG region still covers the silicon nitride layer. In a preferred embodiment, dry removal may include plasma stripping, and wet immersion cleaning may include wet immersion cleaning. Since the top oxide layer still exists as an isolation layer above the silicon nitride layer in the CG region during the stripping and cleaning stages, the photoresist material and its residue, the stripping process, and the cleaning system preferentially act on the top oxide layer rather than directly on the silicon nitride layer, thus significantly changing the exposure conditions of the silicon nitride layer in the PR-related steps compared to existing processes. Furthermore, during the formation of the photoresist pattern, etching of the top oxide layer, and removal of the photoresist pattern, the top oxide layer continuously covers the silicon nitride layer in the CG region, ensuring that the top oxide layer always separates the photoresist pattern from the silicon nitride layer in the CG region.
[0041] In a preferred embodiment, after desizing and rinsing, a final wet etching step is performed to achieve separate removal of CG and non-CG areas. Figure 7 After this step is completed: the top oxide layer in the CG region is removed, exposing the silicon nitride layer in the CG region for subsequent gate and other processes; the tunneling oxide layer and pad oxide layer in the non-CG region are removed, further opening the non-CG region downwards or clearing it to the substrate surface to meet the requirements of subsequent isolation or other structure formation. In a preferred embodiment, this wet etching may include etching the silicon oxide with a fluorine-containing solution. By placing the removal of the top oxide layer in the CG region in the final wet etching step and completing it simultaneously with the removal of the bottom oxide layer in the non-CG region, the timing control goal of continuously retaining the top oxide layer in the PR-related stage and removing it at the end is achieved. It also allows the removal of the bottom oxide layer in the non-CG region and the structure opening to be completed in a unified final step, thereby forming a clearer and more controllable process closed loop.
[0042] Therefore, the main difference between this embodiment and the existing ONO cycle process is not simply changing a certain etching formula or a single step, but rather establishing a new process organization around the timing of top oxide layer retention and removal, as well as the stepwise removal of silicon nitride in non-CG regions and the final partitioned wet etching. Under this organization, the top oxide layer in the CG region acts as an isolation layer in the photolithography, etching, and resist stripping steps, reducing the direct impact of photoresist material and residues on the surface of the silicon nitride layer in the CG region. In the non-CG region, controllable removal is achieved through a sequence of dry etching to open and etch the silicon nitride layer, wet etching to remove the remaining silicon nitride layer and terminating with the bottom oxide layer, and final wet etching to remove the oxide layer. Ultimately, because the risk of interface fluctuations between the silicon nitride layer and the top oxide layer is suppressed, the device threshold voltage window can be improved, making it more suitable for implementation in the SONOS flash product platform targeted in this case.
[0043] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.
Claims
1. A method for improving the interface between the silicon nitride layer and the top oxide layer in a SONOS device, characterized in that, Includes the following steps: Define a control gate region and a non-control gate region on a semiconductor substrate; A bottom oxide layer is formed on the semiconductor substrate. The bottom oxide layer is a tunneling oxide layer in the control gate region and includes a pad oxide layer and a tunneling oxide layer formed on the pad oxide layer in the non-control gate region. A silicon nitride layer and a top oxide layer are sequentially formed on the bottom oxide layer of the control gate region and the non-control gate region; A photoresist pattern is formed on the top oxide layer, and the top oxide layer is etched using the photoresist pattern as a mask to expose the silicon nitride layer in the non-control gate region. Remove the silicon nitride layer from the non-control gate region; Remove the photoresist pattern; The top oxide layer is removed in the control gate region, and the tunneling oxide layer and the pad oxide layer are removed in the non-control gate region.
2. The method according to claim 1, characterized in that, During the process of forming the photoresist pattern, etching the top oxide layer using the photoresist pattern as a mask, and removing the photoresist pattern, the top oxide layer continuously covers the silicon nitride layer of the control gate region, so that the top oxide layer always separates the photoresist pattern from the silicon nitride layer of the control gate region.
3. The method according to claim 1, characterized in that, The method also includes one or more of the following process limitations: (1) The step of etching the top oxide layer using the photoresist pattern as a mask includes dry etching, wherein the dry etching is used to remove the top oxide layer in the non-control gate region, and further etch the silicon nitride layer into the non-control gate region and the etching terminates in the silicon nitride layer. (2) The step of removing the silicon nitride layer in the non-controlled gate region includes wet etching to remove the remaining silicon nitride layer in the non-controlled gate region, and using the bottom oxide layer as the etching termination layer when etching the silicon nitride layer. (3) The step of removing the photoresist pattern includes dry removal and wet immersion washing; (4) The step of removing the top oxide layer in the control gate region and removing the tunneling oxide layer and the pad oxide layer in the non-control gate region includes wet etching.
4. The method according to claim 3, characterized in that, The dry etching in (1) includes etching the top oxide layer and part of the silicon nitride layer using fluorine-containing plasma; The wet etching in (2) includes etching the remaining silicon nitride layer in the non-controlled gate region using a phosphoric acid system; The dry removal method in (3) includes plasma degumming, and the wet immersion washing method includes wet soaking cleaning; The wet etching in (4) includes etching silicon oxide with a fluorine-containing solution.
5. The method according to claim 1, characterized in that, The removal step for removing the top oxide layer is not performed before the photoresist pattern is formed.
6. The method according to claim 1, characterized in that, The formation process of each layer satisfies one or more of the following: The tunneling oxide layer in the bottom oxide layer is formed by thermal oxidation, and the pad oxide layer in the non-control gate region is formed by thermal oxidation and / or chemical vapor deposition. Both the silicon nitride layer and the top oxide layer are formed by high-pressure chemical vapor deposition.
7. The method according to claim 1, characterized in that, In the step of etching the top oxide layer using the photoresist pattern as a mask, an opening is formed in the non-control gate region, the opening being defined by the photoresist pattern.
8. The method according to claim 1, characterized in that, The top oxide layer is a silicon oxide layer, and the top oxide layer is a sacrificial oxide layer that is temporarily retained during the implementation of the method and removed in subsequent steps; and the tunneling oxide layer and the pad oxide layer in the bottom oxide layer are both silicon oxide layers.
9. A SONOS device, characterized in that, The device includes a semiconductor substrate and a control gate region and a non-control gate region located on the semiconductor substrate. The control gate region includes a tunneling oxide layer, a silicon nitride layer formed on the tunneling oxide layer, and a top oxide layer located on the silicon nitride layer. The non-control gate region includes a pad oxide layer, a tunneling oxide layer formed on the pad oxide layer, a silicon nitride layer formed on the tunneling oxide layer, and a top oxide layer located on the silicon nitride layer. The SONOS device is manufactured by the method according to any one of claims 1-8.
10. The SONOS device according to claim 9, characterized in that, The top oxide layer covers the silicon nitride layer in the control gate region, such that the top oxide layer always separates the silicon nitride layer in the control gate region from the material forming the photoresist pattern, thereby improving the threshold voltage window of the SONOS device.