Silicon carbide CMOS device based on P-type doped mesa structure and manufacturing method

Abstract

The invention belongs to the technical field of electronics, and relates to a silicon carbide CMOS device based on a P-type doped mesa structure and a manufacturing method, and the manufacturing method comprises the steps: carrying out the etching of a silicon carbide P-type lightly doped epitaxial layer to form the P-type doped mesa structure, exposing a silicon carbide N-type lightly doped epitaxial layer buried below, and repairing the etching damage through employing a sacrifice oxide layer method; low-energy ion implantation is carried out twice, and annealing is carried out at high temperature to activate the implanted ions; growing a gate oxide layer through thermal oxidation reaction; etching the gate oxide layer in a partial region and depositing ohmic contact metal, and forming good ohmic contact through thermal annealing; and depositing gate metal to form a gate structure. According to the method, the mesa structure formed by etching is used for replacing a well region formed by high-energy ion implantation, a large amount of lattice damage cannot be generated in a channel region of the MOS device, and the non-uniform stress effect introduced by the high-energy ion implantation to the silicon carbide wafer is avoided.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology, and specifically relates to silicon carbide CMOS devices based on P-type doped mesa structures and their fabrication methods. Background Technology

[0002] Existing silicon carbide CMOS integrated circuits are fabricated using a single high-energy Al ion implantation to form a P-type well region, thereby achieving the integration of planar complementary MOS. However, high-energy Al ion implantation is costly and causes significant damage to the surface lattice, reducing the channel mobility of NMOS in the P-type well region.

[0003] To achieve monolithic integration of CMOS on a silicon carbide wafer, such as Figure 15 As shown, firstly, N-type and P-type body regions need to be fabricated on the silicon carbide surface. By implanting high-energy aluminum ions into the N-type epitaxial layer, a P-type well region can be generated in a portion of the N-type epitaxial wafer surface, serving as the P-type body region of the NMOS, while the unimplanted region serves as the N-type body region of the PMOS. Subsequently, a low-energy N-type ion implantation and a low-energy P-type ion implantation are performed to form the source and drain regions of the NMOS and PMOS, respectively. Then, high-temperature thermal annealing exceeding 1500°C is used to repair lattice damage and activate the implanted ions.

[0004] However, high-energy ion implantation generates significant lattice damage on the surface and deep layers of silicon carbide wafers. Even after high-temperature annealing repairs the damage, complex point defects, stacking faults, new dislocations, shallow or deep level defects, basal dislocation loops, and the movement of existing dislocations are still introduced into the lattice, degrading device performance. High-energy ion bombardment introduces substantial lattice mismatches into the deep layers of the silicon carbide wafer, resulting in severe stress. High-temperature, high-energy ion implantation also increases wafer warpage. Furthermore, high-energy ion implantation to form silicon carbide trap regions requires precise control of multiple parameters, leading to long process development cycles and high equipment demands. Therefore, a method for developing monolithic silicon carbide CMOS integrated devices that reduces lattice damage, minimizes stress on the silicon carbide wafer during ion implantation, and lowers development cycles and costs is essential. Summary of the Invention

[0005] To address the shortcomings of the prior art, the present invention aims to provide a silicon carbide CMOS device and its fabrication method based on a P-type doped mesa structure, which solves the defects in the prior art. This fabrication method does not perform high-energy ion implantation to generate a deep well region when fabricating silicon carbide CMOS devices, thus avoiding a large amount of lattice damage on the surface of the silicon carbide wafer and reducing the stress on the silicon carbide wafer during ion implantation.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: This invention provides a method for fabricating a silicon carbide CMOS device based on a P-type doped mesa structure, comprising the following steps: A silicon carbide N-type lightly doped epitaxial layer and a silicon carbide P-type lightly doped epitaxial layer are epitaxially grown sequentially from bottom to top on the upper surface of an N-type silicon carbide substrate. At the same time, a P-type doped mesa is formed by etching part of the silicon carbide P-type lightly doped epitaxial layer to expose the upper surface of the silicon carbide N-type lightly doped epitaxial layer. A sacrificial oxide layer is grown on the surface of the P-type doped mesa and the exposed silicon carbide N-type lightly doped epitaxial layer by thermal oxidation reaction, and then the sacrificial oxide layer is completely removed. After the sacrificial oxide layer is completely removed, both the N-type lightly doped epitaxial layer and the upper surface of the P-type doped mesa of silicon carbide are implanted with N-type ions and P-type ions to form N-type heavily doped ion implantation regions and P-type heavily doped ion implantation regions, respectively. Then, the implanted ions in the N-type heavily doped ion implantation regions and P-type heavily doped ion implantation regions are activated by high-temperature thermal annealing. A gate oxide layer is then grown on the upper surface of the lightly doped N-type epitaxial layer and the P-type doped mesa of silicon carbide through a thermal oxidation reaction. The gate oxide layer is etched to obtain ohmic contact openings. Ohmic contacts are then formed inside the ohmic contact openings and subjected to thermal annealing. Finally, gate metal is deposited and grown on the upper surface of the gate oxide layer to form a gate structure.

[0007] The step of etching a portion of the silicon carbide P-type lightly doped epitaxial layer to expose the upper surface of the silicon carbide N-type lightly doped epitaxial layer while simultaneously forming a P-type doped mesa is as follows: A thick photoresist layer is coated on the upper surface of the lightly doped silicon carbide P-type epitaxial layer obtained by epitaxial growth. The photoresist is then patterned using photolithography processes such as exposure, development, and hardening to form a patterned photoresist.

[0008] The patterned photoresist is chemically treated to create a beveled edge, and then reinforced.

[0009] Based on the patterned photoresist, an inductively coupled plasma etching process is used to etch the silicon carbide P-type lightly doped epitaxial layer. The etching stops at the upper surface of the silicon carbide N-type lightly doped epitaxial layer, forming a P-type doped mesa.

[0010] Remove the patterned photoresist.

[0011] The step of performing N-type ion implantation on the upper surface of the lightly doped N-type epitaxial layer and the P-type doped mesa in silicon carbide to form a heavily doped N-type ion implantation region is as follows: A silicon dioxide layer is deposited and grown on the upper surface of the silicon carbide N-type lightly doped epitaxial layer and the P-type doped mesa as an ion implantation mask.

[0012] A layer of photoresist is coated on the surface of an ion implantation mask, and the photoresist is patterned using photolithography processes such as exposure, development, and hardening to form a patterned photoresist.

[0013] Based on the patterned photoresist, an inductively coupled plasma etching process is used to etch the silicon dioxide ion implantation mask, with the etching stopping at the upper surface of the silicon carbide N-type lightly doped epitaxial layer and the P-type doped mesa.

[0014] Remove the patterned photoresist and retain the silicon dioxide ion implantation mask.

[0015] Based on the silicon dioxide ion implantation mask, nitrogen ions are implanted into the silicon carbide N-type lightly doped epitaxial layer and P-type doped mesa to form an N-type heavily doped ion implantation region, wherein the nitrogen ion implantation temperature is 500℃.

[0016] Remove the ion implantation mask.

[0017] The step of performing P-type ion implantation on the upper surface of the lightly doped N-type epitaxial layer and the P-type doped mesa in silicon carbide to form a heavily doped P-type ion implantation region is as follows: A silicon dioxide layer is deposited and grown on the upper surface of the silicon carbide N-type lightly doped epitaxial layer and the P-type doped mesa as an ion implantation mask.

[0018] A layer of photoresist is coated on the surface of the ion implantation mask, and the photoresist is patterned using photolithography processes such as exposure, development and hardening to form a patterned photoresist. Based on the patterned photoresist, an inductively coupled plasma etching process is used to etch the silicon dioxide ion implantation mask, with the etching stopping at the upper surface of the silicon carbide N-type lightly doped epitaxial layer and the P-type doped mesa.

[0019] Remove the patterned photoresist and retain the silicon dioxide ion implantation mask.

[0020] Based on a silicon dioxide ion implantation mask, aluminum ions were implanted into the lightly doped N-type epitaxial layer and the P-type doped mesa of silicon carbide to form a heavily doped P-type ion implantation region. The aluminum ion implantation temperature was 600℃. The ion implantation mask was then removed.

[0021] Preferably, the doping concentration of the lightly doped silicon carbide N-type epitaxial layer is 5 × 10⁻⁶. 15 cm -3 ~5×10 16 cm -3 The thickness of the silicon carbide N-type lightly doped epitaxial layer is 5µm to 15µm; the doping concentration of the silicon carbide P-type lightly doped epitaxial layer and the P-type doped mesa is 5 × 10⁻⁶. 15 cm -3 ~5×10 16 cm-3 The thickness of the silicon carbide P-type lightly doped epitaxial layer and the P-type doped mesa is 1µm to 2µm.

[0022] Preferably, the peak concentration of nitrogen ions implanted in the N-type heavily doped ion implantation region is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 The junction depth of the N-type heavily doped ion implantation region is 0.3 μm to 0.7 μm; the peak concentration of implanted aluminum ions in the P-type heavily doped ion implantation region is 1 × 10⁻⁶. 19 cm -3 ~5×10 19 cm -3 The junction depth of the P-type heavily doped ion implantation region is 0.2 μm to 0.4 μm.

[0023] Preferably, the thickness of the sacrificial oxide layer is 20nm~40nm, the thermal oxidation temperature range for growing the sacrificial oxide layer is 1200℃~1400℃, the oxidation time for growing the sacrificial oxide layer is 20min~60min, the thickness of the gate oxide layer is 30nm~70nm, the thermal oxidation temperature range for growing the gate oxide layer is 1200℃~1400℃, and the oxidation time for growing the gate oxide layer is 45min~120min.

[0024] Preferably, the thermal annealing temperature for activating the N-type heavily doped ion implantation region and the P-type heavily doped ion implantation region is 1500℃~1600℃, and the thermal annealing time is 20min~40min.

[0025] Preferably, the ohmic contact is any one of Ni metal, Ti / Ni metal stack, or Ni / Ti / Al metal stack, and the thickness of the ohmic contact metal is 30nm~100nm.

[0026] Preferably, the annealing temperature of the ohmic contact is 900℃~1000℃, and the annealing time is 5min~10min.

[0027] Preferably, the material for depositing and growing the gate metal is any one of Al metal, Ti / Al metal stack, or Ti / Au metal stack, and the thickness of the deposited and grown gate metal is 300nm~500nm.

[0028] This invention provides a method for fabricating silicon carbide CMOS devices based on a P-type doped mesa structure, resulting in a silicon carbide CMOS device.

[0029] Preferably, the silicon carbide CMOS device includes an N-channel MOS device and a P-channel MOS device. The N-channel MOS device includes a P-type doped mesa structure and an N-type heavily doped ion implantation region, a P-type heavily doped ion implantation region, a gate oxide layer, an ohmic contact, and a gate structure located on the upper surface of the P-type doped mesa structure; the P-channel MOS device includes a silicon carbide N-type lightly doped epitaxial layer and an N-type heavily doped ion implantation region, a P-type heavily doped ion implantation region, a gate oxide layer, an ohmic contact, and a gate structure located on the upper surface of the silicon carbide N-type lightly doped epitaxial layer.

[0030] The N-channel MOS device includes an NMOS body electrode, an NMOS source electrode, an NMOS drain electrode, and an NMOS gate electrode. An ohmic contact located on the upper surface of the P-type doped mesa and on the upper surface of the P-type heavily doped ion implantation region is the NMOS body electrode in the N-channel MOS device. An ohmic contact located on the upper surface of the P-type doped mesa and on the upper surface of the N-type heavily doped ion implantation region, and close to the NMOS body electrode, is the NMOS source electrode in the N-channel MOS device. An ohmic contact located on the upper surface of the P-type doped mesa and on the upper surface of the N-type heavily doped ion implantation region, and away from the NMOS body electrode, is the NMOS drain electrode in the N-channel MOS device. A gate structure located above the gate oxide layer, between the NMOS source electrode and the NMOS drain electrode, is the NMOS gate electrode in the N-channel MOS device.

[0031] The P-channel MOS device includes a PMOS body electrode, a PMOS source electrode, a PMOS drain electrode, and a PMOS gate electrode: the ohmic contact located on the upper surface of the lightly doped N-type epitaxial layer and the upper surface of the heavily doped N-type ion-implanted region is the PMOS body electrode in the P-channel MOS device; the ohmic contact located on the upper surface of the lightly doped N-type epitaxial layer and the upper surface of the heavily doped P-type ion-implanted region, and close to the PMOS body electrode, is the PMOS source electrode in the P-channel MOS device; the ohmic contact located on the upper surface of the lightly doped N-type epitaxial layer and the upper surface of the heavily doped P-type ion-implanted region, and away from the PMOS body electrode, is the PMOS drain electrode in the P-channel MOS device; the gate structure located above the gate oxide layer, between the PMOS source electrode and the PMOS drain electrode, is the NMOS gate electrode in the P-channel MOS device. Using dielectric isolation and metallization interconnection technology, the electrodes of N-channel MOS devices and P-channel MOS devices can be interconnected to form a functional circuit. The connection relationship is as follows: connect the NMOS source electrode to the NMOS body electrode and connect to ground potential; connect the PMOS source electrode to the PMOS body electrode and connect to digital power supply; connect the NMOS gate electrode to the PMOS gate electrode and connect to inverter input; connect the NMOS drain electrode to the PMOS drain electrode and connect to inverter output.

[0032] Compared with the prior art, the beneficial effects of the present invention are as follows: The proposed method for fabricating silicon carbide CMOS based on a P-type doped mesa structure introduces less stress. Existing processes use a single high-energy ion implantation step to form a P-type well region, introducing non-uniform doping regions into the deep layers of the silicon carbide wafer. This results in uneven stress, which is difficult to eliminate using conventional methods such as thermal annealing. The method for fabricating silicon carbide CMOS based on a P-type doped mesa structure, as described in this invention, uses etching of a portion of the lightly doped P-type epitaxial layer of silicon carbide to form a P-type doped mesa, replacing the existing "P-type well region" structure. This method reduces etching-induced defects and stress. Furthermore, the defects and stress introduced by the process steps in this invention are concentrated in the shallow layers or surface of the wafer, and can be effectively released through sacrificial oxide layer and thermal annealing processes, preventing silicon carbide wafer warpage.

[0033] This invention provides a method for fabricating a CMOS well region using two epitaxial layers. By changing the conditions of uniformly doped epitaxial growth of the two layers, this invention can precisely control the doping concentration of the well region, thereby obtaining a more controllable CMOS threshold voltage. Existing processes create a Gaussian doping distribution on the surface after ion implantation of the well. Therefore, to obtain the desired surface doping concentration, precise control of the ion implantation parameters is required. Furthermore, due to power limitations of the ion implanter, it is difficult to push the peak of the Gaussian distribution deep within the well, resulting in a high surface doping concentration and difficulty in reducing the threshold voltage. Compared to the high surface doping concentration of the ion-implanted well region, the method proposed in this invention, using two lightly doped epitaxial layers to control the surface doping concentration, can achieve a lower and more controllable device threshold voltage, making it more suitable for fabricating logic integrated circuits with low threshold voltages.

[0034] While existing ion implantation processes suffer from lattice defects and dislocations caused by high-energy particle bombardment, and can even lead to localized amorphization, and in the "ion implantation of P-type well regions" process, the P-type body region where the NMOS device channel is located is inevitably affected by high-energy Al ion implantation, and the channel region of the MOS device is most sensitive to mobility, thus the degradation of channel mobility significantly affects the conduction performance of the MOS device, in this invention, only the source and drain regions of the MOS device are affected by ion implantation (similar to existing processes), and these regions are not sensitive to mobility; while the channel region of the MOS device is not affected by ion implantation, and there is no large amount of defect generation and accumulation. This is because this invention exposes the lightly doped N-type epitaxial layer through etching, leaving etching damage and roughness on the epitaxial layer surface. Therefore, this invention proposes a method to repair etching damage by using a sacrificial oxide layer combined with high-temperature thermal annealing to repair surface damage introduced during mesa etching. Simulation analysis and comparison show that the defect density of the etched surface after repair with a sacrificial oxide layer and high-temperature thermal annealing is much smaller than that of the surface after ion implantation.

[0035] This invention enables the fabrication of CMOS devices on wafers through a single mesa etching and two low-temperature ion implantations, effectively reducing process development cycle and costs. Existing processes use a single high-energy P-type ion implantation to achieve a surface-inverted P-type well region, requiring strict control of parameters such as implantation dose, implantation energy, implantation angle, and temperature to achieve the desired surface doping concentration for fabricating devices with the required threshold voltage. In this invention, a lightly doped epitaxial process with easily uniform doping concentration and a controllable etching depth are used instead to form a P-type mesa and expose a lightly doped N-type epitaxial layer, achieving precisely controlled surface doping concentration and shortening the development cycle and costs for high-energy ion implantation well region processes. Furthermore, the high-energy ion implantation process for forming P-type well regions requires ion implanters exceeding 100keV, resulting in high equipment and process costs; this invention only requires a low-power ion implanter for two shallow implantations, reducing equipment budget. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the structure obtained after growing the epitaxial layer according to the present invention.

[0037] Figure 2 This is a schematic diagram of the structure obtained after the mesa etching of the present invention.

[0038] Figure 3 This is a schematic diagram of the structure obtained after growing the sacrificial oxide layer according to the present invention.

[0039] Figure 4 This is a schematic diagram of the structure obtained after etching the sacrificial oxide layer according to the present invention.

[0040] Figure 5 This is a schematic diagram of the structure obtained after N+ ion implantation according to the present invention.

[0041] Figure 6 This is a schematic diagram of the structure obtained after P+ ion implantation according to the present invention.

[0042] Figure 7 This is a schematic diagram of the structure obtained after thermal oxidation of the present invention.

[0043] Figure 8 This is a schematic diagram of the structure obtained after etching the oxide layer according to the present invention.

[0044] Figure 9 This is a schematic diagram of the structure obtained by growing an ohmic contact metal according to the present invention.

[0045] Figure 10 This is a schematic diagram of the structure obtained after growing gate metal according to the present invention.

[0046] Figure 11 This is a schematic diagram of the CMOS device structure of the present invention.

[0047] Figure 12 This is a schematic diagram of the structure obtained after the growth field oxide layer of the present invention.

[0048] Figure 13 This is a schematic diagram of the structure obtained after etching through-holes in this invention.

[0049] Figure 14 This is a schematic diagram illustrating the specific implementation of the CMOS inverter of the present invention, showing the structure after the metallized interconnects are formed.

[0050] Figure 15 This is a schematic diagram of the structure of a P-well CMOS device in the prior art.

[0051] Figure 16 This is a comparison of the transfer characteristic curves and mobility curves of the CMOS of this invention and the traditional P-well silicon carbide CMOS in the Sentaurus TCAD simulation.

[0052] Explanation of reference numerals in the attached figures 1. Silicon carbide wafer substrate; 2. Lightly doped N-type epitaxial layer of silicon carbide; 3. Lightly doped P-type epitaxial layer of silicon carbide; 4. P-type doped mesa of silicon carbide; 5. N+ type ion implantation region; 6. P+ type ion implantation region; 7. Gate oxide layer; 8. Ohmic contact opening; 9. Ohmic contact; 10. Gate structure; D1, N-channel MOS device; D2, P-channel MOS device; D1.1, NMOS body electrode; D1.2, NMOS source electrode; D1.3, NMOS drain electrode; D1.4, NMOS gate electrode; D2.1, PMOS body electrode; D2.2, PMOS source electrode; D2.3, PMOS drain electrode; D2.4, PMOS gate electrode; A1, Silicon carbide substrate; A2, Lightly doped N-type silicon carbide epitaxial layer; A3, Ion implanted P-well; A4, Gate oxide layer; A5, N+ type ion implantation region; A6, P+ type ion implantation region; A7, Gate structure b; A8, Ohmic contact; TD1, N-channel MOS device; TD2, P-channel MOS device. Detailed Implementation

[0053] The specific embodiments of the present invention are described in detail below, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention. Unless otherwise specified, the experimental methods described in the embodiments of the present invention are conventional methods.

[0054] The inventors discovered that in existing silicon carbide CMOS processes, high-energy P-type ion implantation is commonly used on an N-type epitaxial silicon carbide substrate to create a local P-type surface, which serves as the body region of the NMOS, while the original N-type epitaxial surface serves as the body region of the PMOS. The structure is as follows: Figure 11 As shown. The existing technology has the following difficulties: (1) High-energy ion implantation has high equipment requirements; (2) High-energy ion implantation is Gaussian distribution, and it is difficult to control the concentration in the surface channel region, and it is difficult to control the implantation dose and energy; (3) The development cycle of trap region ion implantation process is long and the cost is high; (4) High-energy ion implantation will introduce a large amount of lattice damage, which will affect the surface channel mobility.

[0055] In view of this, the present invention provides a silicon carbide CMOS device based on a P-type doped mesa structure and its fabrication method, which solves the defects in the prior art. This fabrication method does not require high-energy ion implantation to create a P-type well when fabricating silicon carbide CMOS devices. Instead, it creates a local P-type surface through a single P-type epitaxy and mesa etching. The inventive concept of the present invention is as follows: (1) the surface lattice damage caused by etching can be eliminated by sacrificial oxide layer SOX and high-temperature thermal annealing; (2) the channel doping concentration can be controlled more precisely; (3) the process development cycle is shortened; and (4) the required etching and epitaxy costs are low. Therefore, this scheme can obtain more ideal CMOS device mobility and threshold voltage.

[0056] To realize the above-mentioned device, the present invention provides a design of five photomasks required for fabrication.

[0057] (1) Dicing groove, alignment mark and P-type stage photomask (first photomask m1) (2) N-type ion implantation photomask (second photomask m2) (3) P-type ion implantation photomask (third photomask m3) (4) Oxide layer through-hole and ohmic contact photomask (fourth photomask m4) (5) Gate photomask (the fifth photomask m5) like Figures 1-10 As shown, this invention provides a method for fabricating a silicon carbide CMOS device based on a P-type doped mesa structure. The following steps are achieved on a silicon carbide wafer substrate 1 using five photolithography plates: An n-type silicon carbide epitaxial layer is epitaxially grown from bottom to top on a silicon carbide wafer substrate 1 to obtain a silicon carbide N-type lightly doped epitaxial layer 2. Then, a p-type silicon carbide epitaxial layer is epitaxially grown above the silicon carbide N-type lightly doped epitaxial layer 2 to obtain a silicon carbide P-type lightly doped epitaxial layer 3. Positive photoresist is coated on the surface of epitaxial layer 3, and photolithography is performed using a photolithography plate m1. The photoresist is patterned using photolithography processes such as exposure, development, and hardening to form a patterned photoresist. The silicon carbide P-type lightly doped epitaxial layer 3 is etched to obtain a silicon carbide P-type doped mesa 4, and the photoresist is removed.

[0058] The silicon carbide wafer is placed in a high temperature and oxygen atmosphere for thermal oxidation, which causes the silicon carbide P-type doped mesa 4 to undergo a thermal oxidation reaction to grow a sacrificial oxide layer SOX. The sacrificial oxide layer SOX is then completely etched using a hydrofluoric acid solution.

[0059] A silicon dioxide ion implantation mask is deposited on the surface of a silicon carbide wafer using plasma-enhanced chemical vapor deposition (PECVD). Positive photoresist is coated on the surface of the ion implantation mask, and photolithography is performed using an m2 photomask. The photoresist is patterned using photolithography processes such as exposure, development, and hardening to form a patterned photoresist. The silicon dioxide mask is etched to obtain an N+ type ion implantation window, and the photoresist is removed. Then, the silicon carbide wafer is subjected to low-energy, high-concentration nitrogen ion implantation to obtain an N+ type ion implantation region 5. Next, a silicon dioxide mask is deposited on the silicon carbide P-type doped mesa 4 using PECVD. Positive photoresist is coated on the surface of the ion implantation mask, and photolithography is performed using an m2 photomask. The photoresist is patterned using photolithography processes such as exposure, development, and hardening to form a patterned photoresist. The silicon dioxide mask is etched to obtain the P+ type ion implantation window, and the photoresist is removed. Low-energy, high-concentration aluminum ion implantation is performed on the silicon carbide wafer to obtain the P+ type ion implantation region 6. The implanted ions are activated by thermal annealing at high temperature.

[0060] The silicon carbide wafer is placed in a high temperature and oxygen atmosphere for thermal oxidation, so that the silicon carbide P-type doped mesa 4 undergoes thermal oxidation reaction to grow the gate oxide layer 7.

[0061] A negative photoresist is coated on the surface of the gate oxide layer 7. Photolithography is performed using an m4 photomask, employing exposure, development, and hardening processes to pattern the photoresist and form a patterned photoresist. The gate oxide layer 7 is then etched to obtain the ohmic contact opening structure 8. Ohmic contact metal is deposited on the surface of a silicon carbide wafer. Negative and positive photoresist are coated on the surface of the ohmic contact metal. Photolithography is performed using an m4 photomask, employing exposure, development, and hardening processes to pattern the photoresist and form a patterned photoresist. The ohmic contact metal is wet-etched to form the ohmic contact 9, and then the ohmic contact metal is thermally annealed to form a good low-resistivity ohmic contact.

[0062] A gate metal is deposited and grown on the surface of a silicon carbide wafer. A positive photoresist is coated on the surface of the gate metal. Photolithography is performed using an m5 photolithography plate. The photoresist is patterned using photolithography processes such as exposure, development, and hardening to form a patterned photoresist. The gate metal is then etched to form the gate structure 10.

[0063] Specifically, the silicon carbide substrate wafer is an N-type conductivity substrate with a doping concentration of 1E17~5E18. The doping concentration of the n-type silicon carbide epitaxial layer is 5×10⁻⁶. 15 cm -3 ~5×10 16 cm -3 The thickness of the n-type silicon carbide epitaxial layer is 5 μm to 15 μm; the doping concentration of the p-type silicon carbide epitaxial layer is 5 × 10⁻⁶. 15 cm -3 ~5×10 16 cm -3 The thickness of the p-type silicon carbide epitaxial layer is 1µm-2µm.

[0064] Specifically, the thickness of the sacrificial oxide layer (SOX) is 20 nm to 40 nm, the growth temperature range of the sacrificial oxide layer (SOX) is 1200 °C to 1400 °C, and the oxidation time is 30 min to 60 min.

[0065] Specifically, the concentration of nitrogen ions implanted in the N+ type ion implantation region 5 is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 The depth of N+ ion implantation region 5 is 0.3 μm to 0.7 μm; the concentration of aluminum ions implanted in P+ ion implantation region 6 is 1 × 10⁻⁶. 19 cm -3~5×10 19 cm -3 The depth of the P+ type ion implantation region 6 is 0.2 μm to 0.4 μm.

[0066] Specifically, the thermal annealing temperature for activating implanted ions is 1500℃~1600℃, and the thermal annealing time is 20min~40min.

[0067] Specifically, the thickness of the gate oxide layer 7 is 30nm~70nm, the growth temperature of the gate oxide layer 7 is 1200℃~1400℃, and the oxidation time is 30min~60min.

[0068] Specifically, the ohmic contact metal is any one of Ni metal, Ti / Ni metal stack, or Ni / Ti / Al metal stack, and the thickness of the ohmic contact metal is 30nm~100nm.

[0069] Specifically, the heat annealing temperature for forming the low-resistance ohmic contact 9 is 900℃~1000℃, and the heat annealing time is 5min.

[0070] Specifically, the material for depositing and growing the gate metal is any one of Al metal, Ti / Al metal stack, or Ti / Au metal stack, and the thickness of the deposited and grown gate metal is 300nm~500nm.

[0071] This invention provides a method for fabricating silicon carbide CMOS devices based on a P-type doped mesa structure.

[0072] Specifically, the silicon carbide CMOS device includes an N-channel MOS device D1 and a P-channel MOS device D2. The N-channel MOS device D1 includes a P-type doped mesa structure 4 and N-type heavily doped ion implantation regions 5, P-type heavily doped ion implantation regions 6, gate oxide layer 7, ohmic contact 9, and gate structure 10 located on the upper surface of the P-type doped mesa structure 4; the P-channel MOS device D2 includes a silicon carbide N-type lightly doped epitaxial layer 2 and N-type heavily doped ion implantation regions 5, P-type heavily doped ion implantation regions 6, gate oxide layer 7, ohmic contact 9, and gate structure 10 located on the upper surface of the silicon carbide N-type lightly doped epitaxial layer 2.

[0073] The N-channel MOS device D1 includes an NMOS body electrode D1.1; an NMOS source electrode D1.2; an NMOS drain electrode D1.3; and an NMOS gate electrode D1.4. An ohmic contact 9 located on the upper surface of the P-type doped mesa 4 and the upper surface of the P-type heavily doped ion implantation region 6 is the NMOS body electrode D1.1 in the N-channel MOS device D1. An ohmic contact 9 located on the upper surface of the P-type doped mesa 4 and the upper surface of the N-type heavily doped ion implantation region 5, and close to the NMOS body electrode D1.1... The ohmic contact 9 on the side is the NMOS source electrode D1.2 in the N-channel MOS device D1; the ohmic contact 9 located on the upper surface of the P-type doped mesa 4 and the upper surface of the N-type heavily doped ion implantation region 5, and away from the NMOS body electrode D1.1, is the NMOS drain electrode D1.3 in the N-channel MOS device D1; the gate structure 10 located above the gate oxide layer 7 and between the NMOS source electrode D1.1 and the NMOS drain electrode D1.3 is the NMOS gate electrode D1.4 in the N-channel MOS device D1.

[0074] The P-channel MOS device D2 includes a PMOS body electrode D2.1, a PMOS source electrode D2.2, a PMOS drain electrode D2.3, and a PMOS gate electrode D2.4. The ohmic contact 9, located on the upper surface of the lightly doped N-type epitaxial layer 2 and on the upper surface of the heavily doped N-type ion implantation region 5, is the PMOS body electrode D2.1 in the P-channel MOS device D2. The ohmic contact 9, located on the upper surface of the lightly doped N-type epitaxial layer 2 and on the upper surface of the heavily doped P-type ion implantation region 6, and close to the PMOS body electrode D2.1, is also present. Contact 9 is the PMOS source electrode D2.2 in the P-channel MOS device D2; the ohmic contact 9 located on the upper surface of the lightly doped N-type epitaxial layer 2 and on the upper surface of the heavily doped P-type ion implantation region 6, and away from the PMOS body electrode D2.1, is the PMOS drain electrode D2.3 in the P-channel MOS device D2; the gate structure 10 located above the gate oxide layer 7 and between the PMOS source electrode D2.1 and the PMOS drain electrode D2.3 is the NMOS gate electrode D2.4 in the P-channel MOS device D2.

[0075] Using dielectric isolation and metallization interconnection technology, the electrodes of N-channel MOS device D1 and P-channel MOS device D2 can be interconnected to form a functional circuit. The connection relationship is as follows: connect the NMOS source electrode D1.2 to the NMOS body electrode D1.1 and connect it to ground potential GND; connect the PMOS source electrode D2.2 to the PMOS body electrode D2.1 and connect it to digital power supply VDD; connect the NMOS gate electrode D1.4 to the PMOS gate electrode D2.4 and connect it to inverter input IN; connect the NMOS drain electrode D1.3 to the PMOS drain electrode D2.3 and connect it to inverter output OUT.

[0076] Figure 14 A method for metallizing and connecting an integrated inverter based on a P-type doped mesa structure of silicon carbide CMOS device is presented. This method involves depositing electrodes to connect the ohmic contact metal drains of a silicon carbide N-channel MOSFET and a silicon carbide P-channel MOSFET, and then bringing out the electrodes to serve as the output terminal of the inverter. Electrode deposition is also used to connect the metal gates of the silicon carbide N-channel MOSFET and the metal gate of the silicon carbide P-channel MOSFET, and then bringing out the electrodes to serve as the input terminal of the inverter. Furthermore, the ohmic contact metal source of the silicon carbide P-channel MOSFET is connected to the ohmic contact metal body electrode, and then bringing out the electrodes to the highest potential VDD. Finally, the ohmic contact metal source of the silicon carbide N-channel MOSFET is connected to the ohmic contact metal body electrode, and then bringing out the electrodes to the lowest potential GND. Figures 12-14 The physical implementation method of the above-mentioned CMOS integrated inverter is given. A method for fabricating a mesa-structured silicon carbide CMOS device integrated circuit inverter includes the following steps: To realize a silicon carbide CMOS integrated inverter, the design of the two photomasks required for fabrication is presented. (1) Interlayer interconnection via photolithography plate (sixth photolithography plate m6) (2) Metal interconnect photomask (seventh photomask m7) The steps for fabricating metallized interconnects using two photolithography plates to realize a CMOS integrated inverter are as follows: exist Figure 11 Based on the silicon carbide CMOS device fabrication method shown, which uses a P-type doped mesa structure, a silicon dioxide dielectric layer with a thickness of 0.7 μm to 1.2 μm is deposited using PECVD. Figure 12 The structure shown is a field oxide (FOX).

[0077] The positive photoresist transfer pattern was created using a photolithography plate m6, and the structured field oxide layer FOX was etched using ICP etching. The etching thickness was consistent with the deposition thickness. Figure 13 The diagram shows the interlayer interconnect vias (Via) and the interlayer isolation medium (ILD).

[0078] Deposit or evaporate Ti / Al metal stacks. Use photoresist (m7) to create a positive photoresist transfer pattern, then wet-etch the metal to obtain... Figure 14 The structure shown is a metal interconnect.

[0079] Specifically, the thickness of the structural field oxide layer (FOX) is 0.7 μm to 1.2 μm. Specifically, the depth of the through-hole is 0.7um to 1.2um.

[0080] Specifically, in the metal interconnect metal stack, the thickness of Ti is 10nm~30nm, and the thickness of Al is 300nm~700nm.

[0081] The following provides specific embodiments based on the aforementioned method for fabricating and applying silicon carbide CMOS devices with P-type doped mesa structures.

[0082] Example 1 The fabrication method of silicon carbide CMOS devices based on P-type doped mesa structures includes the following steps: A 6-inch conductive silicon carbide substrate was selected for the process. An n-type epitaxial layer was grown from bottom to top on the silicon carbide substrate 1 to obtain a lightly doped N-type silicon carbide epitaxial layer 2. Then, a p-type epitaxial layer was grown on top of the lightly doped N-type silicon carbide epitaxial layer 2 to obtain a lightly doped P-type silicon carbide epitaxial layer 3. The doping concentration of the n-type silicon carbide epitaxial layer was 1×10⁻⁶. 16 cm -3 The thickness is 10 μm; the doping concentration of the p-type silicon carbide epitaxial layer is 1 × 10⁻⁶. 16 cm -3 The thickness is 1.5 μm. A positive photoresist is coated on the surface of the epitaxial layer 3, and photolithography is performed using an m1 photolithography plate. The photoresist is patterned using photolithography processes such as exposure, development, and hardening to form a patterned photoresist. The silicon carbide N-type lightly doped epitaxial layer 3 is etched using inductively coupled plasma (ICP) etching to obtain a silicon carbide wafer with silicon carbide P-type doped mesa 4.

[0083] The silicon carbide wafer is placed in a high temperature and oxygen atmosphere for thermal oxidation, which causes a sacrificial oxide layer SOX to grow on the surface of the silicon carbide wafer. The thickness of the sacrificial oxide layer SOX is 30 nm. Then, the sacrificial oxide layer SOX is completely etched with hydrofluoric acid solution.

[0084] Nitrogen ion implantation was performed on the surface of a silicon carbide wafer to obtain an N+ type ion implantation region 5; aluminum ion implantation was performed to obtain a P+ type ion implantation region 6; the peak ion doping concentration of the N+ type ion implantation region 5 was 1×10⁻⁶. 19 cm -3 The junction depth of N+ type ion implantation region 5 is 0.5 μm; the peak ion doping concentration of P+ type ion implantation region 6 is 3 × 10⁻⁶. 19 cm -3 The junction depth of P+ type ion implantation region 6 is 0.3 μm.

[0085] The steps for obtaining N+ type ion implantation region 5 by nitrogen ion implantation on the surface of silicon carbide wafer are as follows: A 2µm silicon dioxide mask was deposited on the surface of a silicon carbide wafer using plasma-enhanced chemical vapor deposition (PECVD). Positive photoresist was coated onto the silicon dioxide mask surface, and photolithography was performed using an m² photomask. The photoresist was patterned using photolithography processes including exposure, development, and hardening to form a patterned photoresist. The silicon dioxide mask was then etched using inductively coupled plasma (ICP) to remove the photoresist. Nitrogen ion implantation was performed at 500°C with an implantation rate of 1E¹⁴ cm⁻¹. -2 The injection energy was 40keV, and then wet etching with hydrofluoric acid solution was used to completely remove the surface silicon dioxide mask.

[0086] The steps involved in obtaining the P+ type ion implantation region 6 by aluminum ion implantation on the surface of a silicon carbide wafer are as follows: A 2µm silicon dioxide film was deposited on the surface of the silicon carbide p-type doped mesa 4 using plasma-enhanced chemical vapor deposition (PECVD). Positive photoresist was coated onto the silicon dioxide mask surface, and photolithography was performed using an m3 photomask. The photoresist was patterned using photolithography processes including exposure, development, and hardening to form a patterned photoresist. The silicon dioxide mask was etched using inductively coupled plasma (ICP) to remove the photoresist. Aluminum ion implantation was performed at 600°C with an implantation metering of 1E14cm. -2 The injection energy was 60kV. Wet etching with hydrofluoric acid solution was used to remove the surface silicon dioxide mask.

[0087] A 100 nm thick carbon film was sputtered onto the surface of a silicon carbide wafer, and then thermally annealed at 1550 °C for 30 min to activate implanted ions, remove the carbon film, and clean the wafer.

[0088] A gate oxide layer 7 is grown by thermal oxidation reaction on the wafer surface in an oxygen atmosphere at a high temperature of 1250℃. The thickness of the gate oxide layer 7 is 45nm. The steps for photolithography and etching (i.e., removing the gate oxide layer at the source, drain, and body electrode locations of silicon carbide NMOS and PMOS transistors) of gate oxide layer 7 are as follows: The gate oxide layer 7 is removed by inductively coupled plasma (ICP) etching or wet etching with a buffered oxide etchant. Specifically, the ICP etching process for the gate oxide layer 7 involves: coating a negative photoresist onto the gate oxide layer surface; performing photolithography using an m4 photomask; and patterning the photoresist using exposure, development, and hardening processes to form a patterned photoresist. After etching the oxide layer 7 using an ICP device, the surface-coated photoresist is removed, forming the ohmic contact opening 8.

[0089] 50nm Ni metal is evaporated or deposited, and positive photoresist is coated on the metal surface. Photolithography is performed using an m4 photomask, employing exposure, development, and hardening processes to pattern the photoresist and form a patterned photoresist. The metal is then wet-etched with an acid solution to form ohmic contacts 9, and the photoresist is removed. Finally, a thermal annealing treatment is performed at 950℃ for 5 minutes to form good ohmic contacts.

[0090] 300 nm Al metal is evaporated or deposited on the surface of a silicon carbide wafer. Positive photoresist is coated on the gate metal surface, and photolithography is performed using an m5 photomask. The photoresist is patterned using photolithography processes such as exposure, development, and hardening to form a patterned photoresist. The gate metal is etched with an acid solution to remove the photoresist and form the gate structure 10.

[0091] Example 2 The fabrication method of silicon carbide CMOS devices based on P-type doped mesa structures includes the following steps: A 6-inch conductive silicon carbide substrate was selected for the process. An n-type epitaxial layer was epitaxially grown from bottom to top on the silicon carbide substrate 1 to obtain a lightly doped N-type silicon carbide epitaxial layer 2. Then, a p-type epitaxial layer was epitaxially grown above the lightly doped N-type silicon carbide epitaxial layer 2 to obtain a lightly doped P-type silicon carbide epitaxial layer 3. The doping concentration of the n-type silicon carbide epitaxial layer was 5 × 10⁻⁶. 15 cm -3 The thickness is 10 μm; the doping concentration of the p-type silicon carbide epitaxial layer is 5 × 10⁻⁶. 15 cm -3 The thickness is 2 μm. Positive photoresist is coated on the surface of the epitaxial layer 3, and photolithography is performed using an m1 photolithography plate. The photoresist is patterned using photolithography processes such as exposure, development, and hardening to form a patterned photoresist. The silicon carbide N-type lightly doped epitaxial layer 3 is etched using inductively coupled plasma (ICP) to obtain a silicon carbide wafer with silicon carbide P-type doped mesa 4.

[0092] The silicon carbide wafer is placed in a high temperature and oxygen atmosphere for thermal oxidation, which causes the silicon carbide P-type doped mesa 4 to undergo a thermal oxidation reaction to grow a sacrificial oxide layer SOX with a thickness of 40 nm. Then, the sacrificial oxide layer SOX is completely etched using a hydrofluoric acid solution.

[0093] Nitrogen ion implantation was performed on the surface of a silicon carbide wafer to obtain an N+ type ion implantation region 5; aluminum ion implantation was performed to obtain a P+ type ion implantation region 6; the peak doping concentration of the N+ type ion implantation region 5 was 5 × 10⁻⁶. 18 cm -3 The junction depth of N+ ion implantation region 5 is 0.7 μm; the peak doping concentration of P+ ion implantation region 6 is 1 × 10⁻⁶. 19 cm-3 The junction depth of P+ type ion implantation region 6 is 0.4 μm.

[0094] The steps for obtaining N+ type ion implantation region 5 by nitrogen ion implantation on the surface of silicon carbide wafer are as follows: A 2µm silicon dioxide mask was deposited on the surface of a silicon carbide wafer using plasma-enhanced chemical vapor deposition (PECVD). Positive photoresist was coated onto the silicon dioxide mask surface, and photolithography was performed using an m² photomask. The photoresist was patterned using photolithography processes including exposure, development, and hardening to form a patterned photoresist. The silicon dioxide mask was then etched using inductively coupled plasma (ICP) to remove the photoresist. Nitrogen ion implantation was performed at 500°C with an implantation metering of 1E¹³cm. -2 The injection energy was 60keV, and then wet etching with hydrofluoric acid solution was used to completely remove the surface silicon dioxide mask.

[0095] The steps for obtaining the P+ type ion implantation region 6 by aluminum ion implantation on the surface of a silicon carbide wafer are as follows: A 2µm silicon dioxide mask was deposited on the surface of a silicon carbide wafer using plasma-enhanced chemical vapor deposition (PECVD). Positive photoresist was coated onto the silicon dioxide mask surface, and photolithography was performed using an m3 photomask. The photoresist was patterned using photolithography processes including exposure, development, and hardening to form a patterned photoresist. The silicon dioxide mask was then etched using inductively coupled plasma (ICP) to remove the photoresist. Aluminum ion implantation was performed at 600°C with an implantation metering of 1E13cm. -2 The injection energy was 110 kV. Wet etching with hydrofluoric acid solution was used to remove the surface silicon dioxide mask.

[0096] Then, a 100nm thick carbon film is sputtered onto the surface of the silicon carbide wafer, and thermal annealing is performed at 1600℃ for 30 minutes to activate implanted ions, remove the carbon film, and clean the wafer.

[0097] A gate oxide layer 7 is grown on the surface of the silicon carbide wafer by thermal oxidation reaction in an oxygen atmosphere at a high temperature of 1250℃. The thickness of the gate oxide layer 7 is 70nm. The steps for photolithography and etching of gate oxide layer 7 (i.e., removing the gate oxide layer at the source, drain, and body electrode positions of silicon carbide NMOS and PMOS transistors) are as follows: The gate oxide layer 7 is removed by inductively coupled plasma (ICP) etching or wet etching with a buffered oxide etchant. Specifically, the ICP etching process for the gate oxide layer 7 involves: coating a negative photoresist onto the gate oxide layer surface; performing photolithography using an m4 photomask; and patterning the photoresist using photolithography processes such as exposure, development, and hardening to form a patterned photoresist. Then, the gate oxide layer 7 is etched using an ICP device to remove the coated photoresist, forming the ohmic contact opening 8.

[0098] A 10nm / 30nm / 80nm Ti / Ni / Al metal stack is deposited by vapor deposition or evaporation. Positive photoresist is coated onto the metal layer surface, and photolithography is performed using an m5 photomask. The photoresist is patterned using photolithography processes including exposure, development, and hardening to form a patterned photoresist. After etching the metal layer with an acid solution, the photoresist is removed, forming an ohmic contact metal structure. Thermal annealing is then performed at 950℃ for 5 minutes to form a good ohmic contact.

[0099] 300nm Al metal is evaporated or deposited on the surface of a silicon carbide wafer. Positive photoresist is coated on the surface of the gate oxide layer. Photolithography is performed using an m5 photolithography plate. The photoresist is patterned using photolithography processes such as exposure, development, and hardening to form a patterned photoresist. The gate metal is etched with an acid solution to remove the photoresist and form the gate structure 10.

[0100] Example 3 The fabrication method of silicon carbide CMOS devices based on P-type doped mesa structures includes the following steps: A 6-inch conductive silicon carbide substrate was selected for the process. An n-type epitaxial layer was epitaxially grown from bottom to top on the silicon carbide substrate 1 to obtain a lightly doped N-type silicon carbide epitaxial layer 2. Then, a p-type epitaxial layer was epitaxially grown above the lightly doped N-type silicon carbide epitaxial layer 2 to obtain a lightly doped P-type silicon carbide epitaxial layer 3. The doping concentration of the n-type silicon carbide epitaxial layer was 5 × 10⁻⁶. 16 cm -3 The thickness is 5 μm; the doping concentration of the p-type silicon carbide epitaxial layer is 5 × 10⁻⁶. 16 cm -3 The thickness is 1µm; positive photoresist is coated on the surface of the epitaxial layer 3, and photolithography is performed using an m1 photolithography plate. The photoresist is patterned using photolithography processes such as exposure, development, and hardening to form a patterned photoresist. A silicon carbide wafer with silicon carbide p-type doped mesa 4 is prepared by etching the silicon carbide N-type lightly doped epitaxial layer using inductively coupled plasma (ICP).

[0101] The silicon carbide wafer is placed in a high temperature and oxygen atmosphere for thermal oxidation, which causes a sacrificial oxide layer SOX to grow on the surface of the silicon carbide wafer. The thickness of the sacrificial oxide layer SOX is 20 nm. Then, the sacrificial oxide layer SOX is completely etched with hydrofluoric acid solution.

[0102] Nitrogen ion implantation was performed on the surface of a silicon carbide wafer to obtain an N+ type ion implantation region 5; aluminum ion implantation was performed to obtain a P+ type ion implantation region 6; the peak doping concentration of the N+ type ion implantation region 5 was 5 × 10⁻⁶. 19 cm -3 The junction depth of N+ ion implantation region 5 is 0.7 μm; the peak doping concentration of P+ ion implantation region 6 is 5 × 10⁻⁶. 19 cm -3 The junction depth of P+ type ion implantation region 6 is 0.3 μm.

[0103] The step of obtaining N+ type ion implantation region 5 by nitrogen ion implantation on the surface of silicon carbide wafer is as follows: A 2µm silicon dioxide mask was deposited on the surface of a silicon carbide wafer using plasma-enhanced chemical vapor deposition (PECVD). Positive photoresist was coated onto the silicon dioxide mask surface, and photolithography was performed using an m² photomask. The photoresist was patterned using photolithography processes including exposure, development, and hardening to form a patterned photoresist. The silicon dioxide mask was then etched using inductively coupled plasma (ICP) to remove the photoresist. Nitrogen ion implantation was performed at 500°C with an implantation metering of 1E15cm. -2 The injection energy is 30keV, and then wet etching with hydrofluoric acid solution is used to completely remove the surface silicon oxide mask.

[0104] The steps involved in obtaining the P+ type ion implantation region 6 by aluminum ion implantation on the surface of a silicon carbide wafer are as follows: A 2µm silicon dioxide mask was deposited on the surface of a silicon carbide wafer using plasma-enhanced chemical vapor deposition (PECVD). Positive photoresist was coated onto the silicon dioxide mask surface. Photolithography was performed using an m3 photomask, employing exposure, development, and hardening processes to pattern the photoresist and form a patterned photoresist. The silicon dioxide mask was then etched using inductively coupled plasma (ICP) to remove the photoresist. Aluminum ion implantation was performed at 600°C with an implantation metering of 1E15cm. -2 The injection energy was 70kV. Wet etching with hydrofluoric acid solution was used to remove the surface silicon oxide mask.

[0105] Then, a 100 nm thick carbon film is sputtered and deposited on the surface of the silicon carbide wafer, and thermal annealing is performed at 1600 degrees Celsius for 30 min to activate implanted ions, remove the carbon film, and clean the wafer.

[0106] In an oxygen atmosphere at a high temperature of 1200℃, the silicon carbide P-type doped mesa 4 is thermally oxidized to grow a gate oxide layer 7 with a thickness of 30nm. The steps for photolithography and etching of gate oxide layer 7 (i.e., removing the gate oxide layer at the source, drain, and body electrode positions of silicon carbide NMOS and PMOS transistors) are as follows: The gate oxide layer 7 is removed by inductively coupled plasma (ICP) etching or wet etching with a buffered oxide etchant. Specifically, the ICP etching process for the gate oxide layer 7 involves: coating a negative photoresist onto the gate oxide layer surface; performing photolithography using an m4 photomask; and patterning the photoresist using photolithography processes such as exposure, development, and hardening to form a patterned photoresist. Then, the gate oxide layer 7 is etched using an ICP device to remove the coated photoresist, forming the ohmic contact opening 8.

[0107] A 10nm / 30nm Ti / Ni metal stack is deposited by vapor deposition or evaporation. Positive photoresist is coated onto the metal layer surface, and photolithography is performed using an m5 photomask. The photoresist is patterned using photolithography processes including exposure, development, and hardening to form a patterned photoresist. After etching the metal layer with an acid solution, the photoresist is removed, forming an ohmic contact metal structure. Thermal annealing is then performed at 950℃ for 5 minutes, resulting in a good ohmic contact.

[0108] 300nm Al metal is evaporated or deposited on the surface of a silicon carbide wafer. Positive photoresist is coated on the surface of the gate oxide layer. Photolithography is performed using an m5 photolithography plate. The photoresist is patterned using photolithography processes such as exposure, development, and hardening to form a patterned photoresist. The gate metal is etched with an acid solution to remove the photoresist and form the gate structure 10.

[0109] Example 4 The method for metallization and interconnection of silicon carbide CMOS inverters based on P-type doped mesa structures includes the following steps: Based on the device obtained in Example 1, a silicon dioxide dielectric layer with a thickness of 1 μm was deposited on the surface of a silicon carbide wafer using PECVD to form a layer as shown in Example 1. Figure 12 The field oxide layer structure shown is FOX.

[0110] A positive photoresist is coated onto the surface of a silicon dioxide layer. Photolithography is performed using an M6 photomask, employing exposure, development, and hardening processes to pattern the photoresist and form a patterned photoresist layer. The silicon dioxide dielectric layer is then etched using ICP to a depth of 1 μm to remove the photoresist, resulting in a patterned photoresist layer. Figure 13 The through-hole structure shown is Via.

[0111] A 20nm / 500nm Ti / Al metal stack was deposited on the wafer surface by vapor deposition. Positive photoresist was coated onto the metal layer surface, and photolithography was performed using an m7 photomask. The photoresist was patterned using photolithography processes including exposure, development, and hardening to form a patterned photoresist. The metal was then etched using an acid solution to remove the photoresist, forming a patterned metal substrate. Figure 14 The interconnect structure shown is interconnects.

[0112] Comparison Example like Figure 15 As shown, a P-well-based CMOS device is presented, comprising an N-channel MOS device TD1 and a P-channel MOS device TD2. The fabrication method of the P-well-based CMOS device includes the following steps: A six-inch conductive silicon carbide substrate wafer was used for the process flow. A lightly doped silicon carbide N-type epitaxial layer A2 (referred to as silicon carbide N-epitaxial layer A2) was grown from bottom to top on the silicon carbide substrate A1. The epitaxial thickness of silicon carbide N-epitaxial layer A2 was 5 μm, and the doping concentration of silicon carbide N-epitaxial layer A2 was 1E16 cm⁻¹. -3 .

[0113] Aluminum ion implantation was performed on the surface of the silicon carbide N-epitaxial layer A2 to obtain an ion implantation P-well A3; nitrogen ion implantation was performed to obtain an N+ type ion implantation region A5; and aluminum ion implantation was performed to obtain a P+ type ion implantation region A6. The peak doping concentration of the ion implantation P-well A3 was 1E18cm⁻¹. -3 The surface doping concentration of the ion-implanted P-well A3 is 1E17cm⁻¹. -3 The junction depth is 1 μm. The peak doping concentration of the N+ type ion implantation region A5 is 5 × 10⁻⁶. 18 cm -3 The junction depth of the N+ type ion implantation region bA5 is 0.5 μm; the peak doping concentration of the P+ type ion implantation region A6 is 1 × 10⁻⁶. 19 cm -3 The junction depth of the P+ type ion implantation region A6 is 0.3 μm.

[0114] The steps for obtaining the ion-implanted P-type well region A3 by aluminum ion implantation on the silicon carbide N-epitaxial layer A2 are as follows: A 2µm silicon dioxide film was deposited on the surface of the silicon carbide N-epitaxial layer A2 using plasma-enhanced chemical vapor deposition (PECVD). Positive photoresist was coated onto the silicon dioxide mask surface, and the photoresist was patterned using photolithography processes including exposure, development, and hardening to form a patterned photoresist. The photoresist was removed after etching the silicon dioxide mask using inductively coupled plasma (ICP). Aluminum ion implantation was performed at 600°C with an implantation metering of 1E13cm. -2The energy was injected at 200 keV, and then wet etching with hydrofluoric acid solution was used to completely remove the silicon dioxide mask.

[0115] The steps for obtaining the N+ ion implantation region bA5 by nitrogen ion implantation on the silicon carbide N-epitaxial layer A2 are as follows: A 2 μm silicon dioxide film was deposited on the surface of the silicon carbide N-epitaxial layer A2 using plasma-enhanced chemical vapor deposition (PECVD). Positive photoresist was coated onto the silicon dioxide mask surface, and the photoresist was patterned using photolithography processes including exposure, development, and hardening to form a patterned photoresist. The photoresist was removed after etching the silicon dioxide mask using inductively coupled plasma (ICP). Nitrogen ion implantation was performed at 500 °C with an implantation metering of 1E13 cm⁻¹. -2 The injection energy was 40keV, and then wet etching with hydrofluoric acid solution was used to completely remove the silicon dioxide mask.

[0116] The steps for obtaining the P+ type ion implantation region A6 by aluminum ion implantation on the silicon carbide N- epitaxial layer A2 are as follows: A 2µm silicon dioxide film was deposited on the surface of the silicon carbide N-epitaxial layer A2 using plasma-enhanced chemical vapor deposition (PECVD). Positive photoresist was coated onto the silicon dioxide mask surface, and the photoresist was patterned using photolithography processes including exposure, development, and hardening to form a patterned photoresist. The photoresist was removed after etching the silicon dioxide mask using inductively coupled plasma (ICP). Aluminum ion implantation was performed at 600°C with an implantation metering of 1E14cm. -2 The injection energy was 90keV, and then wet etching with hydrofluoric acid solution was used to completely remove the silicon oxide mask on the surface of the silicon carbide N-epitaxial layer A2.

[0117] A 100 nm thick carbon film was sputtered onto the surface of a silicon carbide wafer, and then thermally annealed at 1550 °C for 30 min to activate implanted ions, remove the carbon film, and clean the silicon carbide wafer.

[0118] A gate oxide layer A4 is grown by thermal oxidation reaction on the surface of silicon carbide N-epitaxial layer A2 in an oxygen atmosphere at a high temperature of 1250℃. The thickness of the gate oxide layer A4 is 45nm. The steps for etching the gate oxide layer A4 (i.e., removing the oxide layer above the source, drain, and body electrode locations of the NMOS and PMOS) are as follows: The gate oxide layer A4 is removed using inductively coupled plasma (ICP) etching or wet etching with a buffered oxide etchant. Specifically, the ICP etching process for the gate oxide layer A4 involves coating a positive photoresist onto the surface of the gate oxide layer A4, and then patterning the photoresist using photolithography processes such as exposure, development, and hardening to form a patterned photoresist. Finally, the gate oxide layer A4 is etched using an ICP device to remove the coated photoresist, forming an ohmic contact opening.

[0119] 50nm Ni metal is evaporated or deposited, and positive photoresist is coated on the metal surface. The photoresist is patterned using photolithography processes such as exposure, development, and hardening to form a patterned photoresist. Acid wet etching is then performed to remove the photoresist and form the ohmic contact A8. Finally, thermal annealing is performed at 950℃ for 5 minutes.

[0120] A 300nm Al metal is deposited and grown on the surface of a silicon carbide wafer. Positive photoresist is coated on the metal surface. The photoresist is patterned using photolithography processes such as exposure, development, and hardening to form a patterned photoresist. The aluminum metal is etched with an acid solution to remove the photoresist and form a gate structure bA7.

[0121] Silicon carbide CMOS devices can be prepared in all of the above examples 1 to 3. The silicon carbide CMOS device prepared in example 1 is selected for testing.

[0122] A schematic diagram of a P-well CMOS device given in the prior art is shown below. Figure 15 As shown, the silicon carbide CMOS device prepared by this invention is as follows: Figure 11 As shown, simulation experiments were conducted on P-well CMOS devices and silicon carbide CMOS devices. The Sentaurus silicon carbide default parameters were used for testing, and the results are as follows. Figure 16 As shown in the figure, the red dashed line represents the transfer characteristic curve of the NMOS device based on the P-type mesa structure proposed in this invention, and the red solid line represents the channel mobility curve of the NMOS device based on the P-type mesa structure proposed in this invention; the blue dashed line represents the transfer characteristic curve of the NMOS device based on the traditional P-well structure. Under given process parameters, the threshold voltage of the NMOS proposed in this invention is significantly lower than that of the P-well NMOS, making it more suitable for low-voltage logic integrated circuit applications. Furthermore, the mobility curve of the NMOS obtained in this invention has a significant advantage at the saturation region boundary.

[0123] 1. The fabrication method provided in this invention causes less lattice damage to the region where the N-channel MOS device is located, and the NMOS channel mobility is significantly higher than that of the P-well process.

[0124] 2. The fabrication method provided in this invention can repair surface damage introduced by dry etching of silicon carbide through sacrificial oxidation, and has little impact on the surface doping concentration of silicon carbide MOS design.

[0125] 3. The threshold voltage of the easily adjustable CMOS device can be further optimized by adjusting the doping concentration of the epitaxial layer (silicon carbide N-type lightly doped epitaxial layer 2 and silicon carbide P-type lightly doped epitaxial layer 3).

[0126] 4. High-energy ion implantation in P-trap processes avoids introducing deep defects, reduces the introduction of wafer stress in the process flow, and reduces wafer warpage during the process.

[0127] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for fabricating a silicon carbide CMOS device based on a p-type doped mesa structure, characterized in that, Includes the following steps: A silicon carbide N-type lightly doped epitaxial layer (2) and a silicon carbide P-type lightly doped epitaxial layer (3) are epitaxially grown sequentially from bottom to top on the upper surface of the N-type silicon carbide substrate (1). A portion of the silicon carbide P-type lightly doped epitaxial layer (3) is etched to expose the upper surface of the silicon carbide N-type lightly doped epitaxial layer (2) while forming a P-type doped mesa (4). A sacrificial oxide layer is grown on the surface of the P-type doped mesa (4) and the exposed silicon carbide N-type lightly doped epitaxial layer (2) by thermal oxidation reaction, and then the sacrificial oxide layer is completely removed. The upper surfaces of the silicon carbide N-type lightly doped epitaxial layer (2) and P-type doped mesa (4) after the sacrificial oxide layer has been completely removed are both implanted with N-type ions and P-type ions to form N-type heavily doped ion implantation regions (5) and P-type heavily doped ion implantation regions (6); then the implanted ions in the N-type heavily doped ion implantation regions (5) and P-type heavily doped ion implantation regions (6) are activated by high-temperature thermal annealing. Then, a gate oxide layer (7) is grown on the upper surface of the silicon carbide N-type lightly doped epitaxial layer (2) and P-type doped mesa (4) by thermal oxidation reaction. The gate oxide layer (7) is etched to obtain an ohmic contact opening (8). An ohmic contact (9) is formed inside the ohmic contact opening (8). The ohmic contact (9) is then subjected to thermal annealing treatment. Finally, gate metal is deposited and grown on the upper surface of the gate oxide layer (7) to form a gate structure (10).

2. The method for fabricating a silicon carbide CMOS device based on a P-type doped mesa structure according to claim 1, characterized in that, The doping concentration of the silicon carbide N-type lightly doped epitaxial layer (2) is 5 × 10⁻⁶. 15 cm -3 ~5×10 16 cm -3 The thickness of the silicon carbide N-type lightly doped epitaxial layer (2) is 5 μm to 15 μm; the doping concentration of the silicon carbide P-type lightly doped epitaxial layer (3) and the P-type doped mesa (4) is 5 × 10⁻⁶. 15 cm -3 ~5×10 16 cm -3 The thickness of the silicon carbide P-type lightly doped epitaxial layer (3) and the P-type doped mesa (4) is 1um to 2um.

3. The method for fabricating a silicon carbide CMOS device based on a P-type doped mesa structure according to claim 1, characterized in that, The peak concentration of nitrogen ions implanted in the N-type heavily doped ion implantation region (5) is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 The junction depth of the N-type heavily doped ion implantation region (5) is 0.3 μm to 0.7 μm; the peak concentration of aluminum ions implanted in the P-type heavily doped ion implantation region (6) is 1 × 10⁻⁶. 19 cm -3 ~5×10 19 cm -3 The junction depth of the P-type heavily doped ion implantation region (6) is 0.2 μm to 0.4 μm.

4. The method for fabricating a silicon carbide CMOS device based on a P-type doped mesa structure according to claim 3, characterized in that, The annealing temperature for activating the N-type heavily doped ion implantation region (5) and the P-type heavily doped ion implantation region (6) is 1500℃~1600℃, and the annealing time is 20min~40min.

5. The method for fabricating a silicon carbide CMOS device based on a P-type doped mesa structure according to claim 1, characterized in that, The thickness of the sacrificial oxide layer is 20nm~40nm, the thermal oxidation temperature range for growing the sacrificial oxide layer is 1200℃~1400℃, the oxidation time for growing the sacrificial oxide layer is 20min~60min, the thickness of the gate oxide layer (7) is 30nm~70nm, the thermal oxidation temperature range for growing the gate oxide layer (7) is 1200℃~1400℃, and the oxidation time for growing the gate oxide layer (7) is 45min~120min.

6. The method for fabricating a silicon carbide CMOS device based on a P-type doped mesa structure according to claim 1, characterized in that, The ohmic contact (9) is any one of Ni metal, Ti / Ni metal stack or Ni / Ti / Al metal stack, and the thickness of the ohmic contact metal is 30nm~100nm.

7. The method for fabricating a silicon carbide CMOS device based on a P-type doped mesa structure according to claim 6, characterized in that, The annealing temperature of the ohmic contact (9) is 900℃~1000℃, and the annealing time is 5min~10min.

8. The method for fabricating a silicon carbide CMOS device based on a P-type doped mesa structure according to claim 1, characterized in that, The material for depositing and growing the gate metal is any one of Al metal, Ti / Al metal stack, or Ti / Au metal stack, and the thickness of the deposited and grown gate metal is 300nm~500nm.

9. The silicon carbide CMOS device fabricated by the method for fabricating a silicon carbide CMOS device based on a P-type doped mesa structure according to any one of claims 1 to 8.

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