Embedded contact for SPAD applications

Abstract

The invention relates to an embedded contact for SPAD applications. Systems, devices, and methods are described for positioning contacts for a single photon avalanche diode (SPAD) in an isolation trench structure of an SPAD-based imager. Systems, devices, and methods may include a front-side isolation trench structure disposed between adjacent SPAD pixels, where the trench is lined with a continuous passivation layer having openings that allow conductive material filling the trench to contact the substrate and form buried contacts for one or more adjacent SPAD. The trench may include a stepped trench having an opening in the passivation layer proximate the stepped region. The trench may include an opening in the passivation layer toward a bottom of the front trench. The trench may include a backside trench having a high-k material. The backside trench may be continuous, or segmented, and / or overlapping. A buried SPAD contact as described herein may allow for a reduced pixel size.

Description

Technical Field

[0001] This application generally relates to devices based on single-photon avalanche diodes (SPADs), and more specifically to imagers that use SPAD pixel arrays to detect photons. Background Technology

[0002] An image sensor (also called an imager) can be formed from a two-dimensional array of light-sensing pixels. Each pixel typically includes a photosensitive element that receives incident photons and converts them into electrical signals. The photosensitive element can be a photodiode.

[0003] SPAD-based imagers can use SPADs configured to detect single photons. Photons incident on the SPAD device can induce avalanche currents, which can be detected by appropriate circuitry in the SPAD-based imager. SPAD pixels can generate photons during an avalanche, which can travel to adjacent SPAD pixels and cause one or more of them to avalanche. These additional avalanche currents are a result of crosstalk and are undesirable. Isolation structures can be placed between SPAD pixels to prevent crosstalk and / or other undesirable behavior.

[0004] As SPAD pixels continue to shrink, they force the cathode and anode of the SPAD device closer together. SPAD devices operate under a large reverse bias voltage between their cathode and anode. For small pixels, the electric field between the anode and cathode increases, leading to unwanted edge breakdown in the avalanche region of the SPAD.

[0005] Therefore, there is a need to provide improved devices and methods for forming SPAD pixels. Summary of the Invention

[0006] Various implementations relate to systems, apparatus, and methods for having trench isolation structures for embedded contacts for one or more SPAD pixels.

[0007] In various embodiments, a semiconductor device may include: a substrate having a front side and a back side; a first single-photon avalanche diode (SPAD) disposed in the substrate and having a first contact near the front side of the substrate, wherein the first contact is one of the cathode or anode of the SPAD; a second SPAD disposed in the substrate and positioned adjacent to the first SPAD; and a trench isolation structure disposed in the substrate between the first SPAD and the second SPAD, the trench isolation structure including: a front trench, a continuous passivation layer lining the front trench, wherein the passivation layer includes an opening at a horizontal surface of the front trench; and a conductive material disposed within the front trench and laterally separated from the substrate by the passivation layer, wherein: the conductive material is electrically coupled to the substrate through the opening of the passivation layer to form a second contact, and the second contact is another of the cathode or anode of the SPAD.

[0008] In various embodiments, a semiconductor device may include a substrate having a first surface and a second surface, wherein the first surface is one of a front side or a back side of the substrate, and the second surface is the other of a front side or a back side of the substrate. The semiconductor device may include a first single-photon avalanche diode (SPAD) and a second SPAD, the first SPAD being disposed within the substrate and having a first contact proximate to the first surface of the substrate, wherein the first contact is one of a cathode or anode of the SPAD, and the second SPAD being disposed within the substrate and positioned adjacent to the first SPAD. The semiconductor device may include a trench isolation structure disposed in a substrate between a first SPAD and a second SPAD. The trench isolation structure includes: a trench including a wide trench and a narrow trench, the wide trench being positioned near a first surface of the substrate and the narrow trench extending through the bottom surface of the wide trench toward a second surface of the substrate, wherein the trench includes a transition region between the wide trench and the narrow trench; a continuous passivation layer lining the wide trench and the narrow trench, wherein the passivation layer includes an opening at the transition region; and a conductive material disposed within the trench and laterally separated from the substrate through the passivation layer, wherein the conductive material is electrically coupled to the substrate through the opening in the passivation layer to form a second contact, and the second contact is either the cathode or the anode of the SPAD.

[0009] In various embodiments, a method for forming a trench isolation structure between a first single-photon avalanche diode (SPAD) and a second SPAD in a substrate, wherein the substrate has a front side and a back side, and the first SPAD has a first electrical contact near the front side of the substrate, the method comprising: etching a front trench between the first SPAD and the second SPAD; forming a continuous passivation layer in the front trench; opening the continuous passivation layer at a horizontal surface of the front trench; and forming a conductive material in the front trench, wherein the conductive material is electrically coupled to the substrate through the opening of the passivation layer to form a second electrical contact.

[0010] These and other examples are described in more detail below. Attached Figure Description

[0011] Figure 1 This is a circuit diagram illustrating an exemplary SPAD device according to an implementation scheme.

[0012] Figure 2 This is an illustrative back-illuminated (BSI) side cross-sectional view of a SPAD-based semiconductor device.

[0013] Figures 3A to 3E The diagram shows cross-sectional views of various manufacturing stages of an exemplary SPAD-based semiconductor device with an isolation trench structure according to an embodiment, the isolation trench structure having a conductive material located between annular trenches and electrically coupled to a substrate at the bottom of the trench structure.

[0014] Figures 4A to 4E These are cross-sectional views of various manufacturing stages of an exemplary SPAD-based semiconductor device with an isolation trench structure according to an implementation scheme, the isolation trench structure having a front trench and a back trench.

[0015] Figure 5A This is a top view of an exemplary SPAD-based semiconductor device according to an embodiment, showing the relative horizontal arrangement of components with a front trench and a segmented back trench isolation trench structure.

[0016] Figures 5B to 5C It is based on the implementation plan. Figure 5A Cross-sectional views of various locations in a SPAD-based semiconductor device.

[0017] Figures 6A to 6E The diagram shows cross-sectional views of various manufacturing stages of an exemplary SPAD-based semiconductor device having a first stepped isolation trench structure according to an embodiment, the first stepped isolation trench structure including conductive material in contact with the substrate through an opening in the passivation layer at the stepped region.

[0018] Figures 7A to 7EThis is a cross-sectional view of various manufacturing stages of an exemplary SPAD-based semiconductor device having a second stepped isolation trench structure according to an embodiment, the second stepped isolation trench structure including conductive material in contact with the substrate through an opening in the passivation layer at the stepped region.

[0019] Figures 8A to 8E The diagram shows cross-sectional views of various manufacturing stages of an exemplary SPAD-based semiconductor device with a third-step isolation trench structure according to an embodiment, the third-step isolation trench structure including conductive material in contact with the substrate through an opening in the passivation layer at the step region.

[0020] Figures 9A to 9E The images are cross-sectional views of various manufacturing stages of an exemplary SPAD-based semiconductor device with a fourth-step isolation trench structure according to an embodiment, the fourth-step isolation trench structure including conductive material in contact with the substrate through an opening in the passivation layer at the step region.

[0021] Figure 10A This is a top view showing the relatively horizontal arrangement of components of an exemplary SPAD-based semiconductor device according to an embodiment, the SPAD-based semiconductor device having a third-step isolation trench structure substantially located at the corner of the SPAD pixel.

[0022] Figures 10B to 10D It is based on the implementation plan. Figure 10A Cross-sectional views of various locations in a SPAD-based semiconductor device.

[0023] Figure 11A This is a top view showing the components of an exemplary SPAD-based semiconductor device with an isolation trench structure according to an embodiment, arranged in a relatively horizontal manner. The isolation trench structure has a front trench and a segmented back trench, as well as contacts that are substantially in contact with the substrate at the corners of the SPAD pixels.

[0024] Figures 11B to 11C It is based on the implementation plan. Figure 11A Cross-sectional views of various locations in a SPAD-based semiconductor device.

[0025] Figure 12A This is a top view showing the components of an exemplary SPAD-based semiconductor device with another isolation trench structure according to an embodiment, arranged in a relatively horizontal manner. This other isolation trench structure has a front trench and a segmented back trench, as well as contacts that are substantially in contact with the substrate at the corners of the SPAD pixels.

[0026] Figures 12B to 12C It is based on the implementation plan. Figure 12A Cross-sectional views of various locations in a SPAD-based semiconductor device.

[0027] Figures 13A to 13D These are cross-sectional views of various manufacturing stages of an exemplary SPAD-based semiconductor device with an isolation trench structure according to an embodiment, the isolation trench structure including a conductive material in contact with the substrate through an opening in a passivation layer near the front side of the substrate.

[0028] Figures 14A to 14D The diagram shows cross-sectional views of various manufacturing stages of an exemplary SPAD-based semiconductor device with an isolation trench structure according to an embodiment, the isolation trench structure being partially filled with a passivation layer and including a conductive material in contact with the substrate on the front side near the substrate.

[0029] Figures 15A to 15E The diagram shows cross-sectional views of various manufacturing stages of an exemplary SPAD-based semiconductor device with an isolation trench structure according to an embodiment. The isolation trench structure is filled with a first conductive material and has a second conductive material in contact with the substrate at an opening in a passivation layer near the front side of the substrate.

[0030] Figures 16A to 16D An exemplary geometric arrangement of a representative isolation trench structure according to an implementation scheme is shown. Detailed Implementation

[0031] The following detailed description is intended to provide several examples illustrating the broader concepts set forth herein, but is not intended to limit the invention or its application and use. Furthermore, one is not expected to be bound by any theory presented in the foregoing background or the following detailed description.

[0032] According to various embodiments, trench isolation structures may be located between adjacent pixels of an imaging device. The trench isolation structure may include embedded contacts, either anodes or cathodes, for photodetector diodes of one or more adjacent pixels. Embedded contacts may be referred to as recessed contacts. In some embodiments, the other of the anode or cathode may be located close to or on the front side of the substrate and substantially centered within the pixel. In some embodiments, the photodetector diode may be a SPAD.

[0033] Some embodiments may include stepped isolation trenches with contacts in a stepped area. Some embodiments may include front trenches and back trenches, and the back trench may be segmented and / or overlap with itself. Some embodiments may include trenches lined with a continuous passivation layer, wherein openings in the continuous passivation layer allow conductive material filling the trench to contact a substrate to form embedded contacts.

[0034] Advantageously, the apparatus and method according to this specification increase the distance between the anode and cathode of each SPAD, thereby reducing the risk of edge breakdown in the avalanche region of the corresponding SPAD. The apparatus and method according to this specification provide smaller pixel pitch and critical dimensions, thereby improving imager resolution and light detection performance, while still isolating adjacent pixels and preventing crosstalk and other undesirable behaviors.

[0035] Figure 1 An exemplary SPAD-based imager 100 is illustrated, and is also referred to herein as a SPAD imager 100. The SPAD imager 100 can be used in any number of exemplary systems. The SPAD imager 100 can be a sensor device having one or more single-photon avalanche diode (SPAD) devices 102 for detecting incident photons. In some embodiments, the SPAD imager 100 can be a silicon photomultiplier tube (SiPM) device having multiple SPAD devices 102. SPAD 104 may include a semiconductor diode and can be configured to receive incident photons. In some embodiments, the SPAD-based imager 100 may include one or more microlenses to further guide light into one or more SPADs 104 of the SPAD-based imager 100.

[0036] In some implementations, the system using SPAD imager 100 may include a LiDAR imaging system. The LiDAR imaging system may be a vehicle-mounted LiDAR system, for example, for navigation, obstacle avoidance, ranging, or other safety functions. The LiDAR system may also be, alternatively, a surveillance system, a machine vision system, a survey system, another ranging system, or any other suitable system.

[0037] The SPAD imager 100 may be included in other suitable systems and is not limited to the exemplary embodiments described herein. For example, the SPAD imager 100 may be included in other systems that use light (e.g., visible light, near-infrared (near-IR) light, infrared (IR) light, etc.) to determine information about the environment in which the device is located.

[0038] An exemplary SPAD device 102 includes a SPAD 104 having a cathode and an anode, respectively biased by power supply voltage terminals 108 and 110. During operation of the SPAD device 102, voltage terminals 108 and 110 can reverse bias the SPAD 104 to a voltage higher than its breakdown voltage. When reverse biased above the breakdown voltage, the absorption of a single photon by the SPAD 104 can induce a large avalanche current in the SPAD 104 due to impact ionization.

[0039] The avalanche process in SPAD 104 can, and in some cases will, continue indefinitely. While the avalanche current continues, subsequent photons incident on SPAD 104 cannot be detected. In some embodiments, a quenching circuit 106, which may include passive or active quenching, is used to stop the avalanche process. The quenching circuit 106 can be used to reduce the bias voltage of SPAD 104 below the breakdown level. In some embodiments, the passive quenching circuit 106 may include a resistor connected in series between the cathode of SPAD 104 and the positive bias voltage terminal 108, such as... Figure 1 As shown in the diagram. The SPAD 104, which is coupled in series with the quenching resistor or other quenching circuit 106, may be referred to as a microcell.

[0040] Avalanche currents can generate electrical signals that can be detected by readout circuitry 112. For example, an avalanche current induced by the detection of an incident photon by a microcell and the subsequent quenching of the avalanche current can generate a pulsed current signal, which readout circuitry 112 can identify as photon detection. This pulsed current signal may be referred to herein as an avalanche pulse.

[0041] The readout circuit 112 can process the detection of current signals for various purposes, such as counting the number of incident photons by counting the number of avalanche current pulses using analog or digital pulse counting circuits, and timing the laser time-of-flight (ToF) to determine the distance to the target. The readout circuit 112, coupled to the node between SPAD 104 and quenching circuit 106, in... Figure 1 The examples shown are merely illustrative. The readout circuitry 112 can be coupled to any suitable portion of the SPAD device 102. In some embodiments, the quench circuitry 106 may be integrated with the readout circuitry 112.

[0042] For each induced avalanche current, SPAD 104 must be quenched and reset. During the time required for quenching and resetting SPAD 104 (called the stall time), SPAD 104 cannot detect additional photons. Therefore, the stall time limits the number of photons that can be detected by SPAD 104 within a given time period. In some embodiments, the stall time of SPAD 104 can be on the order of nanoseconds, for example, approximately 3 nanoseconds.

[0043] SPAD 104 also has the potential to avoid generating an avalanche current in response to incident photons. Therefore, SPAD 104 has a photon detection efficiency (PDE), which is the result of several factors, including the probability of generating carriers (electrons and / or holes) when SPAD 104 receives incident photons, and the probability that the generated carriers will trigger an avalanche current. For example, SPAD 104 can have a PDE of approximately 30%, meaning that SPAD device 102 will detect approximately 30% of incident photons.

[0044] SPAD imager 100 (which may also be referred to herein as SPAD-based semiconductor device 100) may include a plurality of SPAD devices 102 to increase the photon detection capability of the SPAD imager. In some embodiments, the plurality of SPAD devices 102 may be coupled in parallel (not shown) between power supply voltage terminals 108 and 110 and may share a common readout circuitry 112. In some embodiments, each of the plurality of SPAD devices 102 may have a separate readout circuitry 112. In some embodiments, the SPAD devices 102 may be arranged as a one-dimensional or two-dimensional array, and the array may include tens, hundreds, thousands, tens of thousands (or more) of SPAD pixels.

[0045] Figure 2 This is a cross-sectional side view of an exemplary SPAD-based semiconductor device 100 having a plurality of SPAD devices arranged in an array, wherein each SPAD is separated by an isolation structure. The SPAD imager 100 includes SPAD 104-1, which is adjacent to other SPADs of the imager, such as adjacent SPADs 104-2 and SPAD 104-3. Each SPAD may be part of a corresponding SPAD device 102, microcell, SPAD pixel 260, etc. Figure 2 The SPAD imager 100 shown is a back-illuminated device (e.g., an image sensor) in which incident light passes through the rear surface (BS) of the substrate 254. Embodiments of this disclosure may be suitably adapted to front-illuminated devices (e.g., image sensors).

[0046] Substrate 254 has a rear surface 256 and a front surface (FS) 258. In some embodiments, such as in a back-side imaging configuration, FS 258 may be adjacent to wiring layer 206. Wiring layer 206 may include one or more metallization layers having conductive signal lines 212, 214, for example, formed of metal, embedded in one or more dielectric layers 208, 210. The dielectric layers may be formed of any desired material, such as silicon dioxide, silicon nitride, organic or inorganic materials, etc. Different layers of conductive signal lines 212, 214 may be coupled using conductive vias 216 through one or more dielectric layers 208, 210.

[0047] In some embodiments, at least some of the wiring layers 206 may be included in a separate substrate, which is directly or indirectly attached to substrate 254 during manufacturing. In some embodiments, substrate 254 and one or more layers of wiring layers 206 may be wafer-bonded to the separate substrate. In some embodiments, the separate substrate may also include readout circuitry 112 and / or other desired circuitry and structures.

[0048] SPAD 104-1 may be formed in a substrate 254 extending between BS256 and FS258. The substrate may include a semiconductor substrate formed of a material such as silicon. The substrate may have any suitable depth D1 measured between BS256 and FS258. In some embodiments, the depth D1 may be between 1 μm and 12 μm, for example between 2 μm and 9 μm, such as 3 μm or 6 μm. The SPAD pixel may have any suitable width, which may also be referred to herein as pixel pitch. In some embodiments, the pixel pitch may be between 1 μm and 20 μm, between 1 μm and 10 μm, between 1 μm and 6 μm, for example 2 μm, 3 μm, or 6 μm.

[0049] The SPAD pixel 260 of the SPAD imager 100 may include SPAD 104-1. SPAD pixel 260 may include a portion of substrate 254 in which SPAD 104-1 is located, such as the portion of substrate 254 between FS258 and BS256 and surrounded by isolation structure 252. SPAD pixel 260 may include other components and connections of the SPAD device 102, such as quenching circuit 106 (not shown). SPAD pixel 260 may include other similarly positioned and associated structures, such as corresponding doped regions 202, 204, corresponding portions of wiring layer 206, and / or other features formed within the corresponding isolation structure 252 and within the substrate between FS258 and BS256.

[0050] In some embodiments, substrate 254 may be formed of a p-type doped semiconductor layer (e.g., p-type doped epitaxial silicon). SPAD 104-1 may be formed of a p-type doped semiconductor layer, a p-type doped enrichment layer 202, and an n-type doped region 204. The n-type doped region 204 may serve as the cathode of SPAD 104-1. The cathode and anode (not shown) of each SPAD pixel 260 may be coupled to corresponding portions of wiring layer 206 via conductive via 216. The doping types of the p-type and n-type regions described herein may be reversed if desired.

[0051] One or more microlenses 286 may be formed on SPADs 104-1, 104-2, and 104-3. The microlenses 286 can focus light toward the respective SPADs 104-1, 104-2, and 104-3. A planarization layer 282 may optionally be formed between the microlenses 286 and the BS256 of the substrate 254. The planarization layer 282 may be formed of any suitable material or combination of materials, such as one or more oxide layers, such as silicon dioxide, silicon nitride, etc.

[0052] Still referencing Figure 2SPAD 104-1 can be isolated from neighboring SPADs via isolation structure 252 in substrate 254. Neighboring SPADs 104-1, 104-2, and 104-3 may also be referred to herein as adjacent SPADs, and neighboring pixels 260 may also be referred to herein as adjacent pixels. To mitigate crosstalk and / or achieve other performance objectives, isolation structure 252 may be formed partially or completely around each SPAD 104-1, 104-2, and 104-3. For example, isolation structure 252 may be formed along one or more sides of each SPAD pixel 260. One side of SPAD pixel 260 may include a substantially linear region between the first SPAD 104-1 and the second neighboring SPAD 104-2. The corners of SPAD pixel 260 may include regions that make at least three SPAD pixels 260 adjacent.

[0053] The isolation structure 252 may include a trench structure formed by FS258 and / or BS256. A trench formed by FS258 may be referred to herein as an FS trench, and a trench formed by BS256 may be referred to herein as a BS trench. In some embodiments, the isolation structure 252 may include a deep trench isolation structure that extends partially or completely through the substrate 254.

[0054] The isolation structure 252 may be filled with different materials that perform various desired functions. The isolation structure 252 may include a light-absorbing material filler that absorbs photons and prevents photons generated, for example by avalanches, from being transmitted to adjacent micro-units and causing crosstalk. In some embodiments, the light-absorbing material includes a metal, such as tungsten.

[0055] The isolation structure 252 may include a conductive material (such as metal, polysilicon, and / or the like) to provide a conductive path to one or more SPADs, as described in more detail below. In some embodiments, the conductive material may include tungsten, polysilicon, and / or the like. In some embodiments, the conductive material may include multiple conductive materials, such as tungsten facing FS258 and polysilicon facing BS256. For another example, approximately the top third of the isolation structure 252 near FS258 may include tungsten and the remaining approximately two-thirds of the isolation structure 252 may include polysilicon.

[0056] The isolation structure may include a low-refractive-index material that causes total internal reflection. The low-refractive-index material reflects photons, thereby confining them within the active region of the SPAD 104-1 to improve efficiency. In some embodiments, the low-refractive-index material may include silicon dioxide or the like.

[0057] The isolation structure 252 may include a high-k material, for example, formed in trenches in the substrate 254, to mitigate dark current. In some embodiments, the high-k material may include an oxide coating, such as aluminum oxide, hafnium oxide, tantalum oxide, and / or the like. The isolation structure 252 may include a passivation layer that performs various desired functions, such as mitigating dark current, isolating the conductive material filler from the substrate 254, reflecting photons, etc. The passivation layer may include any suitable material, such as oxides such as high-k materials, silicon dioxide, silicon nitride, other dielectrics, and / or the like.

[0058] In some embodiments, the portion of the isolation structure 252 closer to FS258 may include a light-absorbing material, such as a metallic filler. The cathode and / or anode contacts of SPAD 104-1 may be adjacent to the front surface 258, and the initiation point of photon emission (e.g., due to avalanche) may be primarily adjacent to FS258. The portion of the isolation structure 252 adjacent to FS258 may receive the emitted photons at an orthogonal angle or approximately an orthogonal angle. The light-absorbing material may be suitably positioned toward FS258 within the isolation structure 252 to block most or all of the emitted photons and prevent crosstalk.

[0059] In some implementations, the portion of the isolation structure 252 away from FS258 may include a low-refractive-index material. The portion of the isolation structure 252 away from FS258 may receive photons emitted at a higher incident angle, and the low-refractive-index material may reflect light as discussed above, thereby preventing light from propagating to adjacent SPADs 104-2, 104-3.

[0060] The embodiments of the isolation trench structure 252 described herein increase the distance between the first SPAD contact and the second SPAD contact, i.e., the distance between the anode and cathode of SPAD 104-1. Some embodiments of the isolation trench structure 252 described herein typically include a first SPAD contact (whether anode or cathode) and a second SPAD contact (the other of the anode or cathode), the first SPAD contact being part of the trench isolation structure 252, the second SPAD contact being located at or near FS258 and substantially centered within the SPAD pixel 260. In several embodiments, the first SPAD contact is substantially contained within the boundary of the isolation trench 252 within the substrate. For example, the first SPAD contact may not extend beyond the boundary of the lateral isolation trench 252.

[0061] Therefore, compared to positioning the first SPAD contact within a bulk substrate 254 between the isolation structures 252, the first SPAD contact is positioned further horizontally (laterally) from the second contact. Some embodiments of the isolation trench structure 252 described herein position the first SPAD contact vertically away from FS258, i.e., partially or completely reaching BS256. Increasing the horizontal and / or vertical distance between the anode and cathode reduces the strength of the electric field and reduces the risk of edge breakdown of the SPAD 104-1. SPAD contacts located substantially within the isolation trench 252 of the substrate may be referred to herein as embedded contacts.

[0062] An embodiment of the isolation trench structure 252 (which may be referred to herein as trench 252, trench structure 252, or isolation structure 252) may include a trench 252 surrounding each SPAD pixel 260. While the embodiments described below discuss the anode contacts of the SPAD as being located within the trench 252 (first SPAD contacts), it will be appreciated that the cathode may alternatively be located within the trench 252.

[0063] First subset of exemplary implementations

[0064] Next, a first subset of embodiments forming the improved trench isolation structure 252 will be described. This first subset of embodiments includes an FS trench lined with a passivation layer and filled with a conductive material, wherein the passivation layer at the bottom of the FS trench (the portion of the trench facing BS256) is open to allow conductive coupling between the conductive material and the substrate 254. The bottom of the FS trench may not be lined with a passivation layer.

[0065] refer to Figures 3A to 3E A first subset of trench isolation implementations may include some first exemplary implementations having a conductive material located between annular trenches and electrically coupled to a substrate 254 at the bottom of trench structure 252.

[0066] refer to Figure 3A The FS surface 258 of substrate 254 can be patterned with photoresist to prepare for etching annular trenches. For clarity, photoresist and photoresist processes are not shown in any of the accompanying figures, but this should be understood. References Figure 3B One or more annular trenches 310 can be etched through the substrate. Each annular trench 310 may partially or completely surround the corresponding SPAD pixel 260.

[0067] The annular trench 310 can be etched to any suitable distance through the substrate 254, such as greater than half, half, or less than half of the substrate 254. In some embodiments, the photoresist can be stripped after etching the annular trench 310.

[0068] refer to Figure 3C The passivation layer 320 can be deposited in the etched annular trench 310. The passivation layer 320 can be a conformal passivation layer. The substrate 254 can be patterned using a photoresist suitable for etching the central portion 330 of the substrate 254 between adjacent passivation layers 320.

[0069] refer to Figure 3D The central portion 330 can then be etched to any suitable distance through the substrate 254 to form a central trench 340. In some embodiments, the central portion 330 may be etched to the same depth as the annular trench 310, or to a shallower depth (e.g., as shown in the image). Figure 3D (as shown in the diagram) or a depth greater than the annular trench 310. In some embodiments, the photoresist may be stripped after the central portion 330 has been etched.

[0070] In some embodiments, a portion 345 of the substrate at the bottom of the central trench 340 may be doped (e.g., by charged ion implantation) to promote conductive coupling with the conductive material to be deposited in the central trench 340. In some embodiments, ion implantation may be used, such as implantation of single-charged positive ions, double-charged positive ions, etc. For example, the substrate 254 may be appropriately patterned and positive ion implantation performed, after which the photoresist may be stripped. The ion implantation may then be activated, for example, by annealing at a suitable temperature for a suitable amount of time (not shown).

[0071] refer to Figure 3E Conductive material 350 may be deposited in the central trench 340. In some embodiments, conductive material 350 may also be deposited on the FS surface 258 of substrate 254, and the substrate may then be patterned and etched as part of wiring layer 206 (not shown). Conductive material 350 may be coupled to appropriate circuitry of SPAD imager 100 via one or more conductive signal lines 212, 214 to form first contacts for one or more adjacent SPADs 104-1, 104-2. Conductive material 350 may, for example, comprise tungsten.

[0072] In some embodiments, substrate 254 may include an etch stop point 360 near BS256. After processing from FS258, FS258 can be attached to a carrier wafer to allow subsequent processing from BS256. The substrate can be etched down to the etch stop point 360, for example, to obtain a desired substrate depth D1. In some embodiments, the substrate can be thinned from BS256 to approximately 6 μm for detecting IR or near-IR photons. Various structures, such as one or more BS trenches, can then be formed from the back side.

[0073] Any of the embodiments taught herein may include an etch stop point 360 and back-side processing, even though no specific embodiment is described. Therefore, in some embodiments, some structures shown and described herein may have a small portion of the structure near BS256 removed during subsequent etching.

[0074] refer to Figures 4A to 4E A first subset of trench isolation implementations may include some second exemplary implementations having a trench structure 252 that may extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 may include an FS trench structure 400 and a BS trench structure 405.

[0075] refer to Figure 4A The FS trench 400 can be formed by patterning the FS surface 258 of the substrate 254 with a photoresist to prepare for etching a wide trench. The wide trench 410 can then be etched through the substrate 254. The wide trench 410 can be etched to any suitable distance through the substrate 254, such as greater than half, half, or less than half of the substrate 254. In some embodiments, the photoresist can be stripped after etching the wide trench 410.

[0076] refer to Figure 4B The passivation layer 420 can be deposited in the wide trench 410. The passivation layer 420 can be a conformal passivation layer. (Reference) Figure 4C The substrate 254 can be patterned with a photoresist suitable for etching the narrow trench 440 through the wide trench 410. The narrow trench 440 can then be etched to any suitable distance through the substrate 254, for example, leaving at least some of the passivation layer 420 on the sidewalls of the wide trench 410. In some embodiments, the narrow trench 440 can be etched to a depth greater than that of the wide trench 410.

[0077] In some embodiments, a portion 445 of the substrate at the bottom of the narrow trench 440 may be doped (e.g., by charged ion implantation) to promote conductive coupling with the conductive material to be deposited in the narrow trench 440. In some embodiments, ion implantation may be used, such as implantation of single-charged positive ions, double-charged positive ions, etc. In some embodiments, the same photoresist used for etching the narrow trench 440 may be used for ion implantation because it is self-aligned and / or because it allows for low-energy implantation with shallow depths. In other embodiments, the substrate 254 may be individually patterned for ion implantation. One or more photoresists may be suitably stripped, and then ion implantation may be activated as described above.

[0078] refer to Figure 4DConductive material 450 may be deposited in narrow trench 440. In some embodiments, conductive material 450 may also be deposited on the FS surface 258 (not shown) of substrate 254, and the substrate may then be patterned and etched as part of wiring layer 206 (not shown). Conductive material 450 may be coupled to appropriate circuitry of SPAD imager 100 via one or more conductive signal lines 212, 214 to form first contacts for one or more adjacent SPADs 104-1, 104-2. Conductive material 450 may, for example, comprise tungsten.

[0079] refer to Figure 4E BS trenches 405, such as partial BS deep trenches, can be formed from the BS surface 256. The trench structure 252 may include both BS trenches 405 and FS trenches 400.

[0080] In some embodiments, the BS trench 405 may include a passivation layer. In some embodiments, the BS trench 405 may be lined with a high-k dielectric 470 and filled with a passivation layer 460, such as silicon dioxide. In some embodiments, the BS trench 405 does not contact the FS trench 400 structure (such as the passivation layer 420 and the conductive material 450) and may leave a conductive path between the conductive material 450 and one or more adjacent SPADs 104-1, 104-2.

[0081] The BS trench 405 may be formed adjacent to the pyramidal light scattering structure 480 for adjacent SPADs 104-1, 104-2. The light scattering structure 480 may be configured to increase the path length of photons in order to detect longer wavelengths of light, such as IR or near IR. In some embodiments, the BS trench 405 may be included to prevent light leakage from one pixel 260 to another due to scattering from the light scattering structure 480, due to photons generated during avalanche of the respective SPAD pixel 260 (which may be referred to as crosstalk), and for other desired purposes.

[0082] refer to Figures 5A to 5C A first subset of trench isolation implementations may include some third exemplary implementations having a trench structure 252 that may extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 may include an FS trench structure 500 and a BS trench structure 505. In some implementations, the trench structure 252 (e.g., the BS trench structure 505) may include multiple individual segments of a BS trench that overlap to provide different conductive paths to SPADs 104-1, 104-2, 104-3, 104-4 and to block light from both. The BS trench 505 may be a deep trench and may be connected to the FS trench 500.

[0083] Figure 5A The relative horizontal arrangement of the various components of the trench structure 252 is shown representatively, without regard to the vertical position of such a structure. Figure 5B and Figure 5C The relative vertical arrangement of the various components of the trench structure is shown.

[0084] refer to Figure 5A The arrays of SPADs 104-1, 104-2, 104-3, and 104-4 may include a conductive material 550 surrounding pixels 260 in an FS trench 500 lined with a passivation layer 560, and the array may include segmented BS trenches 505 comprising a high-k material 570 and / or a passivation layer 560. For example, it may be used with respect to... Figures 4A to 4E The FS trench 500 is formed using a similar or identical method as described in the FS trench 400 shown.

[0085] refer to Figure 5B , it is like Figure 5A Referring to the first cross-section, the first portion of the segmented BS trench 505 may include a passivation layer 560 and / or a high-k material 570, which contacts or otherwise connects to the bottom of the FS trench 500 on one side of the trench structure 252. The BS trench 505 may be specifically connected to the passivation layer 520 of the FS trench 500 on the same side of the trench structure 252. For example... Figure 5B The portion of the BS trench 505 shown, which includes only one side of the passivation layer 560 and / or the high-k material 570, can be referred to as a single-sided segmented BS trench.

[0086] like Figure 5A As shown, in some embodiments, the single-sided segmented BS trench may intersect the conductive material 550 of the FS trench 500 in the horizontal direction, such that the passivation layer 560 and / or high-k material 570 of the single-sided segmented BS trench are adjacent to two SPADs (e.g., SPADs 104-1 and 104-2). In some alternative embodiments, the passivation layer 560 and / or high-k material 570 of the single-sided segmented BS trench may remain adjacent to a single SPAD and may not intersect with the conductive material 550 of the FS trench 500. Either arrangement may provide overlapping single-sided BS trenches 505.

[0087] A conductive path is maintained between the conductive material 550 and the SPAD 104-2 on opposite sides of the trench structure 252, but no conductive path is provided between the conductive material 550 and another adjacent SPAD 104-1. Each SPAD 104-1, 104-2, 104-3, 104-4 may have a conductive path between the corresponding SPAD at the corresponding first portion of the conductive material 550 and the BS trench 505. The conductive material 550 may, for example, comprise tungsten.

[0088] refer to Figure 5C , it is like Figure 5A Referring to the second cross-section, the second portion of the segmented BS trench 505 may include a passivation layer 560 and / or a high-k material 570, which contacts or otherwise connects to the bottom of the FS trench 500 on both sides of the trench structure 252. The BS trench 505 may be specifically connected to the passivation layer 520 of the FS trench 500 on both sides of the trench structure 252. In some embodiments, the second portion of the BS trench 505 may include two back-side deep trenches coated with a high-k material and filled with oxide, wherein each back-side deep trench is connected to a corresponding passivation layer 520 of the FS trench 500 and leaves a substrate 254 between the two back-side deep trenches.

[0089] The second portion of the segmented BS trench 505 blocks direct lateral conductive paths to each adjacent SPAD 104-3, 104-4. The second portion of the segmented BS trench 505 (which may be formed by partially overlapping multiple first portions of the BS trench 505) can be used to prevent some or all of the light leakage between adjacent pixels 260.

[0090] In some embodiments, the BS trench 505 may include a passivation layer 560. In some embodiments, the BS trench 505 may be lined with a high-k dielectric 570 and filled with a passivation layer 560, such as silicon dioxide. The BS trench 505 may be formed adjacent to a pyramidal light scattering structure 480 for adjacent SPADs 104-1, 104-2, 104-3, 104-4, as described with respect to other embodiments above. In some embodiments, the substrate 254 may include an etch stop point 360 as described above. The BS trench 505 may be suitably adapted to other exemplary embodiments described herein.

[0091] Second subset of exemplary implementations

[0092] Next, a second subset of embodiments forming the improved trench isolation structure 252 will be described. This second subset of embodiments includes a multi-width FS trench lined with a passivation layer having an opening at the transition between a first width and a second width of the FS trench. This opening allows the conductive material filler in the trench structure 252 to be electrically coupled to the substrate 254 and to form a first contact of the SPAD 104-1. In some embodiments, the bottom of the FS trench may not be lined with a passivation layer to allow the conductive filler material to be second conductively coupled to the substrate 254.

[0093] The openings in the passivation layer at the transition between the first and second widths of the FS trench can be openings within an otherwise continuous passivation layer, for example, formed in the same deposition step rather than in separate deposition steps to form a passivation layer individually for each width. Therefore, the substrate 254 can be exposed to conductive filler material in the stepped regions of the stepped trench. A multi-width FS trench can be referred to as a stepped trench, and the transition region between the first and second widths of the FS trench can be referred to as a stepped region.

[0094] More generally, the horizontal surface or region of the trench structure 252 may include a surface or portion of the trench structure 252 located between two vertical walls of the trench structure, wherein the vertical walls extend substantially perpendicular to FS 258 and / or BS 256. In some embodiments, the horizontal surface or region is defined by one or more etching steps, and therefore the resulting horizontal region or surface may or may not be substantially flat and perpendicular to the vertical walls, depending on the specific process used. In some embodiments, the bottom of the FS trench or BS trench may be the horizontal surface or region of the trench structure 252. In some embodiments, the transition region may include a horizontal surface or region located between the vertical walls of the wide trench and the narrow trench.

[0095] refer to Figures 6A to 6E A second subset of the trench isolation implementations may include some fourth exemplary implementations having a trench structure 252 that may extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 may include a stepped FS trench having a wide trench 600 and a narrow trench 605 lined with a passivation layer, wherein the passivation layer opens at a transition region to allow electrical coupling of the conductive material filler to the substrate 254.

[0096] refer to Figure 6A The wide FS trench 600 can be formed by patterning the FS surface 258 of the substrate 254 with a photoresist to prepare for etching the wide trench. The wide trench 600 can then be etched through the substrate 254. The wide trench 600 can be etched to any suitable distance through the substrate 254, such as greater than half, half, or less than half of the substrate 254. In some embodiments, the photoresist can be stripped after etching the wide trench 600.

[0097] In some embodiments, a portion 610 of the substrate at the bottom of the wide trench 600 may be doped (e.g., by charged ion implantation) to promote conductive coupling with the conductive material to be deposited in the trench 252. In some embodiments, ion implantation may be used as described above. In some embodiments, the same photoresist used to etch the wide trench 600 may be used for ion implantation prior to stripping the photoresist, because it is self-aligned and / or because it allows for low-energy implantation with shallow depths. In other embodiments, the substrate 254 may be patterned separately for ion implantation, e.g., allowing ion implantation only in the wide trench 600. One or more photoresists may be stripped appropriately, and then ion implantation may be activated as described above.

[0098] refer to Figure 6B The narrow trench 605 can be etched through the wide trench 600. Appropriate patterning of the photoresist can be applied, and the narrow trench 605 can then be etched through the substrate 254. The narrow trench 605 can be etched to any suitable distance through the substrate 254. In some embodiments, the narrow trench 605 can be etched to a depth equal to one to five times the depth of the wide trench 600, for example, two to four times the depth of the wide trench 600. In some embodiments, the narrow trench 605 is formed to a depth approximately twice that of the wide trench 600. In some embodiments, the photoresist can be stripped after etching the narrow trench 605.

[0099] refer to Figure 6C The passivation layer 620 can be deposited in both the wide trench 600 and the narrow trench 605. The passivation layer 620 can be a continuous and discontinuous conformal passivation layer, such as being formed simultaneously or in a single deposition. (Reference) Figure 6D Then, the continuous passivation layer 620 can be opened at the transition between the narrow trench 605 and the wide trench 600.

[0100] In some embodiments, the passivation layer 620 may be etched away at the transition region. For example, spacer etching may be performed to remove some or all of the passivation layer 620 from the surface of the horizontal trench. In some embodiments, the passivation layer may be removed from the bottom of the narrow trench 605. In some such embodiments, the portion of the substrate 254 exposed at the bottom of the narrow trench 605 may then be doped, for example, using ion implantation as described above.

[0101] refer to Figure 6E Conductive material 630 may be deposited in wide trench 600 and narrow trench 605. Conductive material 630 may be in electrical contact with substrate 254 in the transition region between narrow trench 605 and wide trench 600, and in some embodiments also extends through the bottom of narrow trench 605. Conductive material 630 may, for example, comprise tungsten.

[0102] In some embodiments, conductive material 630 may also be deposited on the FS surface 258 of substrate 254 (not shown), and the substrate may then be patterned and etched as part of wiring layer 206 (not shown). The conductive material 630 may be coupled to appropriate circuitry of SPAD imager 100 via one or more conductive signal lines 212, 214 to form first contacts for one or more adjacent SPADs 104-1, 104-2, for example at stepped areas on one or both sides of isolation trench 252, and in some cases also through the bottom of narrow trench 605.

[0103] An embodiment of the fourth exemplary embodiment having electrical contact between the conductive material 630 and the substrate 254 at the bottom of the narrow trench is also an example of an embodiment of the first subset of trench isolation embodiments.

[0104] In some embodiments, substrate 254 may include an etch stop point 360 near BS256. After processing from FS258, FS258 may be attached to a carrier wafer to allow subsequent processing from BS256. The substrate may be etched back-side down to etch stop point 360. In some embodiments, the substrate is etched back-side down to narrow trench 605, and in some embodiments, the back-side etching stops before reaching narrow trench 605.

[0105] refer to Figures 7A to 7E A second subset of the trench isolation implementations may include some fifth exemplary embodiments having a trench structure 252 that may extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 may include a stepped FS trench having a wide trench 600 and a narrow trench 605 lined with a passivation layer, wherein the passivation layer opens at a transition region to allow electrical coupling between the conductive material filler and the substrate 254. The trench structure 252 according to the fifth exemplary embodiment may be an alternative embodiment of the fourth exemplary embodiment, having multiple conductive materials within the trench structure 252.

[0106] refer to Figure 7A As described with respect to the fourth exemplary embodiment, a wide trench 600 may be formed in the substrate 254, its bottom portion 610 may be doped as described above, and a narrow trench 605 may then be formed at the bottom of the wide trench 600.

[0107] refer to Figure 7B and Figure 7CAs described with respect to the fourth exemplary embodiment, a passivation layer with openings may be formed at the transition region. For example, passivation layer 620 may be deposited in both wide trench 600 and narrow trench 605. Passivation layer 620 may be a conformal passivation layer formed in a single deposition. In some embodiments, continuous passivation layer 620 may be etched away at the transition region. For example, spacer etching may be performed to remove some or all of the passivation layer 620 from the surface of the horizontal trench, such as removing enough passivation layer to allow contact with the conductive filler material.

[0108] In some embodiments, the passivation layer may be removed from the bottom of the narrow trench 605, for example by etching with spacers. In some such embodiments, the portion of the substrate 254 exposed at the bottom of the narrow trench 605 may then be doped, for example by ion implantation as described above.

[0109] refer to Figure 7D A first conductive material 730 may be deposited in both the wide trench 600 and the narrow trench 605. The first conductive material 730 may be in electrical contact with the substrate 254 in the transition region between the narrow trench 605 and the wide trench 600, and in some embodiments, it may also extend through the bottom of the narrow trench 605. The first conductive material 730 may comprise polysilicon. In some embodiments, for example, in the same process step, polysilicon may be used to fill the narrow trench 605 and to coat the wide trench 600. The polysilicon may not completely fill the wide trench 600, for example, leaving a cavity 750 within the polysilicon.

[0110] refer to Figure 7E The second conductive material 740 may be deposited within the first conductive material 730 within the wide trench 600 (e.g., within the cavity 750). In some embodiments, the first conductive material 730 may be etched or otherwise treated to modify the shape of the cavity 750. The second conductive material 740 may, for example, comprise tungsten.

[0111] In some embodiments, a second conductive material 740 may also be deposited on the FS surface 258 (not shown) of the substrate 254, and the substrate may then be patterned and etched as part of the wiring layer 206 (not shown). The second conductive material 740 may be coupled to appropriate circuitry of the SPAD imager 100 via one or more conductive signal lines 212, 214 to combine with the first conductive material 730 to form first contacts for one or more adjacent SPADs 104-1, 104-2. For example, the first contacts may be located in a stepped area on one or both sides of the isolation trench 252, and in some cases also through the bottom of the narrow trench 605.

[0112] The fifth exemplary embodiment, which has electrical contact between the conductive material 730 and the substrate 254 at the bottom of the narrow trench, is also an example of an embodiment of the first subset of trench isolation embodiments.

[0113] refer to Figures 8A to 8E A second subset of the trench isolation implementations may include some sixth exemplary embodiments having a trench structure 252 that may extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 may include a stepped FS trench having a wide trench 600 and a narrow trench 605 lined with a passivation layer, wherein the passivation layer is open at a transition region to allow electrical coupling between the conductive material filler and the substrate 254. The trench structure 252 according to the sixth exemplary embodiment may be an alternative embodiment of the fourth and / or fifth exemplary embodiments, having multiple conductive materials within the trench structure 252, wherein a second conductive material contacts the substrate 254 in the transition region.

[0114] refer to Figure 8A As described with respect to the fifth exemplary embodiment, a wide trench 600 may be formed in the substrate 254, its bottom portion 610 may be doped as described above, and a narrow trench 605 may then be formed at the bottom of the wide trench 600. Also as described with respect to the fifth exemplary embodiment, the wide trench 600 and the narrow trench 605 may be lined with a conformal passivation layer 620.

[0115] refer to Figure 8B As described similarly with respect to the fifth exemplary embodiment, a first conductive material 730 may be deposited in the wide trench 600 and the narrow trench 605. The first conductive material 730 may include polysilicon. In some embodiments, for example, in the same process step, polysilicon may be used to fill the narrow trench 605 and to coat the wide trench 600. The polysilicon may not completely fill the wide trench 600, for example, leaving a cavity 750 within the polysilicon.

[0116] refer to Figure 8C In some embodiments, the photoresist can be patterned to suitably etch the first conductive material 730 from the wide trench 600. The first conductive material 730 can be etched from the wide trench 600, for example, to completely remove it from the wide trench 600. Etching can create a second cavity 850 in the first conductive material 730 in the narrow trench 605. The photoresist can be removed as needed.

[0117] refer to Figure 8DThe continuous passivation layer 620 can be etched away at the transition region. For example, spacer etching can be performed to remove some or all of the passivation layer 620 from the surface of the horizontal trench, such as removing enough passivation layer to allow contact with the conductive filler material. In some embodiments, such as using polysilicon as the first conductive material 730, the bottom of the second cavity 850 can also be etched.

[0118] refer to Figure 8E The second conductive material 840 may be deposited within the wide trench 600. In some embodiments, the second conductive material may also be deposited within the first conductive material 730 within the narrow trench 605 (e.g., within the second cavity 850). The second conductive material 840 may make electrical contact with the substrate 254 in the transition region between the narrow trench 605 and the wide trench 600 through openings in the passivation layer 620. The second conductive material 840 may, for example, comprise tungsten.

[0119] In some embodiments, a second conductive material 840 may also be deposited on the FS surface 258 of the substrate 254 (not shown), and the substrate may then be patterned and etched as part of the wiring layer 206 (not shown). The second conductive material 840 may be coupled to appropriate circuitry of the SPAD imager 100 via one or more conductive signal lines 212, 214 to form first contacts for one or more adjacent SPADs 104-1, 104-2. For example, the first contacts may be located in stepped areas on one or both sides of the isolation trench 252.

[0120] refer to Figures 9A to 9E A second subset of the trench isolation implementations may include some seventh exemplary embodiments having a trench structure 252 that may extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 may include a stepped FS trench having a wide trench 600 and a narrow trench 605, each lined with a passivation layer, wherein separation of the passivation layer at a transition region allows electrical coupling of the conductive material filler to the substrate 254. Some trench structures 252 according to the seventh exemplary embodiment may, for example, be variations of the second and / or sixth exemplary embodiments, having separate narrow FS trenches formed through the conductive material.

[0121] refer to Figure 9A As described with respect to the sixth exemplary embodiment, a wide trench 600 may be formed in the substrate 254, and its bottom portion 610 may be doped as described above. In some seventh exemplary embodiments, a first passivation layer 920 may be formed in the wide trench 600. As described above, the first passivation layer 920 may be a deposited conformal passivation layer.

[0122] The passivation layer 920 can be removed at the bottom of the wide trench 600. For example, spacer etching can be performed to remove some or all of the passivation layer 920 from the surface of the horizontal trench, such as removing enough passivation layer to allow contact between the conductive filler material and the substrate 254. In other embodiments, the passivation layer 920 may be formed on the sidewalls of the wide trench 600, rather than on the bottom of the wide trench 600. The formation of the passivation layer 920 and the doping of the bottom portion 610 of the wide trench 600 can occur in any suitable order.

[0123] refer to Figure 9B Conductive material 930 may be deposited in wide trench 600. Conductive material 930 may be in electrical contact with substrate 254 at the bottom of wide trench 600. Conductive material 930 may, for example, comprise tungsten. In some embodiments, conductive material 930 may also be deposited on the FS surface 258 (not shown) of substrate 254, and the substrate may then be patterned and etched as part of wiring layer 206 (not shown). Conductive material 930 may be coupled to appropriate circuitry of SPAD imager 100 via one or more conductive signal lines 212, 214 to form first contacts for one or more adjacent SPADs 104-1, 104-2.

[0124] refer to Figure 9C The narrow trench 605 can be etched through the conductive material 930 in the wide trench 600. Appropriate patterning of a photoresist can be applied, and the narrow trench 605 can then be etched through the conductive material 930 and the substrate 254. The narrow trench 605 can be etched to any suitable distance through the substrate 254.

[0125] In some embodiments, the narrow trench 605 may be etched to have a depth equal to one to five times the depth of the wide trench 600, for example, two to four times the depth of the wide trench 600. In some embodiments, the narrow trench 605 is formed to a depth approximately twice that of the wide trench 600. In some embodiments, the photoresist may be stripped after etching the narrow trench 605.

[0126] refer to Figure 9D The second passivation layer 950 may be formed in the narrow trench 605, for example, including the conductive material 930 formed on the wide trench 600. The second passivation layer 950 may be a conformal passivation layer. (See reference) Figure 9E The narrow trench 605 (included within the wide trench 600) may be filled using a filler material 960. In some embodiments, the filler material 960 may include a conductive material, such as polysilicon. The filler material 960 may also be deposited on an FS258, which may then be patterned, etched, and coupled to the appropriate circuitry of the SPAD imager 100, as described above.

[0127] The conductive material 930 may make electrical contact with the substrate 254 in a transition region between the narrow trench 605 and the wide trench 600 (e.g., between the two passivation layers 620, 950). The conductive material 930 may form first contacts for one or more adjacent SPADs 104-1, 104-2. For example, the first contacts may be located in stepped regions on one or both sides of the isolation trench 252.

[0128] Third subset of exemplary implementations

[0129] Next, a third subset of embodiments forming the improved trench isolation structure 252 will be described. This third subset of embodiments includes a trench structure 252 having embedded first contacts substantially located at the corners of one or more SPAD pixels 260, and having no or substantially no first contacts along either side of the one or more SPAD pixels 260. The third subset of embodiments may include embedded first contacts substantially located at points where four SPAD pixels 260 meet, and these embedded first contacts may be electrically coupled to, for example, one, two, three, or four adjacent SPAD pixels 260. Positioning the first contacts substantially at the corner intersections of the SPAD pixels 260 allows for smaller critical dimensions of the trench structure 252 and closer spacing between the SPAD pixels 260.

[0130] A third subset of the implementation of the trench structure 252 restricts the first contact point for each SPAD 104-1 to one or more corner regions of the corresponding SPAD pixel 260, thereby further increasing the distance between the first and second contacts of the SPAD 104-1 compared to positioning the first contact point along one side of the SPAD pixel 260. This increased distance further reduces the electric field and reduces the risk of edge breakdown of the SPAD 104-1.

[0131] Other subsets of the embodiments described above and below include variations, which are also included within this third subset of the embodiments. For example, see reference... Figures 10A to 10D The sixth exemplary embodiment described above may include the following variations, which have the following characteristics: Figures 8A to 8E The groove structure 252 described is basically located at the corner of the corresponding SPAD pixel 260.

[0132] Figure 10A The relative horizontal arrangement of the various components of the trench structure 252 is shown representatively, without regard to the vertical position of such a structure. Figures 10B to 10D The relative vertical arrangement of the various components of the trench structure is shown.

[0133] refer to Figure 10AThe array of SPADs 104-1, 104-2, 104-3, 104-4, 104-5, 104-6, and 104-7 may include narrow trenches 605 lined with a passivation layer 620, which substantially surrounds the SPAD pixel 260, has no openings in the passivation layer, and thus prevents the formation of first contacts on the sides of the respective SPAD pixel 260. The array of SPADs 104-1, 104-2, 104-3, 104-4, 104-5, 104-6, and 104-7 may include, as per [reference to...] Figure 8E The trench structure 252 described and illustrated is located at the farthest extent on one or more sides of the corresponding SPAD pixel 260. That is, regarding Figure 8E The groove structure 252 may be located at one or more corners of each SPAD pixel 260 to provide a first contact point for one or more adjacent SPADs.

[0134] Figures 10C to 10D Is it like this? Figure 10A The second and third cross sections referenced in the text illustrate how the above-described cross sections can be formed at the corners of one or more SPAD pixels 260 in these sixth embodiments. Figure 8E The trench isolation structure 252 described and illustrated herein. The trench structure 252 may include a wide trench 600 and a narrow trench 605, and may be filled with a first conductive material 730 and a second conductive material 840. In some embodiments, the first conductive material 730 may include polysilicon, and the second conductive material may include tungsten.

[0135] The trench structure 252 may include an opening at the passivation layer 620 at the transition region to allow the second conductive material 840 to be electrically coupled to the substrate 254, thereby forming first contacts at one or more corners of the respective SPAD pixel 260 with respect to the respective SPADs 104-3, 104-4, 104-5, 104-6, 104-7. In some embodiments, the trench structure 252 at the corners of the SPAD pixel 260 may be symmetrical in two orthogonal directions with respect to the plane of FS258 and BS256, for example, as shown in... Figure 10C and Figure 10D The cross-section is shown.

[0136] refer to Figure 10B , it is like Figure 10AThe first cross-section referenced in the figure may not form a wide trench 600 and a transition region with passivation layer openings along the remaining portion of the side surface of the SPAD pixel 260. In some embodiments, a narrow trench 605 portion of the trench structure 252 may be formed only along the remaining portion of the side surface of the SPAD pixel 260. The narrow trench 605 structure along the side surface of the SPAD pixel 260 may be formed simultaneously with the narrow trench 605 structure at the corner of the SPAD pixel 260, and may be appropriately filled with a first conductive material 730 and a second conductive material 840.

[0137] The narrow trench 605 structure along the side of the SPAD pixel 260 can therefore have the same or similar structure and material arrangement as the narrow trench 605 structure formed in the corner of the SPAD pixel 260. The unbroken passivation layer 620 of the narrow trench prevents the second conductive material 840 from being electrically coupled to the substrate 254.

[0138] For another example, see [reference] Figures 11A to 11C The above text is about Figures 5A to 5C The described third exemplary embodiment may include the following variations, which make regarding Figure 5B The described FS trench 500 is substantially located at the corner of the corresponding SPAD pixel 260 and makes about Figure 5C The described trench structure 252 is positioned along the remaining portion of the side of the corresponding SPAD pixel 260. These variations may include segmented BS trenches 505. Figure 11A The relative horizontal arrangement of the various components of the trench structure 252 is shown representatively, without regard to the vertical position of such a structure. Figure 11B and Figure 11C The relative vertical arrangement of the various components of the trench structure is shown.

[0139] refer to Figure 11A The arrays of SPAD 104-1, 104-2, 104-3, and 104-4 may include, as per the information provided... Figure 11C The isolation trench structure 252 described and shown essentially surrounds the SPAD pixel 260. Similar to... Figure 5C Here Figure 11C The isolation trench structure 252 includes both FS trench 500 and BS trench 505 structures. These FS trench 500 and BS trench 505 structures may not have an opening between the facing portions of the BS trench 505 and the FS trench 500, thus preventing the formation of a first contact point on the side of the corresponding SPAD pixel 260.

[0140] SPAD 104-1, 104-2, 104-3, and 104-4 arrays may include, as per [reference to...] Figure 11BThe FS trench 500 described and shown does not have a BS trench 505 located at the furthest range 1110 on one or more sides of the corresponding SPAD pixel 260. That is, regarding Figure 11B The FS trench 500 may be positioned adjacent to one or more corners of each SPAD pixel 260 to provide a first contact point for one or more adjacent SPADs 104-1, 104-2, 104-3, 104-4.

[0141] refer to Figure 11B , it is like Figure 11A The first cross-section referenced herein, according to the trench isolation structure 252 of the FS trench 500 described above with respect to the third exemplary embodiment, may be formed at the corner of one or more SPAD pixels 260. Similar to... Figure 5B , Figure 11B The FS trench 500 may include an opening at the bottom of the FS trench 500 to allow the conductive material 550 to be electrically coupled to the substrate 254, thereby forming a first contact at the corner of one or more corresponding SPAD pixels 260.

[0142] In some implementations, the groove structure 252 at the corner of the SPAD pixel 260 may be symmetrical in two orthogonal directions that are in the same plane as FS 258 and BS 256. In some such implementations, the BS groove 505 is absent at the corner intersection of the SPAD pixel 260, which may have a negligible or minor negative impact on SPAD pixel isolation.

[0143] refer to Figure 11C , it is like Figure 11A The second cross-section referenced herein, along the remaining portion of the sidewall of SPAD pixel 260, includes both the FS trench 500 and the BS trench 505 described above with respect to the third exemplary embodiment, such that the high-k material 570 and / or passivation layer 560 of the BS trench contacts the passivation layer 520 of the FS trench 500, thereby preventing the conductive material 550 from electrically coupling with adjacent SPADs 104-3, 104-4. In some embodiments, the FS trench 500 at the corner of SPAD pixel 260 may be formed simultaneously with the FS trench 500 along the sidewall of SPAD pixel 260.

[0144] For another example, see [reference] Figures 12A to 12C The above text is about Figures 5A to 5C The described third exemplary embodiment may include the following variations, which make regarding Figure 5B The described trench structure 252 is substantially located at the corner of the corresponding SPAD pixel 260 and makes about Figure 5CThe described trench structure 252 is positioned along the remaining portion of the side of the corresponding SPAD pixel 260. These variations may include segmented BS trenches 505.

[0145] Figure 12A The relative horizontal arrangement of the various components of the trench structure 252 is shown representatively, without regard to the vertical position of such a structure. Figure 12B and Figure 12C The relative vertical arrangement of the various components of the trench structure is shown.

[0146] like Figure 12A As shown, the arrays of SPAD 104-1, 104-2, 104-3, and 104-4 may include, as per the description... Figure 12C The isolation trench structure 252 described and shown essentially surrounds the SPAD pixel 260. Similar to... Figure 5C Here Figure 12C The isolation trench structure 252 includes both FS trench 500 and BS trench 505 structures. These FS trench 500 and BS trench 505 structures may not have an opening between the facing portions of the BS trench 505 and the FS trench 500, thus preventing the formation of a first contact point on the side of the corresponding SPAD pixel 260.

[0147] Also in Figure 12A In this context, the arrays of SPAD 104-1, 104-2, 104-3, and 104-4 may include, as per [reference to...] Figure 12B The isolation trench structure 252 described and shown is located at the furthest extent 1110 on one or more sides of the corresponding SPAD pixel 260. Similar to... Figure 5B Here Figure 12B The isolation trench structure 252 includes an FS trench 500 and a BS trench 505 located on one side of the isolation trench structure 252.

[0148] In some implementations, the groove structure 252 at the corner of the SPAD pixel 260 may be open only to one adjacent SPAD pixel 260. That is, regarding Figure 12B The described arrangement of the FS trench 500 and BS trench 505 may be located at a corner of each SPAD pixel 260 to provide a first contact to only one adjacent SPAD 104-1. In some such embodiments, SPAD pixel isolation can be maintained because the substrate 254 of each SPAD pixel remains laterally isolated from adjacent SPAD pixels.

[0149] In some implementations, the FS groove 500 at the corner of the SPAD pixel 260 may be formed simultaneously with the FS groove 500 along the side of the SPAD pixel 260, and the BS groove 505 at the corner of the SPAD pixel 260 may be formed simultaneously with the BS groove 505 along the side of the SPAD pixel 260.

[0150] Fourth subset of exemplary implementations

[0151] Next, a fourth subset of embodiments forming the improved trench isolation structure 252 will be described. This fourth subset of embodiments includes a trench structure 252 having a first contact located within the trench structure 252 at substantially the same surface of the substrate as the second contact of the SPAD 104-1. In some embodiments, the SPAD 104-1 has a second contact (e.g., a cathode) on or near the front side of the substrate and a first contact (e.g., an anode) on or near the front side. This fourth subset of embodiments may include a first contact electrically coupled to one, two, three, or four adjacent SPAD pixels 260.

[0152] refer to Figures 13A to 13D A fourth subset of the trench isolation implementation may include some eighth exemplary implementations having a trench structure 252 that may extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 may include an FS trench lined with a passivation layer, wherein an opening in the passivation layer near FS 258 allows a conductive material filler to be electrically coupled to a substrate 254 near FS 258.

[0153] refer to Figure 13A As described above, FS trenches 1300 can be formed in substrate 254 to any suitable depth. (Reference) Figure 13B A passivation layer 1320 can be formed in the FS trench 1300. The passivation layer 1320 can be a deposited conformal passivation layer.

[0154] refer to Figure 13C Some of the passivation layer 1320 can be removed from the top of the FS trench 1300. For example, spacer etching can be performed to completely remove the passivation layer 1320 from the top portion of the FS trench 1300 near the FS258. In some embodiments, the passivation layer 1320 at the bottom of the FS trench 1300 can also be partially or completely removed, for example, by etching from the same spacer.

[0155] A portion 1310 of the opening of the passivation layer 1320 near the top of the FS trench 1300 on substrate 254 may be doped, for example, by implantation with charged ions as described above. In some embodiments, the same photoresist used for spacer etching may be used for ion implantation prior to stripping the photoresist. In other embodiments, substrate 254 and / or FS trench 1300 may be individually patterned for ion implantation. One or more photoresists may be suitably stripped, and then ion implantation may be activated as described above.

[0156] refer to Figure 13D Conductive material 1330 may be deposited in FS trench 1300. Conductive material 1330 may be in electrical contact with substrate 254 adjacent to FS 258, and in some embodiments also extends through the bottom of FS trench 1300. Conductive material 1330 may, for example, comprise tungsten.

[0157] In some embodiments, conductive material 1330 may also be deposited on FS258 (not shown) of substrate 254, and the substrate may then be patterned and etched as part of wiring layer 206 (not shown). The conductive material 1330 may be coupled to appropriate circuitry of SPAD imager 100 via one or more conductive signal lines 212, 214 to form first contacts for one or more adjacent SPADs 104-1, 104-2, such as FS258 on one or both sides near isolation trench 252.

[0158] refer to Figures 14A to 14D A fourth subset of the trench isolation implementation may include some ninth exemplary implementations having a trench structure 252 that may extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 may include FS trenches filled with a passivation layer except for those near FS 258, wherein the conductive material filler in the FS trenches near FS 258 is electrically coupled to the substrate 254.

[0159] refer to Figure 14A As described above, FS trenches 1300 can be formed in substrate 254 to any suitable depth. (Reference) Figure 14B The FS trench 1300 may be filled with a passivation material 1420, such as an oxide, like silicon dioxide. In some embodiments, the FS trench 1300 may be completely filled with the passivation material 1420. In some embodiments, the top portion of the FS trench 1300 may not have any passivation material 1420 left.

[0160] refer to Figure 14CSome passivation material 1420 can be removed from the top of the FS trench 1300. For example, spacer etching can be performed to completely remove the passivation material 1420 from the top portion of the FS trench 1300 near FS258. The passivation material 1420 can be removed to any suitable depth within the FS trench 1300.

[0161] A portion 1310 of the passivation material 1420 near the top of the FS trench 1300 on the substrate 254, which has been removed or is otherwise absent, may be doped, for example, by implantation with charged ions as described above. In some embodiments, the same photoresist used for spacer etching may be used for ion implantation prior to stripping the photoresist. In other embodiments, the substrate 254 and / or the FS trench 1300 may be individually patterned for ion implantation. One or more photoresists may be suitably stripped, and then ion implantation may be activated as described above.

[0162] refer to Figure 14D Conductive material 1430 may be deposited in FS trench 1300. Conductive material 1430 may be in electrical contact with substrate 254 adjacent to FS 258. Conductive material 1430 may, for example, include tungsten.

[0163] In some embodiments, conductive material 1430 may also be deposited on FS258 (not shown) of substrate 254, and the substrate may then be patterned and etched as part of wiring layer 206 (not shown). The conductive material 1430 may be coupled to appropriate circuitry of SPAD imager 100 via one or more conductive signal lines 212, 214 to form first contacts for one or more adjacent SPADs 104-1, 104-2, such as FS258 on one or both sides near isolation trench 252.

[0164] refer to Figures 15A to 15E A fourth subset of the trench isolation implementation may include some tenth exemplary implementations having a trench structure 252 that may extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 may include an FS trench lined with a passivation layer and filled with a first conductive material, wherein an opening in the passivation layer near FS 258 allows a second conductive material to be electrically coupled to a substrate 254 near FS 258.

[0165] refer to Figure 15A As described above, FS trenches 1300 can be formed in substrate 254 to any suitable depth. (Reference) Figure 15B A passivation layer 1320 can be formed in the FS trench 1300. The passivation layer 1320 can be a deposited conformal passivation layer. (Reference) Figure 15CThe FS trench 1300 may be filled with a first conductive material 1540. In some embodiments, the first conductive material 1540 may include polycrystalline silicon.

[0166] refer to Figure 15D In some embodiments, some of the passivation layer 1320 may be removed from the top of the FS trench 1300. For example, spacer etching may be performed to completely remove the passivation layer 1320 from the top portion of the FS trench 1300 near FS258. In some embodiments, the first conductive material 1540 remains substantially the same before and after the removal of the passivation layer 1320.

[0167] A portion 1310 of the opening of the passivation layer 1320 near the top of the FS trench 1300 on substrate 254 may be doped, for example, by implantation with charged ions as described above. In some embodiments, the same photoresist used for spacer etching may be used for ion implantation prior to stripping the photoresist. In other embodiments, substrate 254 and / or FS trench 1300 may be individually patterned for ion implantation. One or more photoresists may be suitably stripped, and then ion implantation may be activated as described above.

[0168] refer to Figure 15E The second conductive material 1530 may be deposited in the FS trench 1300, for example, in a cavity provided by removing the passivation layer 1320. The second conductive material 1530 may be in electrical contact with the substrate 254 adjacent to the FS 258. The second conductive material 1530 may, for example, comprise tungsten.

[0169] In some embodiments, a first conductive material 1540 and / or a second conductive material 1530 may also be deposited on the FS258 of the substrate 254 (not shown), and the substrate may then be patterned and etched as part of the wiring layer 206 (not shown). The conductive first conductive material 1540 and / or the second conductive material 1530 may be coupled to appropriate circuitry of the SPAD imager 100 via one or more conductive signal lines 212, 214 to form first contacts for one or more adjacent SPADs 104-1, 104-2, such as on the FS258 near one or both sides of the isolation trench 252.

[0170] Fifth subset of exemplary implementations

[0171] Next, a fifth subset of embodiments forming the improved trench isolation structure 252 will be described. This fifth subset includes an FS trench having a passivation layer and a conductive material filler, arranged to form one or more first contacts of SPAD104-1, as described above according to the various exemplary embodiments. The fifth subset also includes a segmented BS trench having a first portion contacting one side of the bottom of the FS trench and a second portion contacting both sides of the bottom of the FS trench.

[0172] The segmented BS trench can be applied to the implementations of the first to fourth subsets of the exemplary embodiments described above. For example, the implementation of the fifth subset of the exemplary embodiments may include the implementation according to the third exemplary embodiment and as shown with respect to Figure 5. Figures 11A to 11C and Figures 12A to 12C The described trench structure 252. For example, as shown in Figure 5, Figures 11A to 11C and Figures 12A to 12C The segmented BS trench structure described can also be used in conjunction with the FS trench structure described above. Therefore, the fifth subset of the exemplary embodiments also includes variations of the first, second, fourth, fifth, sixth, seventh, eighth, ninth, and tenth exemplary embodiments described above.

[0173] Therefore, according to various embodiments of several subsets of the exemplary embodiments described above, the isolation trench 252 may include a trench having a single passivation layer and metal within the trench, the metal contacting the substrate 254 through an opening in the passivation layer. The isolation trench 252 may include a single passivation layer in an annular ring surrounding each SPAD pixel 260 and metal located between the annular rings and away from the contact between the FS258 and the substrate 254.

[0174] The isolation trench 252 may include a stepped region. For example, the isolation trench 252 may include an FS trench having a single passivation layer and being filled with polysilicon at the BS portion facing the FS trench and with metal at the FS portion facing the FS trench, wherein the metal contacts the substrate 254 through an opening in the passivation layer at the stepped region. The isolation trench 252 may include an FS trench having a single passivation layer and being filled with polysilicon and with metal at the FS portion facing the FS trench, wherein the polysilicon contacts the substrate 254 through an opening in the passivation layer at the stepped region.

[0175] The isolation trench 252 may include an FS trench with a single passivation layer, in which metal is filled, wherein the metal contacts the substrate 254 away from FS 258, and the isolation trench may include a BS trench, which is formed from BS 256 as a deep trench using a high-k material and silicon dioxide. The FS trench and the BS trench may be separate and / or connected. In some such embodiments, the FS trench and the BS trench are segmented and connected to allow a path for the electric field used for the anode / cathode and have overlap to prevent light leakage (e.g., crosstalk) due to scattering from scattering structures in or near pixel 260.

[0176] The isolation trench 252 may include an FS trench with two passivation layers, wherein the inner passivation layer is filled with polysilicon and metal is located between the outer passivation layer and the inner passivation layer and in contact with the substrate 254. The metal may form a ring around the polysilicon. The isolation trench 252 may include an FS trench line or be filled with passivation layers and include metal adjacent to the FS 258, wherein the metal is in contact with the substrate 254.

[0177] The isolation trench 252 may include an embodiment having a first contact of SPAD104-1 only at the intersection of three or more pixels (e.g., at a corner). The contact at the intersection may include an opening in a single passivation layer, thereby allowing the metal of the trench 252 to contact the substrate, and the remainder along the side of the pixel 260 has no opening in a single passivation layer.

[0178] Figures 16A to 16D An exemplary geometric arrangement of a representative isolation trench structure is shown. For example, a stepped trench structure 252 according to any one of the first to fourth stepped isolation trench structures may include a narrow trench 605 that is approximately twice as deep as the wide trench 600 of the stepped trench structure 252. The SPAD pixels 260 may have any suitable spacing as described above, for example, approximately 2 μm to approximately 3 μm.

[0179] refer to Figure 16A The substrate 254 may have a depth D1 of approximately 3 μm, the wide trench 600 may have a depth of approximately 1 μm, and the narrow trench 605 may have a depth of approximately 2 μm. The wide trench 600 may have a critical dimension (CD) of approximately 150 nm, and the narrow trench 605 may have a critical dimension of approximately 100 nm. Therefore, the wide trench 600 may have an aspect ratio (AR) of approximately 6.7, and the narrow trench 605 may have an aspect ratio of approximately 20.

[0180] refer to Figure 16BThe substrate 254 may have a depth D1 of approximately 3 μm, the wide trench 600 may have a depth of approximately 1 μm, and the narrow trench 605 may have a depth of approximately 2 μm. The wide trench 600 may have a critical dimension (CD) of approximately 400 nm, and the narrow trench 605 may have a critical dimension of approximately 200 nm. Therefore, the wide trench 600 may have an AR of approximately 2.5, and the narrow trench 605 may have an AR of approximately 10.

[0181] refer to Figure 16C The substrate 254 may have a depth D1 of approximately 6 μm, the wide trench 600 may have a depth of approximately 2 μm, and the narrow trench 605 may have a depth of approximately 4 μm. The wide trench 600 may have a critical dimension (CD) of approximately 400 nm, and the narrow trench 605 may have a critical dimension of approximately 200 nm. Therefore, the wide trench 600 may have an AR of approximately 5, and the narrow trench 605 may have an AR of approximately 20.

[0182] refer to Figure 16D The substrate 254 may have a depth D1 of approximately 6 μm, the wide trench 600 may have a depth of approximately 2 μm, and the narrow trench 605 may have a depth of approximately 4 μm. The wide trench 600 may have a critical dimension (CD) of approximately 600 nm, and the narrow trench 605 may have a critical dimension of approximately 400 nm. Therefore, the wide trench 600 may have an AR of approximately 3.3, and the narrow trench 605 may have an AR of approximately 10.

[0183] Other embodiments may similarly use one or more of the narrow or wide trench geometries, even without a stepped trench arrangement. For example, some embodiments according to the eighth, ninth, and / or tenth exemplary embodiments may have critical dimensions as described with respect to wide trench 600 or narrow trench 605. As another example, some embodiments according to the first exemplary embodiment may have an annular trench 310 formed with the critical dimension of wide trench 600 and a central trench 340 formed with the critical dimension of narrow trench 605.

[0184] Therefore, various embodiments provide SPAD-based systems, devices, and methods with embedded contacts. Various embodiments may include one of the anode or cathode of the SPAD within an isolation trench structure. The embedded contact may be located within the isolation trench, near the same side of the substrate as the other of the anode or cathode, and / or at a distance from the side of the substrate having the other of the anode or cathode.

[0185] The systems, apparatus, and methods described herein provide increased spacing between the anode and cathode of the respective SPAD and reduced likelihood of edge breakdown in the avalanche region of the respective SPAD. Various embodiments allow for smaller pixels, smaller critical dimensions of pixel and / or trench structures, etc. Therefore, various embodiments provide increased imager resolution.

[0186] It should be understood that the embodiments described above regarding SPAD-based pixels can be applied to other imaging pixels, such as those used in CMOS image sensors. It should also be understood that the embodiments according to this specification can be applied to rear-facing imaging devices and / or front-facing imaging devices. The various imager device structures, isolation trench structures, embedded contacts, materials, processing steps, etc., shown and described above can be arranged in any number of equivalent embodiments.

[0187] The general concepts set forth herein are applicable to any number of alternative but equivalent embodiments. The term “exemplary” is used herein to denote an example, illustration, or description that may have any number of alternatives. Any specific embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other specific embodiments, nor is it intended as a model that must be replicated in other specific embodiments. While several exemplary embodiments have been presented in the foregoing detailed description, it should be understood that numerous alternative but equivalent variations exist, and the examples presented herein are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, various changes may be made to the function and arrangement of the described elements without departing from the scope of the claims and their legal equivalents.

Claims

1. A semiconductor device, the semiconductor device comprising: A substrate having a front side and a back side; A first single-photon avalanche diode (SPAD) is located in the substrate and has a first contact near the front side of the substrate; A second SPAD is located in the substrate and positioned next to the first SPAD; and A trench isolation structure, wherein the trench isolation structure is located in the substrate between the first SPAD and the second SPAD, the trench isolation structure comprising: A frontal trench, the frontal trench having one or more vertical walls and a horizontal surface; A continuous passivation layer lining the front trench, wherein the passivation layer includes an opening at the horizontal surface of the front trench; and A conductive material is disposed within the front trench and laterally separated from the substrate through the passivation layer, wherein the conductive material is electrically coupled to the substrate through the opening in the passivation layer to form a second contact.

2. The semiconductor device according to claim 1, wherein, The conductive material includes tungsten.

3. The semiconductor device according to claim 1, wherein, The substrate near the opening of the passivation layer is positively doped.

4. The semiconductor device according to claim 1, wherein, The front groove includes: Wide groove, the wide groove being positioned close to the front side; A narrow groove extending from the bottom surface of the wide groove toward the back surface; and A transition region, located between the wide trench and the narrow trench, the transition region including the opening in the passivation layer.

5. The semiconductor device according to claim 4, wherein, The continuous passivation layer includes a second opening at the bottom surface of the narrow trench.

6. The semiconductor device according to claim 1, wherein: The opening in the passivation layer includes: A first opening, the first opening being adjacent to a first corner of the first SPAD; and A second opening is located adjacent to the second corner of the first SPAD; and The passivation layer does not include an opening between the first corner and the second corner.

7. The semiconductor device according to claim 1, wherein: The frontal groove has a first side adjacent to the first SPAD, a second side adjacent to the second SPAD, and a bottom surface; and The trench isolation structure also includes: The segmented back groove structure includes: The first part includes a dielectric material in contact with the bottom surface of the front trench on the first side of the front trench; and The second part includes the dielectric material that contacts the bottom surface of the front trench on both the first side and the second side of the front trench.

8. The semiconductor device according to claim 7, wherein, The segmented back groove structure includes the overlap of two first parts of the back groove structure.

9. The semiconductor device according to claim 1, wherein, The second contact point is located at a first depth from the front side, wherein the first depth is equal to at least half the distance between the front side and the back side.

10. A semiconductor device, the semiconductor device comprising: A substrate having a first surface and a second surface; A first single-photon avalanche diode (SPAD) is located in the substrate and has a first contact near the first surface of the substrate; A second SPAD, wherein the second SPAD is located in the substrate; and A trench isolation structure, wherein the trench isolation structure is located in the substrate between the first SPAD and the second SPAD, the trench isolation structure comprising: The trench includes: A wide trench, wherein the wide trench is positioned close to the first surface of the substrate; A narrow trench extending through the bottom surface of the wide trench toward the second surface of the substrate; and A transition zone, located between the wide trench and the narrow trench; A continuous passivation layer lining the wide trench and the narrow trench, wherein the passivation layer includes an opening at the transition region; and A conductive material is disposed within the trench and electrically coupled to the substrate through the opening in the passivation layer to form a second contact.

11. The semiconductor device according to claim 10, wherein, The substrate near the opening of the passivation layer is positively doped.

12. The semiconductor device according to claim 10, wherein, The continuous passivation layer includes a second opening at the bottom surface of the narrow trench.

13. The semiconductor device according to claim 10, wherein, The conductive material includes tungsten.

14. The semiconductor device according to claim 10, wherein, The conductive material includes: The first part, the first part comprising polycrystalline silicon; and The second part comprises tungsten deposited on the first part.

15. The semiconductor device according to claim 10, wherein: The opening in the passivation layer includes: A first opening, the first opening being adjacent to a first corner of the first SPAD; and A second opening is located adjacent to the second corner of the first SPAD; and The passivation layer does not include an opening between the first corner and the second corner.

16. A method for forming a trench isolation structure between a first single-photon avalanche diode (SPAD) and a second SPAD in a substrate, wherein the substrate has a front side and a back side, and the first SPAD has a first electrical contact proximate to the front side of the substrate, the method comprising: Etch a frontal trench between the first SPAD and the second SPAD; A continuous passivation layer is formed in the front trench; An opening is formed in the continuous passivation layer at the horizontal surface of the front trench; as well as A conductive material is formed in the front trench, wherein the conductive material is electrically coupled to the substrate through the opening to form a second electrical contact.

17. The method according to claim 16, further comprising: The substrate is doped near the opening.

18. The method of claim 16, wherein: Etching the front trench includes: Etching wide trenches; and Narrow trenches are etched through the bottom surface of the wide trenches; Forming the continuous passivation layer includes simultaneously forming the continuous passivation layer in both the wide trench and the narrow trench; and Forming an opening in the continuous passivation layer includes opening the continuous passivation layer at the transition region between the wide trench and the narrow trench.

19. The method of claim 16, wherein, Forming an opening in the continuous passivation layer includes opening the continuous passivation layer at a first corner and a second corner of the first SPAD without opening the continuous passivation layer between the first corner and the second corner, wherein the first corner and the second corner of the first SPAD are adjacent to the second SPAD.

20. The method of claim 16, further comprising: Forming segmented back grooves, including: A first portion of the back trench is etched onto a first side of the bottom surface of the front trench, wherein the first side is adjacent to the first SPAD; The second portion of the back trench is etched onto both the first and second sides of the bottom surface of the front trench, wherein the second side of the front trench is adjacent to the second SPAD; and The first and second portions of the back trench are filled with a dielectric material.

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