Semiconductor substrate etching method and photoresist etching resistance evaluation method

Abstract

The invention relates to a semiconductor substrate etching method and a photoresist anti-etching performance evaluation method. The semiconductor substrate etching method comprises the following steps: providing a semiconductor substrate partially covered by a metal-based photoresist pattern layer; and etching the semiconductor substrate partially covered by the metal-based photoresist pattern layer by using a mixed gas comprising a first etching gas and a second etching gas, the first etching gas comprising a C-F group, and the second etching gas comprising an S-F group. The method for evaluating the etching resistance of the photoresist comprises the following steps: providing an object layer; forming a photoresist pattern layer on the object layer; shielding at least one part of an area, which is not covered by the photoresist, on the object layer to obtain a test sample; etching the test sample; and calculating the etching selection ratio according to the following formula, wherein the shielded part of the object layer is not etched. The etching method can realize high selection ratio and high depth-to-width ratio of the etched pattern, and the pattern transmission morphology is vertical; the evaluation method is simple to operate and accurate in selection ratio calculation result.

Description

Technical Field

[0001] This disclosure belongs to the field of photolithography technology, specifically relating to a semiconductor substrate etching method based on metal-based photoresist and a method for evaluating the etching resistance of photoresist. Background Technology

[0002] Advances in photolithography technology and materials are crucial factors driving the development of the semiconductor industry. As the integration density of integrated circuits continues to increase, the requirements for photoresist resolution also rise. According to the Rayleigh equation, photoresist resolution is inversely proportional to the exposure wavelength, so reducing the exposure wavelength is the primary way to improve resolution. Photoresist resolution is evolving from micrometers and submicrometers to nanometers, which necessitates continuously decreasing the wavelength of the exposure light source, while simultaneously ensuring high transmittance of the photoresist within the corresponding wavelength range. Based on different lithography precision and light source wavelengths, photoresists can be categorized into g-line photoresists, i-line photoresists, KrF photoresists, ArF photoresists, and EUV (Extreme Ultraviolet) photoresists, with EUV photoresists having a light source wavelength of 13.5 nm. Due to its high lithography precision, this photoresist is the dominant lithography process for next-generation advanced processes and can be applied to processes below 7 nm. With the development of high-end processes, the demand for EUV photoresists is increasing.

[0003] EUV lithography is currently the most promising and important technology at the advanced technology node of integrated circuits, requiring advanced EUV photoresist materials. In EUV lithography processes, for stripes with a resolution of 20-30nm, to prevent pattern collapse, the aspect ratio must not exceed 2:1, resulting in a photoresist film thickness of approximately 40-60nm. This relatively thin film thickness necessitates EUV photoresists with strong etching resistance and high etching selectivity to effectively protect the underlying material during pattern transfer. Existing literature reports that metal-based photoresists possess advantages such as high sensitivity, good pattern resolution, low edge roughness, and strong etching resistance, making them highly promising EUV photoresists. However, for metal-based photoresists, conventional etching methods using Cl2, HBr, and CF gases cannot achieve a high selectivity ratio between the underlying material and the metal-based photoresist, failing to meet the requirements of strong etching resistance and high etching selectivity for EUV photoresists. Therefore, developing a high-selectivity etching method specifically for metal-based photoresists is crucial.

[0004] Currently reported methods for evaluating the etching resistance of positive photoresists are relatively simple. Metal-based photoresists, however, are negative photoresists, and their etching resistance evaluation methods are more complex. In SEM (Scanning Electron Microscopy) and AFM (Atomic Force Microscopy) characterization, the interface between the metal-based photoresist layer and the semiconductor substrate is unclear, making it difficult to determine the remaining thickness of the photoresist and the etching depth of the semiconductor substrate. This complicates the calculation of etching rates and selectivity ratios. Therefore, a new method for evaluating the etching resistance of negative photoresists needs to be developed. Summary of the Invention

[0005] This disclosure addresses the requirements of existing technologies for the etching resistance of high-resolution photoresists by proposing a high-selectivity etching method based on metal-based photoresists and a novel method for evaluating the etching resistance of negative photoresists. The metal-based photoresist etching method of this disclosure can achieve high selectivity and high aspect ratio in the etched patterns, with vertical pattern transfer topology. The photoresist etching resistance evaluation method of this disclosure is simple to operate and provides accurate selectivity calculation results.

[0006] On one hand, this disclosure relates to a semiconductor substrate etching method, the method comprising:

[0007] Provides a semiconductor substrate partially covered by a metal-based photoresist patterning layer;

[0008] A semiconductor substrate partially covered by a metal-based photoresist pattern layer is etched using a mixed gas containing a first etching gas and a second etching gas.

[0009] The first etching gas contains CF groups, and the second etching gas contains SF groups.

[0010] In some embodiments, the metal-based photoresist is selected from metal oxide cluster photoresist, metal oxide nanoparticle photoresist, and metal-organic small molecule photoresist.

[0011] In some embodiments, the first etching gas is selected from one or more of CH3F, CH2F2, CHF3, and CF4.

[0012] In some embodiments, the first etching gas is CHF3.

[0013] In some embodiments, the second etching gas is selected from SF6.

[0014] In some embodiments, the semiconductor substrate is selected from one or more of silicon, silicon dioxide, and silicon nitride substrates.

[0015] In some embodiments, the etching is performed within a plasma chamber.

[0016] In some implementations, the first etching gas flow rate is 10-100 sccm.

[0017] In some implementations, the second etching gas flow rate is 2-20 sccm.

[0018] In some implementations, the etching power is 10-500W.

[0019] In some implementations, the etching pressure is 1-50 mTorr.

[0020] In some implementations, the etching time is 10s-300s.

[0021] In some implementations, the etching temperature is 5-35°C.

[0022] On the other hand, this disclosure relates to a method for evaluating the etching resistance of photoresist, the method comprising:

[0023] Provide an object layer;

[0024] A photoresist pattern layer is formed on the object layer;

[0025] By masking at least a portion of the area on the object layer that is not covered by photoresist, a test sample is obtained.

[0026] The test sample was etched;

[0027] The etching selectivity ratio is calculated using the following formula:

[0028]

[0029] Where S represents the etching selectivity, d1 represents the vertical distance between the top plane of the photoresist pattern layer before etching and the bottom plane of the photoresist pattern layer, d2 represents the vertical distance between the top plane of the target layer at the masked area after etching and the bottom plane formed after etching, and d3 represents the vertical distance between the top plane of the photoresist pattern layer after etching and the bottom plane formed after etching. d1, d2, and d3 have the same unit.

[0030] The parts of the object layer that are hidden are not etched.

[0031] In some implementations, the object layer is a semiconductor substrate.

[0032] In some embodiments, preferably, the semiconductor substrate is selected from one or more of silicon, silicon dioxide, and silicon nitride substrates.

[0033] In some embodiments, the photoresist is a metal-based photoresist.

[0034] In some embodiments, the metal-based photoresist is selected from metal oxide cluster photoresist, metal oxide nanoparticle photoresist, and metal-organic small molecule photoresist.

[0035] In some implementations, at least a portion of the area on the object layer not covered by photoresist is masked with an insulating material that is inert to the etchant.

[0036] In some implementations, insulating tape is used to mask at least a portion of the area on the object layer that is not covered by photoresist.

[0037] In some embodiments, etching is performed using a mixture of a first etching gas and a second etching gas.

[0038] In some embodiments, the first etching gas is selected from one or more of CH3F, CH2F2, CHF3, and CF4.

[0039] In some embodiments, the first etching gas is CHF3.

[0040] In some embodiments, the second etching gas is selected from SF6.

[0041] In some implementations, d1, d2, and d3 are measured using an atomic force microscope. Attached Figure Description

[0042] Figure 1 This diagram illustrates the etching selectivity of a silicon wafer etched using the semiconductor substrate etching method disclosed herein and the measurement of the etching selectivity using the photoresist etching resistance evaluation method disclosed herein.

[0043] Figure 2 (a) is a photograph of a portion of the silicon wafer not covered by photoresist, which was masked with 3M tape in Example 1.

[0044] Figure 2 (b) is an AFM characterization diagram of the thickness of the photoresist film after exposure and development in Example 1 without etching.

[0045] Figure 2 (c) is the AFM characterization diagram of the trench depth after 60s of etching in Example 1.

[0046] Figure 2 (d) is the AFM characterization diagram of the height difference of the silicon wafer with and without the shielding portion after etching for 60s in Example 1 (a small amount of surface burrs does not affect the measurement of the silicon substrate height difference).

[0047] Figure 3 (a) is a SEM cross-sectional view of the pattern formed in the silicon wafer after etching in Example 1.

[0048] Figure 3(b) is a SEM cross-sectional view of the pattern formed in the silicon wafer after etching in Example 2. Detailed Implementation

[0049] To enable those skilled in the art to understand the features and effects of the present invention, the terms and expressions used in the specification and claims are explained and defined in general below. Unless otherwise specified, all technical and scientific terms used herein have the ordinary meaning understood by those skilled in the art regarding the present invention, and in case of conflict, the definitions in this specification shall prevail.

[0050] The theories or mechanisms described and disclosed herein, whether right or wrong, should not in any way limit the scope of the invention, that is, the contents of the invention can be implemented without being limited by any particular theory or mechanism.

[0051] In this document, the terms “contains,” “includes,” “containing,” and similar terms encompass the meanings of “basically composed of” and “composed of.” For example, when this document discloses “A contains B and C,” “A is basically composed of B and C” and “A is composed of B and C” should be considered as having been disclosed in this document.

[0052] In this document, all features defined by numerical ranges or percentage ranges, such as numerical values, quantities, contents, and concentrations, are for the sake of brevity and convenience only. Accordingly, descriptions of numerical ranges or percentage ranges should be considered as covering and specifically disclosing all possible sub-ranges and individual numerical values ​​(including integers and fractions) within those ranges.

[0053] In this document, when describing embodiments or examples, it should be understood that it is not intended to limit the invention to those embodiments or examples. Rather, all alternatives, modifications, and equivalents of the methods and materials described herein are covered within the scope defined by the claims.

[0054] For the sake of brevity, not all possible combinations of the technical features in each implementation or embodiment are described herein. Therefore, as long as there is no contradiction in the combination of these technical features, the technical features in each implementation or embodiment can be combined arbitrarily, and all possible combinations should be considered within the scope of this specification.

[0055] Semiconductor substrate etching methods

[0056] After photoresist is coated, exposed, and developed to form a photoresist pattern, its masking effect is used to etch the substrate not covered by the photoresist. However, the photoresist is also in the etching environment and will be etched to some extent. Therefore, etching resistance is an important performance characteristic of photoresist, usually characterized by etching selectivity. Etching selectivity is defined as the ratio of the etching rate of the substrate to the etching rate of the photoresist. Metal-based photoresists, due to containing metal atoms with high EUV light absorption cross-sections, have high sensitivity and resolution, making them suitable for use as EUV photoresists. However, for metal-based photoresists, conventional etching methods using Cl2, HBr, and CF gases as etchants have low selectivity. The inventors of this application unexpectedly discovered that by using a mixed etchant containing CF groups and SF groups, the etching selectivity of the semiconductor substrate relative to the metal-based photoresist can be significantly improved.

[0057] In the term "CF group," C refers to carbon and F refers to fluorine. Similarly, in the term "SF group," S refers to sulfur and F refers to fluorine.

[0058] In this disclosure, a gas containing the CF group refers to a gas containing carbon and fluorine elements, particularly a gas composed only of carbon and fluorine elements or only of carbon, fluorine and hydrogen elements.

[0059] In this disclosure, a gas containing an SF group refers to a gas containing carbon and sulfur elements, particularly a gas composed solely of carbon and sulfur elements.

[0060] The semiconductor substrate etching method disclosed herein includes a process of providing a semiconductor substrate partially covered by a metal-based photoresist patterned layer. This process may include steps such as coating the semiconductor substrate with a metal-based photoresist material, exposure, and development to form a photoresist patterned layer. A pre-baking step may be included after coating and before exposure. A post-baking step may be included after exposure and before development. A cleaning and drying step may be included after development. These steps are known in the art.

[0061] The semiconductor substrate etching method disclosed herein further includes a step of etching a semiconductor substrate partially covered by a metal-based photoresist patterned layer using a mixed gas comprising a first etching gas and a second etching gas. The first etching gas comprises CF groups, and the second etching gas comprises SF groups. The first etching gas may be selected from one or more of CH3F, CH2F2, CHF3, and CF4. For example, CHF3 may be selected as the first etching gas. SF6 may be selected as the second etching gas. In some embodiments, the mixed gas comprising the first and second etching gases is a mixture of CHF3 and SF6.

[0062] Metal-based photoresists can be selected from metal oxide cluster photoresists, metal oxide nanoparticle photoresists, and metal-organic small molecule photoresists. These metal-based photoresists can be negative photoresists. For example, metal oxide cluster photoresists include, but are not limited to, tin-oxygen cluster photoresists; metal oxide nanoparticle photoresists include, but are not limited to, those composed of metal oxides (MO... x It consists of a core and a shell of organic carboxylic acid ligands; metal-organic small molecule photoresists include, but are not limited to, tin-containing hybrid polymer photoresists.

[0063] The semiconductor substrate can be selected from a silicon substrate.

[0064] Photoresist patterns can include line patterns, bar patterns, and aperture patterns.

[0065] Etching can be performed within a plasma chamber. The flow rate of the first etching gas can be 10–100 sccm, for example, 10 sccm, 20 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, 100 sccm, or any combination thereof. The flow rate of the second etching gas can be 2–20 sccm, for example, 2 sccm, 4 sccm, 6 sccm, 8 sccm, 10 sccm, 12 sccm, 14 sccm, 16 sccm, 18 sccm, 20 sccm, or any combination thereof. As used herein, sccm stands for standard cubic centimeters per minute, which is a unit of measurement for gas volumetric flow rate under standard conditions. In this document, "standard conditions" refers to 0°C and 1 atmosphere (1 atm).

[0066] The etching power can be 10-500W, for example, 10W, 20W, 30W, 40W, 50W, 60W, 70W, 80W, 90W, 100W, 150W, 200W, 250W, 300W, 350W, 400W, 450W, 500W, and any combination thereof.

[0067] The etching pressure can be 1-50 mTorr, for example, 1 mTorr, 2 mTorr, 3 mTorr, 4 mTorr, 5 mTorr, 6 mTorr, 7 mTorr, 8 mTorr, 9 mTorr, 10 mTorr, 12 mTorr, 14 mTorr, 16 mTorr, 18 mTorr, 20 mTorr, 22 mTorr, 24 mTorr, 26 mTorr, 28 mTorr, 30 mTorr, 32 mTorr, 34 mTorr, 36 mTorr, 38 mTorr, 40 mTorr, 42 mTorr, 44 mTorr, 46 mTorr, 48 mTorr, 50 mTorr, and any combination thereof.

[0068] The etching time can be 10-300 seconds, such as 10s, 20s, 30s, 40s, 50s, 60s, 70s, 80s, 90s, 100s, 110s, 120s, 130s, 140s, 150s, 160s, 170s, 180s, 190s, 200s, 210s, 220s, 230s, 240s, 250s, 260s, 270s, 280s, 290s, 300s, and any combination thereof.

[0069] The etching temperature is 5-35℃, for example, 5℃, 6℃, 7℃, 8℃, 9℃, 10℃, 11℃, 12℃, 13℃, 14℃, 15℃, 16℃, 17℃, 18℃, 19℃, 20℃, 21℃, 22℃, 23℃, 24℃, 25℃, 26℃, 27℃, 28℃, 29℃, 30℃, 31℃, 32℃, 33℃, 34℃, 35℃, and any combination thereof.

[0070] Unexpectedly, the semiconductor substrate etching method disclosed herein not only achieves a high etching selectivity, but also obtains a high aspect ratio and a vertical pattern transfer topology.

[0071] Evaluation method for photoresist etching resistance

[0072] When using photoresist as a mask to etch a substrate, not only the substrate is etched, but the photoresist is also inevitably etched. Etching of the photoresist is detrimental. Therefore, it is desirable to increase the etching rate of the substrate while decreasing the etching rate of the photoresist, that is, to improve etching selectivity. When measuring etching selectivity, it is necessary to determine the boundary between the photoresist and the substrate after etching, thereby measuring the thickness of the remaining photoresist and the depth of substrate etching. However, after the exposed substrate has been etched, the boundary between the photoresist and the substrate is often difficult to determine accurately, leading to inaccurate measured etching selectivity. To solve this problem, this disclosure creatively proposes a novel method for evaluating the etching resistance of photoresist.

[0073] The method for evaluating the etching resistance of photoresist disclosed herein includes providing an object layer to be etched. The object layer can be any etchable material. For example, the object layer can be a semiconductor substrate, such as one or more of silicon, silicon dioxide, and silicon nitride substrates.

[0074] The evaluation method further includes forming a photoresist pattern layer on the object layer. The photoresist pattern layer can be formed by any method known in the art. For example, methods for forming a photoresist pattern layer may include coating, exposure, development, etc., and may further include one or more steps such as pre-baking, post-baking, cleaning, and drying. The type of photoresist is not particularly limited; for example, it can be a positive or negative photoresist; it can be a chemically amplified photoresist, a metal-based photoresist, a block copolymer photoresist, etc. In some embodiments, the photoresist is a metal-based photoresist. In some embodiments, the metal-based photoresist is selected from metal oxide cluster photoresists, metal oxide nanoparticle photoresists, and metal-organic small molecule photoresists.

[0075] The evaluation method further includes masking at least a portion of the area of ​​the object layer not covered by photoresist to obtain a test sample. The masked portion of the object layer is not etched. The masking material is not particularly limited, as long as it can prevent the object layer from being etched. The masking material can be selected based on the etchant used. The masking material can be adhered to the area of ​​the object layer not covered by photoresist. The masking material can be self-adhesive or can be attached to the object layer using an adhesive. A masking material that is easily removable from the object layer after etching is advantageous. Preferably, a masking material that adheres firmly to the object layer, is easy to remove, and leaves no residue after removal. The masking material needs to withstand the etching environment without losing its protective function for the object layer. For example, the masking material can be an insulating material that is inert to the etchant. For example, the masking material can be insulating tape, such as 3M tape manufactured by 3M. There are no particular limitations on the size of the masked area; it can be selected based on the requirements of convenient measurement.

[0076] The evaluation method further includes etching the test sample. The evaluation method disclosed herein does not particularly limit the etching method; it can be dry etching or wet etching, such as ion beam sputtering etching, plasma etching, reactive ion etching, chemical etching, electrolytic etching, etc.

[0077] like Figure 1 As shown, the left image is a schematic diagram of the object layer partially covered by the photoresist patterning layer before etching. For ease of distinction, the diagonal striped areas in the image represent the top portion of the object layer that will be masked. Except for the top masking material, the diagonal striped area on the left and the gray area on the right are integral and both belong to the object layer. Before etching, the photoresist thickness is d1, which is the vertical distance between the top plane of the photoresist patterning layer and the bottom plane of the photoresist patterning layer before etching. The right image shows the situation after etching. To avoid interfering with observation, the masking material at the top of the diagonal striped area in the image has been removed. The Si substrate marked in the image is an example of the object layer material. The etching depth of the object layer is d2, which is the vertical distance between the top plane of the object layer at the masked area and the bottom plane formed after etching. To measure d2, the masking material can be removed, and then the distance from the top of the unetched portion of the object layer to the bottom of the etched trench can be measured along the unetched portion. Additionally, the trench depth d3 from the top of the photoresist to the bottom of the trench is measured. This is the vertical distance between the top plane of the photoresist patterned layer after etching and the bottom plane formed after the target layer is etched. d1, d2, and d3 can be measured, for example, using an atomic force microscope. The thickness of the photoresist that has been etched away can be obtained by calculating d1 + d2 - d3. The etching time is denoted as T, and the etching rates of the photoresist and the target layer can be obtained using equations (1) and (2), respectively:

[0078]

[0079] The etching selectivity S of the object layer relative to the photoresist can be calculated using the following formula:

[0080]

[0081] d1, d2, and d3 have the same unit, such as nm or The unit of T is min or s.

[0082] In existing methods, the entire exposed portion of the substrate is etched. Therefore, to measure the etching depth d2 of the target layer, the interface between the photoresist layer and the target layer must first be determined, which is very difficult to accurately determine. The method disclosed in this invention cleverly avoids the step of determining the interface and can accurately measure the etching depth d2 of the target layer. Therefore, the method of this invention is simple to operate and provides more accurate results than calculations.

[0083] As an example, in the semiconductor substrate etching method of this disclosure, the etching resistance of the metal-based photoresist can be evaluated using the evaluation method of this disclosure. For example, this exemplary evaluation method may include the following steps:

[0084] Provide semiconductor substrates;

[0085] Forming a metal-based photoresist pattern layer on a semiconductor substrate;

[0086] At least a portion of the area on the semiconductor substrate not covered by photoresist is masked to obtain a test sample;

[0087] The test sample is etched using a mixture of a first etching gas and a second etching gas.

[0088] Measure d1, d2, and d3;

[0089] The etching selectivity ratio of the semiconductor substrate relative to the metal-based photoresist is calculated using the above formula (3).

[0090] The first etching gas contains CF groups, and the second etching gas contains SF groups.

[0091] The first etching gas is selected from one or more of CH3F, CH2F2, CHF3 and CF4, and the second etching gas is selected from SF6.

[0092] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0093] In the semiconductor substrate etching method disclosed herein, the semiconductor substrate exhibits a selectivity for the photoresist of up to 9.0 or higher, vertical pattern transfer, and sidewall angles approaching 90°. Even with relatively small critical dimensions, the aspect ratio can reach 5, or even higher than 10. This superior etching performance, characterized by high selectivity, high aspect ratio, and vertical pattern transfer, contributes to achieving excellent device performance.

[0094] This disclosed method for evaluating the etch resistance of photoresist employs a masking material (such as insulating tape) to partially obscure the target layer (such as a semiconductor substrate) not covered by the photoresist (such as a metal-based photoresist). This allows for simple measurement and calculation of the etching rates of both the photoresist and the target layer, thereby enabling the calculation of the etch selectivity of the target layer relative to the photoresist. This method is simple to operate and provides accurate selectivity calculation results.

[0095] Example

[0096] The present invention will be described below by way of specific embodiments. It should be understood that these embodiments are merely illustrative and are not intended to limit the scope of the invention.

[0097] Unless otherwise specified, the equipment used in the following embodiments is conventional equipment in the art; unless otherwise specified, the reagents used are commercially available products or prepared by conventional methods in the art. In the following embodiments, unless otherwise described in detail, conventional experimental methods in the art can be used.

[0098] Example 1

[0099] A 43nm thick photoresist film was spin-coated onto a silicon wafer (cut size: 10mm*10mm (UV+Ring), thickness: 525±15μm, manufactured by Saichi Electronics) using a tin-oxygen cluster photoresist and a spin coater (Laurell, USA, model: WS-650Mz-23NPPB). After EBL (electron beam) exposure and ethyl acetate (Sinopharm Group) development, a photoresist pattern layer was formed on the silicon wafer. 3M 7413D brown insulating tape (a polyimide film) from 3M was used to mask a portion of the silicon wafer not covered by the photoresist (e.g., ...). Figure 2 (as shown in (a)). The silicon wafer was etched using a mixed etching gas of CHF3 and SF6 in an inductively coupled plasma (ICP) chamber (Oxford UK Plasma pro ICP180 plasma etching machine). Specific etching conditions are shown in Table 1.

[0100] Table 1 Etching conditions

[0101]

[0102] Before etching, the thickness of the unetched photoresist was characterized using AFM, and the results are as follows: Figure 2 As shown in (b), the thickness d1 of the metal-based photoresist was thus obtained as 29.0 nm. After etching for 60 s, the trench depth d3 was characterized using AFM, and the results are as follows. Figure 2 As shown in (c), d3 = 183.6 nm was thus obtained. After etching, AFM was used to characterize the height difference between the portion of the silicon wafer covered by 3M tape and the portion not covered, and the results are as follows. Figure 2 As shown in (d), the etch depth of the silicon wafer was d2 = 174.0 nm. AFM results indicate that after 60 s of etching, the 1 μm stripe etch trench depth (from the top of the etched photoresist to the bottom of the trench) is d3 = 183.6 nm, and the silicon wafer recess depth (i.e., the etch depth of the silicon wafer) is d2 = 174.0 nm. Combined with the photoresist thickness before etching, d1 = 29.0 nm, the photoresist etching rate can be calculated as follows: The etching rate of the silicon wafer is The etching selectivity ratio for the two is 9.1.

[0103] In addition, SEM characterization was performed on the silicon wafer with photoresist patterns after etching. Figure 3 (a) is a SEM cross-sectional image, showing that the etched pattern morphology is vertically transmitted and the sidewall angle is close to 90°. From this image, we can obtain the pitch HP = 25nm, and calculate the aspect ratio AR = 137.5 ÷ 22.18 = 6.2.

[0104] It should be noted that the semiconductor substrate etching method of this disclosure does not require masking a portion of the silicon wafer not covered by photoresist. In this embodiment, to illustrate the high etching selectivity resulting from the semiconductor substrate etching method of this disclosure, tests were conducted using the photoresist etching resistance evaluation method of this disclosure. Therefore, a portion of the silicon wafer not covered by photoresist was masked before etching. In other words, this embodiment simultaneously demonstrates both the semiconductor substrate etching method and the photoresist etching resistance evaluation method of this disclosure.

[0105] Example 2

[0106] The silicon wafer was etched according to the method in Example 1, except that the etching time was 90 s. The etched silicon wafer was then characterized by SEM. Figure 3 (b) is a SEM cross-sectional view, showing that the etched pattern morphology is vertically transmitted and the sidewall angle is close to 90°. From this image, we can obtain the pitch HP = 30nm, and calculate the aspect ratio AR = 237.1 / 21.95 = 10.8.

[0107] This disclosure uses insulating tape to cover a portion of the semiconductor substrate not covered by the photoresist pattern layer, creating a height difference between the etched and unetched areas of the semiconductor substrate. This allows for the simultaneous determination of the etching depth and pattern trench depth of the semiconductor substrate on a single substrate, enabling the calculation of the semiconductor substrate etching rate and the metal-based photoresist etching rate. Furthermore, it allows for the determination of the photoresist's etch selectivity relative to the silicon substrate. This method facilitates the convenient measurement and calculation of the semiconductor substrate's selectivity relative to the metal-based photoresist, achieving results exceeding 9.0.

[0108] Furthermore, the etching method for semiconductor substrates disclosed herein produces etched patterns with vertical transfer and sidewall angles approaching 90°. With smaller critical dimensions, the aspect ratio can reach 5, or even higher than 10.

[0109] The specific embodiments of this disclosure have been described above. The scope of protection of this disclosure is not limited to the exemplary embodiments described above. Any modifications, equivalent substitutions, or improvements made by those skilled in the art within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for etching a semiconductor substrate, the method comprising: Provides a semiconductor substrate partially covered by a metal-based photoresist patterning layer; A semiconductor substrate partially covered by a metal-based photoresist pattern layer is etched using a mixed gas containing a first etching gas and a second etching gas. The first etching gas contains CF groups, and the second etching gas contains SF groups.

2. The method according to claim 1, characterized in that, The metal-based photoresist is selected from metal oxide cluster photoresist, metal oxide nanoparticle photoresist, and metal-organic small molecule photoresist.

3. The method according to claim 1, characterized in that, The first etching gas is selected from one or more of CH3F, CH2F2, CHF3 and CF4, preferably CHF3; and / or The second etching gas is selected from SF6.

4. The method according to claim 1, characterized in that, The semiconductor substrate is selected from silicon substrates.

5. The method according to claim 1, characterized in that, The etching is performed within a plasma chamber, and the etching conditions satisfy one or more of the following: The first etching gas flow rate is 10-100 sccm; The second etching gas flow rate is 2-20 sccm; Etching power is 10-500W; The etching pressure is 1-50 mTorr; Etching time is 10s-300s; The etching temperature is 5-35℃.

6. A method for evaluating the etching resistance of photoresist, the method comprising: Provide an object layer; A photoresist pattern layer is formed on the object layer; By masking at least a portion of the area on the object layer that is not covered by photoresist, a test sample is obtained. The test sample was etched; Calculate the etching selectivity using the following formula: Where S represents the etching selectivity, d1 represents the vertical distance between the top plane of the photoresist pattern layer before etching and the bottom plane of the photoresist pattern layer, d2 represents the vertical distance between the top plane of the target layer at the masked area after etching and the bottom plane formed after etching, and d3 represents the vertical distance between the top plane of the photoresist pattern layer after etching and the bottom plane formed after etching. d1, d2, and d3 have the same unit. The parts of the object layer that are hidden are not etched.

7. The method according to claim 6, characterized in that, The target layer is a semiconductor substrate, preferably selected from silicon substrates; and / or The photoresist is a metal-based photoresist. Preferably, the metal-based photoresist is selected from metal oxide cluster photoresist, metal oxide nanoparticle photoresist, and metal-organic small molecule photoresist.

8. The method according to claim 6, characterized in that, At least a portion of the area on the object layer not covered by photoresist is covered with an insulating material that is inert to the etchant, preferably insulating tape.

9. The method according to claim 6, characterized in that, Etching is performed using a mixture of a first etching gas and a second etching gas. Preferably, the first etching gas is selected from one or more of CH3F, CH2F2, CHF3 and CF4, with CHF3 being the most preferred; and / or the second etching gas is selected from SF6.

10. The method according to claim 6, characterized in that, d1, d2 and d3 were measured using an atomic force microscope.

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