A Glass Core multi-chip packaging method and packaging structure

Abstract

The application discloses a Glass Core multi-chip package method and package structure. The glass core layer is used as the core carrier of the package, laser-induced modification is performed in the glass core layer, then a through-hole and a blind hole structure are sequentially formed by combining a phased wet etching process, crack sealing passivation treatment is introduced after the laser modification, the expansion of the glass micro-cracks in the etching process is effectively inhibited, the through-hole is subjected to metallization treatment to build vertical electrical interconnection, redistribution layers are respectively built on the front and back sides of the glass core layer, independent processing and collaborative interconnection of the front and back sides are realized, multiple chips are bonded in the blind hole and on the back side of the glass core layer in stages, and gap filling, molding and grinding processes are combined, and finally, a multi-chip package structure with complete structure and reliable electrical interconnection is obtained. The application realizes controllable coexistence of the through-hole and the blind hole and collaborative interconnection of the front and back sides, and is suitable for high-density multi-chip package applications.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging, and particularly relates to a Glass Core multi-chip packaging method and packaging structure. Background Technology

[0002] As advanced packaging technologies continue to develop towards higher integration and multi-chip collaboration, traditional packaging solutions based on organic substrates or silicon interposers can meet the needs of early single-chip or low-density packaging applications. However, as the number of chips increases, interconnect density improves, and package size shrinks further, their shortcomings in terms of dimensional stability, thermomechanical reliability, processing accuracy, and long-term service consistency become increasingly apparent.

[0003] On the one hand, existing organic substrate materials generally suffer from a large coefficient of thermal expansion and are significantly affected by temperature changes. In multi-chip packaging and multi-layer redistribution structures, organic substrates are prone to warping, interlayer stress concentration, and solder joint fatigue during repeated thermal cycling, thus affecting packaging yield and reliability. Especially in complex packages that integrate multiple functional chips and have multi-layer interconnect structures, substrate warping and dimensional drift significantly increase the difficulty of chip mounting and alignment, limiting further improvements in packaging accuracy. On the other hand, while silicon interposers have advantages in dimensional stability and processing accuracy, their material cost is high, the processing flow is complex, and there are significant limitations in large-size or high-yield mass production. In addition, silicon itself has a certain degree of conductivity, requiring additional isolation and design methods in high-frequency and high-speed signal applications, further increasing the complexity of the packaging structure and manufacturing cost.

[0004] Glass, due to its excellent flatness, low coefficient of thermal expansion, good dimensional stability, and natural electrical insulation properties, is increasingly considered a promising interlayer material. However, glass as an encapsulation carrier still faces many technical bottlenecks in practical applications, especially in the construction of hole structures and multi-process collaborative processing. In existing technologies, glass through-holes and blind holes are typically formed using mechanical drilling, direct laser drilling, or single wet etching. These methods either cause significant mechanical or thermal shock to the glass, easily introducing cracks and edge chipping, or they are insufficient in terms of hole shape control and depth consistency, making it difficult to simultaneously and stably form through-hole and non-through-hole structures in the same glass core layer. A more prominent problem is that when it is necessary to form through-hole and blind hole structures simultaneously in the same glass core layer, existing processes often lack effective process isolation methods. Through-holes and blind holes are prone to mutual interference during etching or processing, leading to defects such as premature penetration of blind holes, uncontrolled hole depth, or lateral erosion of the hole opening. In addition, laser processing or etching inevitably introduces microcracks and defects into the glass. These defects often become the preferred growth channels for the corrosive medium in subsequent wet etching steps, further amplifying the non-uniformity of the pore shape and reducing the overall pore yield.

[0005] Furthermore, as multi-chip packaging gradually moves towards three-dimensionality and heterogeneous integration, the packaging structure often needs to integrate different functional chips on both sides of the glass core layer, and achieve complex electrical connections through vias and redistribution layers. Existing technologies lack mature system solutions for multi-chip integration sequence, front and back interconnection coordination, and overall stress management, resulting in narrow process windows and large yield fluctuations during the manufacturing process of the packaging structure, making it difficult to meet the reliability and consistency requirements of high-end applications. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a Glass Core multi-core packaging method and packaging structure.

[0007] Specifically, the technical solution provided by this invention is as follows:

[0008] A Glass Core multi-chip packaging method includes the following steps:

[0009] Laser-induced modification of the glass core layer is performed to form easily corroded through-hole modification regions and blind-hole modification regions;

[0010] Through-holes penetrating the glass core layer are generated in the through-hole modification region by wet etching and then metallized.

[0011] Blind holes extending from the upper surface of the glass core to a set depth are generated in the blind hole modification area by wet etching.

[0012] Several internal chips are embedded in blind vias, and a front metal wiring layer is constructed on the upper surface of the glass core layer; the front metal wiring layer is electrically connected to the internal chips and the metallized vias, and at the same time provides external interconnection points.

[0013] The glass core layer is flipped to form a back metal wiring layer on its lower surface, which is electrically connected to the metallized vias and provides external interconnection points.

[0014] Several external chips are bonded to the outside of the back metal wiring layer, and the external chips are electrically connected to the back metal wiring layer through external interconnection points.

[0015] The gaps between the external chip and the glass core layer and its back metal wiring layer are filled and cured, and then molded and polished to form a robust and reliable multi-core package structure.

[0016] The outer interconnection points of the front metal wiring layer are also constructed with a ball grid array to realize the electrical connection and signal interaction between the multi-core package structure and the external circuit.

[0017] Furthermore, after laser-induced denaturation and before wet etching, the glass core layer undergoes crack sealing and passivation treatment, including the following steps:

[0018] S1. Clean the surface of the glass core layer to remove debris and redeposit generated during the laser modification process;

[0019] S2. Prepare a compressive stress sealing film on the surface of the glass core layer to bridge and seal microcracks in the modified area;

[0020] S3. Hydrate and passivate the glass core layer to suppress the ability of microcracks to guide the propagation of corrosive media.

[0021] Further, step S1 includes:

[0022] The glass core layer was ultrasonically cleaned in deionized water for 2 minutes, then transferred to anhydrous ethanol and ultrasonically cleaned for 1 minute to replace the water and remove fine particles. After removal, the surface was dried with nitrogen. If there is concern about organic contamination, isopropanol was added after ultrasonic cleaning and rinsed for 30 seconds before drying. Finally, it was pre-baked on a hot plate at 120°C for 3 minutes to remove adsorbed water.

[0023] Further, step S2 includes:

[0024] Inorganic silica sol is dropped onto the surface of a glass core layer and spin-coated to form a uniform film. Immediately after spin-coating, the film is softened to allow the sol to undergo further condensation and form a dense silica network. The softening process includes a first stage and a second stage: in the first stage, the glass core layer is placed horizontally on a hot plate preheated to 80°C for 2 minutes to remove low-boiling-point solvents from the film; in the second stage, the glass core layer is placed horizontally on a hot plate preheated to 150°C for 5 minutes to promote the condensation reaction of the sol.

[0025] Further, step S3 includes:

[0026] Place the glass core layer in a water vapor environment at 70-85℃ for 3-8 minutes to allow slight hydration of the microcrack tips, which blunts the tips and reduces the tendency for subsequent corrosion to propagate rapidly along the cracks; or immerse the glass core layer in deionized water at 60-70℃ for 1-3 minutes and then remove it and blow it dry with nitrogen; finally, pre-bake it on a hot plate at 120℃ for 2 minutes to remove the surface water film.

[0027] Furthermore, before generating vias by wet etching, a layer of photoresist is first uniformly coated on the surface of the glass core layer to form a continuous cover film. Then, exposure and development are performed according to the pre-designed photolithography pattern, so that the photoresist forms a patterned structure with a set distribution on the surface of the glass core layer. The photoresist is selectively retained and covers the surface position of the corresponding blind hole modification area, while the via modification area is exposed.

[0028] Furthermore, the metallization includes: forming a continuous metal seed layer on the inner wall of the via through by physical vapor deposition, and then thickening the metal layer by electroplating to obtain a via conductor that meets electrical performance requirements; or forming a thin metal layer on the inner wall of the via through by atomic layer deposition, and then thickening the metal layer by electroplating to improve conductivity; or growing a metal layer in situ on the inner wall of the via through by chemical copper plating, so that a continuous metal conductive path is formed inside the via.

[0029] Furthermore, before generating blind vias through wet etching, the photoresist covering the blind via modification area is first removed, and the glass core layer is temporarily fixed to the surface of the first carrier plate used as a support. Then, a layer of photoresist is uniformly coated on the surface of the glass core layer to form a continuous cover film. Subsequently, exposure and development are performed according to the pre-designed photolithography pattern, so that the photoresist forms a patterned structure with a set distribution on the surface of the glass core layer. The photoresist is selectively retained to cover the surface position of the corresponding via, while the blind via modification area is exposed. Finally, after the blind vias are generated through wet etching, the photoresist covering the vias is removed.

[0030] Furthermore, after embedding the internal chip in the blind hole and completing the construction of the front metal wiring layer, the glass core layer is flipped and temporarily fixed to the second carrier board used as a support through the front metal wiring layer, while the first carrier board is removed; the second carrier board is removed after completing the molding and grinding to form a structurally stable multi-core package structure.

[0031] A multi-chip package structure constructed by the above method includes a glass core layer and a front metal wiring layer and a back metal wiring layer respectively constructed on the upper and lower surfaces of the glass core layer; the glass core layer has a plurality of through holes and blind holes, the through holes are conductive after being metallized, and a plurality of internal chips are embedded in the blind holes; the front metal wiring layer is electrically connected to the internal chips and the metallized through holes, and provides external interconnection points, the external interconnection points being provided with ball grid arrays for connecting external circuits; the back metal wiring layer is electrically connected to the metallized through holes, and a plurality of external chips are bonded to the outside of the back metal wiring layer, the external chips being electrically connected to the back metal wiring layer.

[0032] Compared with the prior art, the present invention has at least the following beneficial effects:

[0033] This invention uses a glass core layer as the core carrier and systematically designs the glass material from the initial stage of the process, focusing on its advantages in dimensional stability, electrical insulation and flatness. This makes the glass no longer just a passive load-bearing structure, but a functional interposer for through holes, blind holes, electrical interconnects and multi-chip integration. It fundamentally improves the problems of traditional organic substrates, such as easy warping and insufficient thermal stability, as well as the high cost and process limitations of silicon interposers.

[0034] At the pore structure construction level, this invention achieves precise differentiation and independent control of through-holes and blind holes within the same glass core layer through laser-induced modification and staged wet etching. Through-holes and blind holes are not formed by a single drilling or uniform etching process, but rather by pre-defining modified regions of different depths and continuity within the glass using lasers, followed by photolithography protection and selective etching to gradually release the structure. This approach significantly reduces dependence on the etching conditions themselves, making the penetration, depth, and morphology of the pores primarily determined by the preceding laser modification. This effectively improves the consistency and repeatability of the pore structure, avoiding common problems in existing technologies such as uncontrolled pore diameter, accidental penetration of blind holes, and lateral etching.

[0035] To address the technical challenge of microcracks easily forming in glass materials after laser processing and being further amplified during wet corrosion, this invention introduces a crack sealing and passivation treatment after laser-induced denaturation. Through cleaning, low-temperature film formation, and slight hydration, potential cracks are actively sealed and passivated, significantly suppressing the rapid propagation of corrosive media along the cracks. This improves the stability and overall yield of through-hole and blind-hole forming processes without adding complex equipment or additional structures.

[0036] In terms of electrical interconnection and multi-chip integration, this invention achieves a process path where the front and back sides are processed independently yet collaboratively by first completing the via metallization, then constructing the redistribution layers on both sides in stages, and coordinating with multiple temporary bonding and debonding processes on the carrier board. This process effectively avoids the risks of warping and structural damage caused by directly flipping or processing the back side when the glass's self-supporting capacity is insufficient, enabling multi-layer redistribution and multi-chip mounting to be completed in a controlled and flat state. Simultaneously, the reliable connection of the redistribution layers on the upper and lower surfaces through vias makes the electrical connection paths between chips more flexible, providing greater freedom for heterogeneous chip integration and complex interconnection designs.

[0037] Regarding the overall reliability of multi-chip packaging, this invention utilizes a rational chip introduction sequence, a top and bottom surface separation processing strategy, and final gap filling and overall molding treatment to enable multiple chips to form a uniformly stressed and structurally continuous package within a glass core layer. Compared to existing technologies that simply stack multiple chips or provide localized reinforcement, this approach is more conducive to stress dispersion under thermal cycling and mechanical loads, reducing the risk of solder joint fatigue and interface failure, thereby significantly improving the long-term stability and lifespan of the packaged device. Attached Figure Description

[0038] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0039] Figure 1 This is a framework diagram of the multi-core packaging method provided in the embodiments of the present invention;

[0040] Figure 2 This is a schematic flowchart of the multi-core packaging method provided in the embodiments of the present invention. Figure 1 ;

[0041] Figure 3 This is a schematic flowchart of the multi-core packaging method provided in the embodiments of the present invention. Figure 2 . Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, other embodiments obtained by those skilled in the art without creative effort are all within the scope of protection of the present invention.

[0043] Example 1

[0044] like Figures 1-3 As shown, this embodiment provides a Glass Core multi-chip packaging method, which mainly includes the following steps:

[0045] 1. Determine the glass core layer

[0046] First, the Glass Core is determined. This glass core layer serves as the foundational carrier of the entire multi-chip package structure, and it is identified from the initial stages of the process as the main support for all subsequent structural construction and process implementation. At this point, the Glass Core has not yet formed vias or blind vias, nor has it undergone any metallization; it remains a single, continuous piece of glass material. The reason for using the glass core layer as the core carrier is that glass itself possesses characteristics such as high flatness, good dimensional stability, and resistance to warping, making it very suitable as an intermediary layer in multi-chip packaging.

[0047] 2. Laser-induced denaturation

[0048] Then, the glass core layer undergoes laser-induced modification treatment, a crucial preliminary step in the subsequent through-hole and blind-hole formation process. In this embodiment, instead of directly drilling or etching holes in the glass, a laser is first used for pretreatment inside the glass. During this process, by adjusting the focal length and depth of the laser, the laser energy is concentrated on different depth regions of the glass core layer, thereby forming modified zones with altered properties within the glass. These modified zones maintain the appearance of a complete glass structure, but their internal material properties have changed, making them more easily selectively removed during subsequent wet etching.

[0049] Through laser-induced modification, this embodiment selectively forms two different types of laser-modified regions within the same glass core layer. One type corresponds to the through-hole region that needs to penetrate the glass core layer later, while the other type corresponds to the blind hole region formed only within a portion of the glass thickness. The through-hole modified regions are typically distributed continuously along the glass thickness direction, providing conditions for the formation of subsequent through-hole structures; while the blind hole modified regions are limited to a local depth range of the glass core layer, used to form blind hole structures that do not penetrate the glass in subsequent processes.

[0050] After laser-induced modification, submicron to micron-sized microcracks or defects may exist around the modified area. If wet etching is performed directly at this point, the etching solution will preferentially enter the crack tip and accelerate its propagation along the crack, causing problems such as orifice enlargement, side etching of the hole wall, and accidental penetration of blind holes. Therefore, in this embodiment, wet etching is not performed immediately after laser modification, but crack sealing treatment is performed first to close or passivate any potential microcracks.

[0051] First, perform a rapid surface cleaning to remove debris and redeposit. Place the glass core layer in deionized water and sonicate for 2 minutes (frequency approximately 40 kHz; power should not be too high to avoid secondary propagation of microcracks). Then, transfer it to anhydrous ethanol and sonicate for 1 minute to displace moisture and remove fine particles. After removal, dry the surface with nitrogen gas, maintaining a distance of 10-20 cm between the nozzle and the surface to prevent high-speed airflow from causing contamination at the pores or modified areas. If concerned about organic contamination, additional IPA (isopropanol) can be added after sonication in ethanol for 30 seconds before drying. After cleaning, it is recommended to pre-bake on a 120°C hot plate for 3 minutes to remove adsorbed water, resulting in more uniform film formation.

[0052] Subsequently, the compressive stress sealing film was prepared. Inorganic silica sol was dropped onto the surface of the glass core layer, first spin-coated at 500 rpm for 5 seconds to spread the sol, then spin-coated at 3000 rpm for 30 seconds to form a uniform film. Immediately after spin-coating, the film underwent soft baking: 80℃ for 2 minutes + 150℃ for 5 minutes, allowing the sol to further condense and form a dense silica network. This temperature is considered a low-temperature process, generally not introducing new high thermal stress, while significantly improving the film's density and adhesion. For stronger sealing, a curing period of 200℃ for 10 minutes can be added, but 150℃ is usually sufficient.

[0053] The recommended inorganic silica sol is prepared using TEOS (tetraethyl orthosilicate) as the silicon source, ethanol as the solvent, deionized water as the hydrolysate, and hydrochloric acid as the catalyst. For example, to prepare 100 mL: 20 mL TEOS, 60 mL anhydrous ethanol, 18 mL deionized water, and 2 mL 0.1 mol / L hydrochloric acid. After thoroughly mixing the TEOS and ethanol, slowly add the mixture of deionized water and hydrochloric acid. Stir magnetically at room temperature (20-25°C) for 30 min, then allow to stand for 1-2 h to age and obtain a stable sol. This formulation typically forms a film thickness of approximately 80-200 nm (depending on spin coating speed), sufficient to cover and bridge microcrack openings without being too thick to affect subsequent photoresist coating. If a sol preparation is not desired, commercially available inorganic silica coatings can be used instead, such as low-temperature curable silica network precursors, commonly found in glass protective coating systems.

[0054] After the film has cured, a slight hydration passivation process is performed. The glass core layer is placed in a water vapor environment at 70-85℃ for 3-8 minutes to induce slight hydration at the crack tip, blunting the tip and reducing the tendency for subsequent corrosion to propagate rapidly along the crack. If a steam chamber is unavailable, warm water immersion can be used as an alternative: immerse the glass core layer in deionized water at 60-70℃ for 1-3 minutes, then remove it and dry it with nitrogen, followed by pre-baking at 120℃ for 2 minutes to remove the surface water film.

[0055] 3. PR coating + exposure + development

[0056] After laser-induced modification, photoresist coating, exposure, and development are performed on the glass core layer surface to clearly distinguish and protect areas for subsequent processing. In this step, a layer of photoresist is first uniformly coated onto the surface of the glass core layer to form a continuous cover film. Then, exposure and development are performed according to a pre-designed photomask pattern, causing the photoresist to form a specifically distributed patterned structure on the glass surface. The photoresist is selectively retained at the surface positions corresponding to the laser-modified blind hole areas, thus completely covering those areas.

[0057] Through the above treatment, the laser-modified areas corresponding to blind vias are effectively masked by photoresist on the glass surface, while the modified areas corresponding to through-holes are exposed. At this point, although the laser modification of both through-holes and blind vias is completed inside the glass, the photoresist clearly distinguishes them in the process. The modified areas of blind vias covered by photoresist will not directly participate in the reaction or processing in subsequent through-hole related processes, thus remaining protected and preventing premature release or damage during the through-hole processing stage.

[0058] 4. Wet corrosion of through-holes

[0059] Because the laser-modified areas corresponding to blind holes are covered with photoresist, while the laser-modified areas corresponding to through holes are completely exposed, the wet etching process only acts on the through-hole modified areas. The etching solution uses a wet etching system suitable for glass materials, such as an etching solution based on hydrofluoric acid or a fluorine-buffered etching solution. The specific composition, concentration, and temperature of the etching solution can be set according to the glass material and thickness. During the wet etching process, the glass core layer is placed in the appropriate etching environment, and the etching medium preferentially acts on the laser-modified glass areas corresponding to the through holes. Since laser-induced denaturation has altered the local structure and chemical stability of the glass in this area, making it more susceptible to etching than unmodified glass, the etching reaction gradually advances along the distribution path of the through-hole modified areas towards the glass thickness. As the etching time continues, the glass material in the through-hole areas is continuously removed, eventually forming a through-hole structure penetrating both the upper and lower surfaces of the glass core layer.

[0060] 5. Through-hole metallization

[0061] After wet etching of the vias, a via structure actually penetrating the upper and lower surfaces has been formed in the glass core layer. These vias are geometrically complete, but at this point they are still just glass channels and do not have any conductive function. In order for these vias to be able to undertake the vertical electrical interconnection between chips and between chips and redistribution layers, metallization is required to construct a conductive structure for the vias.

[0062] Through-hole metallization targets the corroded inner wall and surrounding area of ​​the through-hole. By introducing metal material into the through-hole, the original glass channel is transformed into a metallized through-hole structure with stable conductivity. Different metallization techniques can be selected to achieve conductivity through-holes, depending on process conditions, equipment capabilities, and product requirements. For example, a continuous metal seed layer can be formed on the inner wall of the through-hole using physical vapor deposition, followed by electroplating to thicken the metal layer, thereby obtaining a through-hole conductor that meets electrical performance requirements. Alternatively, atomic layer deposition can be used to form a thin metal layer with better coverage and higher density on the inner wall of the through-hole, followed by electroplating to enhance conductivity. Or, methods such as chemical copper plating can be used to grow a metal layer in situ on the inner wall of the through-hole, creating a continuous metal conductive path inside the through-hole.

[0063] 6. PR glue removal

[0064] Remove the PR photoresist used in the preceding process to cover the blind via modification area.

[0065] Throughout the previous process stages, the photoresist played a crucial protective role, preventing the laser-modified areas corresponding to the blind vias from being corroded or covered by metal during the via formation and metallization processes, thus ensuring a strict distinction between the vias and blind vias in the structural formation sequence. Once the via structure is complete and possesses stable conductivity, retaining the photoresist is no longer necessary. After removing the PR resist, the surface of the glass core layer is no longer covered by photoresist, and the previously protected laser-modified areas of the blind vias are re-exposed, restoring the entire glass core layer surface to a state suitable for further processing and patterning.

[0066] 7. Bonding the first carrier board

[0067] In this process, the glass core layer is temporarily fixed to the surface of the first carrier board, ensuring that the glass core layer remains in a controlled and flat state throughout the subsequent processing. The carrier board itself does not participate in the final composition of the packaging structure; its main function is to serve as a process carrier, providing the necessary strength and support for the glass core layer before further patterning, blind via release, and chip mounting.

[0068] 8. PR coating + exposure + development

[0069] At this point, the vias have been formed and metallized within the glass core layer, and their structure and function are determined. Therefore, they need to be carefully protected in subsequent processes to prevent them from being affected during blind via processing. Specifically, by uniformly coating photoresist on the surface of the glass core layer and exposing and developing it according to a pre-set pattern, a continuous cover layer of photoresist is formed on the surface corresponding to the vias, while the laser-modified areas corresponding to the blind vias are intentionally exposed. In this way, the surface state of the glass core layer is clearly divided into two parts: the protected area for vias and the area to be processed for blind vias.

[0070] 9. Blind hole wet corrosion

[0071] In the blind-hole wet etching process, the glass core layer is placed in a suitable corrosive environment, and the corrosive medium preferentially acts on the laser-modified region corresponding to the blind hole. Since the glass material in this region has already undergone structural and chemical stability changes during the laser-induced modification step, its corrosion resistance is significantly lower than that of unmodified glass. Therefore, the corrosion reaction gradually propagates inward from the glass surface along a pre-set modification depth. As the etching process proceeds, the glass material within the blind-hole modification region is gradually removed, but the corrosion depth is limited by the laser modification range and does not penetrate the entire glass core layer. This results in a blind-hole structure with a certain depth within the glass core layer, which does not extend through the upper and lower surfaces.

[0072] 10. PR glue removal

[0073] Remove the photoresist formed in the previous process to protect the via area.

[0074] By performing a photoresist removal process, the photoresist covering the surface of the via area is completely removed, exposing the surface of the glass core layer again. This process does not change the geometry of the formed vias or blind holes, nor does it damage the metallization structure inside the vias. Its main purpose is to restore the overall open state of the glass core layer surface, so that the via area, blind hole area, and glass substrate surface are simultaneously in a state that can participate in subsequent processes.

[0075] 11. Bonding the first chip

[0076] After completing the construction of all vias and blind vias and removing the photoresist, the glass core layer possesses a complete via structure and electrical interconnect foundation. At this point, the process flow officially enters the chip integration stage. The first chip introduced is Die1. In this embodiment, Die1 is fixed into the blind vias of the glass core layer, ensuring stable integration into the glass core layer multi-chip package structure. Through a predetermined bonding method, Die1 is reliably bonded to the glass core layer, so that the chip is no longer in a temporary mechanical placement state but becomes a fixed component of the package structure. With the completion of bonding, the position of Die1 is precisely locked, and its spatial relationship relative to the via structure and the glass core layer is determined, thus providing a stable geometric reference for subsequent interconnect construction.

[0077] This bonding step establishes a reliable interface connection between Die1 and the glass core layer, enabling the chip to withstand the thermal and mechanical forces introduced by subsequent redistribution layer fabrication, substrate switching, and further packaging steps. Simultaneously, the active surfaces or pad areas of Die1 are accurately exposed and positioned at this stage, providing a direct connection foundation for building the Top RDL on top of it.

[0078] 12. TOP RDL

[0079] After the Die1 bonding is completed, the construction phase of the Top Redistribution Layer (Top RDL) begins. At this point, the Die1 is stably fixed on the Glass Core, and its positional relationship, orientation, and spatial correspondence with the via structures are all determined. Therefore, the formation of the top interconnect structure can be carried out on this basis. The Top RDL is one or more layers of metal wiring structures built on the top surface of the Glass Core. Its main function is to realize the electrical connection between the Die1 and the via structures in the Glass Core, while providing pads, traces, and interconnect interfaces for subsequent packaging structures.

[0080] During the formation of the Top RDL, the redistribution layer is designed and fabricated around the already bonded Die1, allowing the electrode pads of the Die1 to be re-exposed via metal wiring and precisely aligned with the vias inside the glass core layer. In this way, the fine-pitch pads originally located on the chip surface are transformed into wiring and pad layouts suitable for packaging and multi-layer interconnect requirements, thereby significantly improving the flexibility of interconnect design.

[0081] 13. Bonding the second carrier board

[0082] After the top surface redistribution layer is constructed, the overall structure, which already includes the glass core layer, via and blind via structures, the bonded first chip Die1, and the Top RDL, is temporarily bonded to the second carrier board on the Top RDL side. This ensures that the side containing Die1 and Top RDL is effectively protected in subsequent processes. At this point, the packaging structure has gradually transitioned from the glass structure processing stage to the multi-chip integration stage, with increased overall thickness and structural complexity. If flipping or back-side processing is performed directly, problems such as warping, displacement, or stress concentration may easily occur due to insufficient self-supporting capacity of the structure. Therefore, the introduction of the second carrier board at this stage is to provide new and reliable mechanical support for the entire package before the carrier board switching and back-side processing.

[0083] 14. Debonding of the first carrier board

[0084] The first carrier is separated and removed from the Glass Core structure. The glass core layer no longer relies on the first carrier for support; instead, the second carrier fully assumes the load-bearing function required for subsequent processes. Since the bonding of the second carrier is completed before the first carrier is debonded, the glass core layer and the chips and interconnect structures above it will not be suspended, bent, or damaged due to uneven local stress. Through this step, the stage where the upper surface of the glass core layer was the main processing surface has ended. Subsequent processes will focus on the back side of the glass core layer, entering the stage of back redistribution layer construction and further multi-chip integration.

[0085] 15. BackSide RDL

[0086] After the first carrier plate is debonded and the second carrier plate provides stable support for the overall structure, the construction phase of the backside redistribution layer (RDL) begins. At this point, the back side of the glass core layer is fully exposed and becomes the main operating surface for subsequent processing. The through-hole structure inside the glass core layer has been metallized in the previous process and spatially connected to the upper and lower surfaces, providing a direct electrical connection basis for the formation of the backside redistribution layer.

[0087] In this stage, a Backside Rewiring Layer (RDL) is constructed by sequentially forming a dielectric layer and a metal wiring structure on the back side of the glass core layer. This allows the vias inside the glass core layer to be re-exposed and rearranged on the back side. The purpose of the Backside RDL is to electrically connect and layout-match the positions of the vias on the back side with the subsequent chip mounting areas, thereby transforming the vertical interconnects, which were originally limited by the via positions, into a planar wiring structure with greater design freedom. Through the backside redistribution layer, signal, power, or ground paths can be guided to suitable locations for subsequent chip mounting and interconnection, according to the package design requirements, without being limited by the original distribution of vias in the glass core layer.

[0088] After the Backside RDL is completed, the back side of the glass core layer has a complete electrical interconnect network and chip support conditions, providing a direct electrical connection interface and structural foundation for the subsequent mounting and bonding of the second and third chips. It also enables the entire multi-chip package structure to have an independent and collaborative rewiring system in both the top and bottom directions.

[0089] 16. Multi-chip bonding

[0090] After the backside redistribution layer is constructed, this embodiment performs the introduction and bonding process of the second chip Die2 and the third chip Die3. Die2 and Die3 are placed on the corresponding areas on the back side of the glass core layer according to the predetermined package design positions and are precisely aligned with the Backside RDL.

[0091] During the introduction of Die2 and Die3, the two chips can be arranged side-by-side or relatively independently on the back of the glass core layer, depending on packaging requirements. Functionally, they can complement or synergize with the aforementioned Die1. After alignment, Die2 and Die3 are fixed to the back of the glass core layer using appropriate bonding processes, thus ensuring their stable mechanical integration into the entire packaging system.

[0092] Once bonding is complete, Die2 and Die3 are no longer simply independent chips attached to the back surface, but become functional units tightly integrated with the Backside RDL and electrical interconnect structure. Their electrodes can be further connected to the via structure through the backside redistribution layer, and establish an electrical connection with Die1 in the blind via of the glass core layer.

[0093] 17. Gap filling

[0094] After bonding Die2 and Die3, an underfill process is performed to fill and cure the gaps between the backside chip and the glass core layer and its backside redistribution layer. At this point, Die2 and Die3 are fixed to the backside of the glass core layer by bonding, and there are inevitably tiny gaps between the chip body and the Backside RDL. If these gaps remain unfilled for a long time, they can easily lead to solder joint fatigue, interface cracking, or decreased chip reliability under subsequent thermal cycling or mechanical stress. Therefore, the underfill process is needed to completely fill this area.

[0095] During the underfill process, the filler material is introduced between Die2, Die3, and the back of the glass core layer, allowing it to flow gradually along the bottom of the chip and fully fill the gaps between the chip and the redistribution layer. As the filler material spreads and cures, the bottom space of Die2 and Die3 is supported as a whole, transforming the connection between the chip and the glass core layer from one relying on local bonding points to a unified structural state supported by continuously cured material. This not only effectively disperses the thermal and mechanical stresses experienced by the chip during use but also suppresses localized stress concentrations caused by differences in the thermal expansion coefficients of the materials. The filler material is not limited to traditional epoxy-based underfill materials; other encapsulation material systems with similar flow-curing properties can also be used, such as modified epoxy resins, epoxy-siloxane hybrid materials, or low-modulus polymer fillers.

[0096] 18. Molding and Grinding

[0097] After the bonding and gap filling of the back-side chips are completed, the overall packaging stage begins, which involves a molding + grinding process. At this point, through-hole and blind-hole structures have been formed inside the glass core layer. The first chip Die1, the second chip Die2, and the third chip Die3 are integrated on the front and back sides, respectively. The corresponding upper surface redistribution layer and back surface redistribution layer have also been constructed. The entire structure has complete electrical interconnection, but it is still in an open intermediate state in terms of shape and mechanical protection.

[0098] In the molding process, molding material is introduced outside the package structure, encapsulating the glass core layer, individual chips, and redistribution layers within a unified package. During its flow and curing process, the molding material fills the space around the chips and within structural voids, transforming the original multi-layered structure and multiple chips into a single, continuous package block. The primary function of this process is to provide external mechanical protection for the internal glass core layer, via structures, and chip interconnects. Simultaneously, the overall encapsulation with molding material further disperses and buffers the thermal and mechanical stresses that the package may experience during subsequent use, thereby improving the overall reliability of the multi-chip package structure.

[0099] After molding, the package's dimensions and thickness are usually still in a relatively rough state. Therefore, further refining of the package's thickness and surface morphology is required through a grinding process. During the grinding process, specific surfaces of the package are removed to ensure the overall thickness meets the predetermined requirements, while also guaranteeing good flatness and consistency of the package surface.

[0100] 19. Debonding of the second carrier board

[0101] After the molding and polishing processes are completed, the entire multi-chip package structure has met the predetermined requirements in terms of size, thickness, and flatness. The internal chips and interconnect structures are fully encapsulated and supported by the molding material. At this point, the role of the second carrier board is complete. Its main function is to provide temporary mechanical support for the overall structure during the preceding back-side redistribution layer construction, back-side chip mounting, underfill, and molding and polishing processes. With sufficient structural strength and integrity, the temporary bond between the second carrier board and the package can be safely released, allowing the package structure to become independent of the carrier board support.

[0102] 20. External interconnection and finished product separation

[0103] After the second substrate debonding is completed, the final stage of external interconnection and final product separation begins, namely the ball grid array (BGA) construction and singulation process. During BGA construction, a ball grid array is formed at designated pad locations on the package, enabling the multi-chip package to electrically connect to external circuit boards. By introducing solder balls, the electrical interconnections established within the package by vias and redistribution layers are extended to the outside, thereby enabling the output of chip functionality to system-level applications. Subsequently, the singulation process segments the entire package, cutting the originally sheet-like package structure into several independent single-chip packages. After segmentation, each packaged device includes a glass core layer, via and blind via structures, front and back redistribution layers, and multiple integrated functional chips, achieving standardized external interconnect interfaces through the BGA.

[0104] Example 2

[0105] Based on the above method, this embodiment provides a Glass Core multi-chip packaging structure. The packaging structure uses a glass core layer as the core carrier, and achieves collaborative interconnection and integrates multiple chips on its front and back sides. Overall, it presents a composite form of glass interposer, vertical interconnection, front and back wiring, and multi-chip collaborative integration. Each functional unit cooperates with each other in space and electrically to form a complete, stable and highly integrated packaging system.

[0106] Specifically, the core of this packaging structure is a single piece of glass core layer. In its finished state, the glass core layer maintains excellent overall continuity and flatness. Its interior is not a solid structure, but rather contains several through-holes and blind vias according to the packaging design requirements. The through-holes extend along the thickness direction of the glass core layer and, after metallization, form vertical interconnect channels with good conductivity, ensuring reliable electrical connection between the upper and lower surfaces of the glass core layer. The blind vias extend only to a localized area of ​​the glass core layer's thickness and do not penetrate the entire layer. Internal chips are embedded within these blind vias. Through this blind via structure, the internal chips can be stably housed within the glass core layer, and their positional relationship is precisely defined within the packaging structure, thereby achieving high-density embedded integration of the chips.

[0107] A front-side metal wiring layer is constructed on the upper surface of the glass core layer. This front-side metal wiring layer is designed and laid out around the internal chips within the blind vias in the glass core layer, allowing the electrodes of the internal chips to be re-exposed through the metal wiring and electrically connected to the metallized vias in the glass core layer. Through the front-side metal wiring layer, the internal chips are no longer limited to their original pad layout but can be rewired and functionally rearranged according to packaging requirements. External interconnection points are also provided on the outer region of the front-side metal wiring layer. These interconnection points are further configured with ball grid arrays to achieve electrical connections between the package structure and the external circuit board. Through the ball grid array, the complex multi-chip interconnection relationships within the glass core layer are uniformly exposed, giving the entire package structure a standardized and easily system-integrated external interface.

[0108] A back metal wiring layer is constructed on the lower surface of the glass core layer. This back metal wiring layer is also electrically connected to the metallized vias inside the glass core layer, thus forming a continuous electrical interconnect network with the front metal wiring layer and the internal chips. Several external chips are further bonded to the outside of the back metal wiring layer. These external chips can be arranged in parallel on the back of the glass core layer according to functional requirements. The external chips are electrically connected directly to the back metal wiring layer through their bottom pads, thereby establishing electrical connections with the internal chips and the front wiring layer inside the glass core layer via the metallized vias. Thus, the internal chips, external chips, and the front and back metal wiring layers together constitute a multi-chip system that is interconnected and functionally coordinated.

[0109] From an overall structural perspective, this package structure achieves electrical connectivity between the upper and lower surfaces vertically through metallized vias, while horizontally it relies on front and back metal wiring layers for flexible signal rearrangement and functional partitioning. Internal chips are embedded within the glass core layer, while external chips are distributed on the back of the glass core layer. These two layers are spatially layered and electrically tightly coupled through vias and wiring layers, effectively avoiding the heat dissipation difficulties and stress concentration problems associated with simple chip stacking. Furthermore, the excellent dimensional stability and electrical insulation properties of the glass core layer itself allow this package structure to maintain good geometric accuracy and electrical performance consistency even under high-density interconnection and multi-chip collaborative operation.

[0110] In summary, the final packaging structure of this invention fully leverages the advantages of the glass core layer in terms of flatness, dimensional stability, and insulation performance. Through the coordinated design of through-holes and blind vias, it achieves an organic combination of internal embedded chip integration and external chip surface integration. The front and back metal wiring layers are structurally independent but electrically interconnected, making the interconnection relationships between multiple chips clearer and more controllable, while significantly improving the integration and design freedom of the packaging structure. Compared to existing multi-chip packaging structures, this structure exhibits significant advantages in space utilization, electrical interconnect reliability, and overall packaging stability, making it particularly suitable for high-density, multi-functional, and heterogeneous chip integration packaging scenarios.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; under the concept of the present invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the present invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A Glass Core multi-chip packaging method, characterized in that, Including the following steps: Laser-induced modification of the glass core layer is performed to form easily corroded through-hole modification regions and blind-hole modification regions; Through-holes penetrating the glass core layer are generated in the through-hole modification region by wet etching and then metallized. Blind holes extending from the upper surface of the glass core to a set depth are generated in the blind hole modification area by wet etching. Several internal chips are embedded in blind vias, and a front metal wiring layer is constructed on the upper surface of the glass core layer; the front metal wiring layer is electrically connected to the internal chips and the metallized vias, and at the same time provides external interconnection points. The glass core layer is flipped to form a back metal wiring layer on its lower surface, which is electrically connected to the metallized vias and provides external interconnection points. Several external chips are bonded to the outside of the back metal wiring layer, and the external chips are electrically connected to the back metal wiring layer through external interconnection points. The gaps between the external chip and the glass core layer and its back metal wiring layer are filled and cured, and then molded and polished to form a robust and reliable multi-core package structure. The outer interconnection points of the front metal wiring layer are also constructed with a ball grid array to realize the electrical connection and signal interaction between the multi-core package structure and the external circuit.

2. The Glass Core multi-chip packaging method as described in claim 1, characterized in that, After laser-induced denaturation and before wet etching, the glass core layer undergoes crack sealing and passivation treatment, including: S1. Clean the surface of the glass core layer to remove debris and redeposit generated during the laser modification process; S2. Prepare a compressive stress sealing film on the surface of the glass core layer to bridge and seal microcracks in the modified area; S3. Hydrate and passivate the glass core layer to suppress the ability of microcracks to guide the propagation of corrosive media.

3. The Glass Core multi-chip packaging method as described in claim 2, characterized in that, Step S1 includes: The glass core layer was ultrasonically cleaned in deionized water for 2 minutes, then transferred to anhydrous ethanol and ultrasonically cleaned for 1 minute to replace the water and remove fine particles. After removal, the surface was dried with nitrogen. If there is concern about organic contamination, isopropanol was added after ultrasonic cleaning and rinsed for 30 seconds before drying. Finally, it was pre-baked on a hot plate at 120°C for 3 minutes to remove adsorbed water.

4. The Glass Core multi-chip packaging method as described in claim 2, characterized in that, Step S2 includes: Inorganic silica sol is dropped onto the surface of a glass core layer and spin-coated to form a uniform film. Immediately after spin-coating, the film is softened to allow the sol to undergo further condensation and form a dense silica network. The softening process includes a first stage and a second stage: in the first stage, the glass core layer is placed horizontally on a hot plate preheated to 80°C for 2 minutes to remove low-boiling-point solvents from the film; in the second stage, the glass core layer is placed horizontally on a hot plate preheated to 150°C for 5 minutes to promote the condensation reaction of the sol.

5. The Glass Core multi-chip packaging method as described in claim 2, characterized in that, Step S3 includes: Place the glass core layer in a water vapor environment at 70-85℃ for 3-8 minutes to allow slight hydration of the microcrack tips, which blunts the tips and reduces the tendency for subsequent corrosion to propagate rapidly along the cracks; or immerse the glass core layer in deionized water at 60-70℃ for 1-3 minutes and then remove it and blow it dry with nitrogen; finally, pre-bake it on a hot plate at 120℃ for 2 minutes to remove the surface water film.

6. The Glass Core multi-chip packaging method as described in claim 1, characterized in that, Before generating vias by wet etching, a layer of photoresist is first uniformly coated on the surface of the glass core layer to form a continuous cover film. Then, exposure and development are performed according to the pre-designed photolithography pattern, so that the photoresist forms a patterned structure with a set distribution on the surface of the glass core layer. The photoresist is selectively retained to cover the surface position of the corresponding blind hole modification area, while the via modification area is exposed.

7. The Glass Core multi-chip packaging method as described in claim 6, characterized in that, The metallization includes: forming a continuous metal seed layer on the inner wall of the via through by physical vapor deposition, and then thickening the metal layer by electroplating to obtain a via conductor that meets electrical performance requirements; or forming a thin metal layer on the inner wall of the via through by atomic layer deposition, and then thickening the metal layer by electroplating to improve conductivity; or growing a metal layer in situ on the inner wall of the via by chemical copper plating to form a continuous metal conductive path inside the via.

8. The Glass Core multi-chip packaging method as described in claim 7, characterized in that, Before generating blind vias via wet etching, the photoresist covering the blind via modification area is first removed, and the glass core layer is temporarily fixed to the surface of the first carrier plate used as a support. Then, a layer of photoresist is uniformly coated on the surface of the glass core layer to form a continuous cover film. Subsequently, exposure and development are performed according to the pre-designed photomask pattern, so that the photoresist forms a patterned structure with a set distribution on the surface of the glass core layer. The photoresist is selectively retained to cover the surface position of the corresponding via, while the blind via modification area is exposed. Finally, after the blind vias are generated via wet etching, the photoresist covering the vias is removed.

9. The Glass Core multi-chip packaging method as described in claim 8, characterized in that, After embedding the internal chip in the blind via and completing the front metal wiring layer construction, the glass core layer is flipped and temporarily fixed to the second carrier board used as a support through the front metal wiring layer, while the first carrier board is removed; the second carrier board is removed after completing the molding and grinding to form a structurally stable multi-core package structure.

10. A multi-core packaging structure constructed based on the method of any one of claims 1 to 9, characterized in that, The device includes a glass core layer and a front metal wiring layer and a back metal wiring layer respectively constructed on the upper and lower surfaces of the glass core layer; the glass core layer has a plurality of through holes and blind holes, the through holes are conductive after being metallized, and a plurality of internal chips are embedded in the blind holes; the front metal wiring layer is electrically connected to the internal chips and the metallized through holes, and also provides external interconnection points, the external interconnection points being provided with ball grid arrays for connecting external circuits; the back metal wiring layer is electrically connected to the metallized through holes, and a plurality of external chips are bonded to the outside of the back metal wiring layer, the external chips being electrically connected to the back metal wiring layer.

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