Layout structure and test method of fast recovery diode
By alternating fast recovery diodes with different current specifications on the wafer and using a specific probe card, the problem of multiple tests for fast recovery diodes was solved, achieving efficient electrical performance testing and cost reduction.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-13
- Publication Date
- 2026-04-07
AI Technical Summary
In existing technologies, fast recovery diodes require multiple tests when the current specifications are different, which leads to complex testing procedures, high probe card costs, and low production capacity.
A fast recovery diode layout structure is adopted, in which diodes of different current specifications are alternately distributed on the wafer, and electrical performance is tested by a specific probe card, reducing the number of test procedures and probe cards used.
This technology enables simultaneous testing of diodes with different current ratings within a single test program, reducing the number of tests and probe card costs, and improving production efficiency.
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Figure CN121805809A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the semiconductor field, and in particular to a layout structure and testing method for a fast recovery diode. Background Technology
[0002] A fast recovery diode (FRD) is a power semiconductor device characterized by good switching performance, short reverse recovery time, and soft recovery characteristics. Fast recovery diodes have wide applications in many fields, such as high frequency, industrial control, rectification, photovoltaics, energy storage, and consumer electronics.
[0003] Fast recovery diodes (FCDs) come in different current ratings (e.g., 100A, 150A, 300A) depending on their conduction current. Before mass production, FCDs require electrical performance verification. To shorten the verification cycle and reduce fabrication costs, FCDs with different current ratings are often combined onto a single layout for electrical performance testing (typically using chip probing, CP). Because FCDs with different current ratings have varying dimensions, chip probing (CP testing) presents challenges: it requires multiple tests (more than n tests if there are n current ratings), and different current ratings necessitate different test procedures and probe cards, impacting production capacity. Summary of the Invention
[0004] Based on this, this application provides a layout structure and testing method for fast recovery diodes, which reduces testing procedures, reduces the number of tests, reduces probe card costs, and increases production capacity.
[0005] In a first aspect, embodiments of this application provide a layout structure for a fast recovery diode, comprising:
[0006] A wafer includes alternating odd-numbered and even-numbered row regions. Each odd-numbered row region includes several first regions arranged sequentially along the row direction. Each even-numbered row region includes several second regions arranged sequentially along the row direction. The size of the second regions is equal to the size of the first regions. Multiple first regions and second regions are arranged alternately in the column direction, which is perpendicular to the row direction.
[0007] A first recovery diode and a second recovery diode are located in the second region. The second recovery diode is located on one side of the first recovery diode in the row direction. The first recovery diode has a first current specification, and the second recovery diode has a second current specification.
[0008] The third recovery diode is located in the first region. The third recovery diode has a third current specification, which is greater than the size of the first current specification and also greater than the size of the second current specification.
[0009] In some embodiments of this application, the size of the third recovery diode is larger than the size of the first recovery diode and the size of the second recovery diode.
[0010] In some embodiments of this application, the first region has only one third recovery diode, and the second region has one first recovery diode and one second recovery diode.
[0011] In some embodiments of this application, the third current specification of the third recovery diode includes 300A, the first current specification of the first recovery diode includes 100A, and the second current specification of the second recovery diode includes 150A.
[0012] In some embodiments of this application, in addition to a third recovery diode, the first region also has a fourth recovery diode. The fourth recovery diode is located on one side of the third recovery diode in the row direction. The fourth recovery diode has a fourth current specification, which is smaller than the size of the first current specification and smaller than the size of the second current specification.
[0013] In some embodiments of this application, the third current specification of the third recovery diode includes 100A, the first current specification of the first recovery diode includes 60A, the second current specification of the second recovery diode includes 80A, and the fourth current specification of the fourth recovery diode includes 40A.
[0014] In some embodiments of this application, the wafer further includes dicing channels located between adjacent first regions, between adjacent second regions, and between adjacent first and second regions.
[0015] Secondly, embodiments of this application also provide a testing method, including:
[0016] A probe card is provided, which includes a first part of probes and a second part of probes located on one side of the first part of probes. The first part of probes is coupled to a first power supply through a first control switch, and the second part of probes is coupled to a second power supply through a second control switch.
[0017] Provides the aforementioned layout structure for the fast recovery diode;
[0018] Align the probe card with a second region, with the first part of the probe contacting the first recovery diode and the second part of the probe contacting the second recovery diode;
[0019] Close the first control switch, apply a test current to the first recovery diode through the first part of the probe, and measure the forward voltage drop of the first recovery diode;
[0020] Turn off the first control switch, close the second control switch, apply a test current to the second recovery diode through the second part of the probe, and measure the forward voltage drop of the second recovery diode;
[0021] Turn off the second control switch, move the wafer or the probe card so that the probe card is aligned with a first area, and the first part of the probe and the second part of the probe contact the third recovery diode;
[0022] Close the first control switch and the second control switch, apply a test current to the third recovery diode through the first part probe and the second part probe, and measure the forward voltage drop of the third recovery diode.
[0023] In some embodiments of this application, both the first part probe and the second part probe have multiple rows, and each row of the first part probe and each row of the second part probe have multiple probes.
[0024] In some embodiments of this application, when a test current is applied through the first probe, the magnitude of the test current is gradually increased;
[0025] When applying the test current through the second probe, gradually increase the magnitude of the test current.
[0026] The embodiments of this application may have, or at least have, the following advantages:
[0027] The fast recovery diode layout structure in this embodiment includes: a wafer, the wafer including alternately distributed odd-numbered row regions and even-numbered row regions, each odd-numbered row region including a plurality of first regions arranged sequentially along the row direction, each even-numbered row region including a plurality of second regions arranged sequentially along the row direction, the size of the second regions being equal to the size of the first regions, and multiple first regions and second regions being arranged alternately in the column direction, the column direction being perpendicular to the row direction; a first recovery diode and a second recovery diode located in the second regions, the second recovery diode being located on one side of the first recovery diode in the row direction, the first recovery diode having a first current specification, and the second recovery diode having a second current specification; and a third recovery diode located in the first regions, the third recovery diode having a third current specification, the magnitude of the third current specification being greater than the magnitude of the first current specification and greater than the magnitude of the second current specification. In this application, by merging a first recovery diode and a second recovery diode of different current specifications into a second region, and placing a third recovery diode of a different current specification in the first region, during electrical performance testing (ChipProbing, CP) of the wafer, the first and second regions are of the same or identical size and regularly distributed on the wafer. This allows the testing equipment to maintain a fixed step size (the step size is the distance from one test region to an adjacent test region, such as from the first region to the second region, or from one first region to an adjacent first region, or from one second region to an adjacent second region) within a single test program. Therefore, the first and second regions can be tested sequentially as a single test unit within a single test program. This means that electrical performance testing of the first recovery diode, a second recovery diode, and a third recovery diode of different current specifications can be performed within a single test program, reducing the number of test programs, the number of tests, and increasing production capacity. Furthermore, a probe card with a specific structure can be used during testing to perform electrical performance testing on recovery diodes of various current specifications, eliminating the need for a separate probe card for each current specification and reducing probe card costs.
[0028] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0030] Figure 1 A schematic diagram of the layout structure of a fast recovery diode provided for some embodiments of this application;
[0031] Figure 2 for Figure 1 A magnified structural diagram of the first and second regions in the middle;
[0032] Figure 3 Enlarged structural schematic diagrams of the first and second regions provided in other embodiments of this application;
[0033] Figure 4 This is a schematic diagram of the probe card structure provided in some embodiments of this application;
[0034] Figure 5 A schematic diagram of the structure for testing the electrical performance of a second region in a test method provided in some embodiments of this application;
[0035] Figure 6 This is a schematic diagram of the structure for testing the electrical performance of a first region in a test method provided in some embodiments of this application.
[0036] Explanation of reference numerals in the attached figures:
[0037] Wafer 100; Grading lane 101;
[0038] First region 11; Second region 12; First recovery diode 1; Second recovery diode 2; Third recovery diode 3; Fourth recovery diode 4; First part probe 21; Second part probe 22. Detailed Implementation
[0039] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0040] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.
[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0043] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0044] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.
[0045] This application first provides a layout structure for a fast recovery diode. Figure 1 A schematic diagram of the layout structure of a fast recovery diode provided for some embodiments of this application; Figure 2 for Figure 1 A magnified structural diagram of a first region and a second region.
[0046] Reference Figure 1 and Figure 2 The layout structure of fast recovery diodes includes:
[0047] Wafer 100 includes alternating odd-numbered row regions and even-numbered row regions. Each odd-numbered row region includes a plurality of first regions 11 arranged sequentially along the row direction. Each even-numbered row region includes a plurality of second regions 12 arranged sequentially along the row direction. The size of the second region 12 is equal to the size of the first region 11. Multiple first regions 11 and second regions 12 are arranged alternately in the column direction, which is perpendicular to the row direction.
[0048] A first recovery diode 1 and a second recovery diode 2 are located in the second region 12. The second recovery diode 2 is located on one side of the first recovery diode 1 in the row direction. The first recovery diode 1 has a first current specification and the second recovery diode 2 has a second current specification.
[0049] The third recovery diode 3 is located in the first region 11. The third recovery diode 3 has a third current specification, which is greater than the size of the first current specification and greater than the size of the second current specification.
[0050] Wafer 100 may be a silicon (Si) wafer, a silicon-germanium (SiGe) wafer, a silicon-germanium-carbon (SiGeC) wafer, a silicon carbide (SiC) wafer, a gallium arsenide (GaAs) wafer, an indium arsenide (InAs) wafer, an indium phosphide (InP) wafer, or other III / V or II / VI semiconductor wafers. Alternatively, for example, wafer 101 may be a layered wafer comprising Si / SiGe, Si / SiC, silicon-on-insulator (SOI), germanium-on-insulator (SOI), or silicon-germanium-on-insulator.
[0051] Wafer 100 includes alternating odd-numbered and even-numbered rows of regions, as shown in one example, such as Figure 1 As shown, wafer 100 includes 13 row regions, where rows labeled 1, 3, 5, 7, 9, 11 and 13 are odd-numbered row regions, and rows labeled 2, 4, 6, 8, 10 and 12 are even-numbered row regions.
[0052] Each odd-numbered row region includes several first regions 11 arranged sequentially along the row direction, and each even-numbered row region includes several second regions 12 arranged sequentially along the row direction, such as... Figure 1As shown, the row direction is the X-axis direction, and the column direction is the Y-axis direction. Since the wafer 100 is circular, in order to improve the utilization rate of the wafer, the number of first regions 11 in different odd-numbered row regions can be different, and the number of second regions 12 in different even-numbered row regions can be different.
[0053] The first region 11 and the second region 12 are the same size or dimensions, and the plurality of first regions 11 and the plurality of second regions 12 are arranged in rows and columns. The wafer 100 also includes dicing channels 101 located between adjacent first regions 11, between adjacent second regions 12, and between adjacent first regions 11 and second regions 12 (see reference). Figure 2 ).
[0054] In this application, fast recovery diodes (FRDs) with different current specifications are respectively arranged in the first region 11 and the second region.
[0055] In some embodiments, continue to refer to Figure 1 and Figure 2The second region 12 has a first recovery diode 1 and a second recovery diode 2. The second recovery diode 2 is located on one side of the first recovery diode 1 in the row direction. The first recovery diode 1 has a first current specification, and the second recovery diode 2 has a second current specification. The first region 11 has only one third recovery diode 3. The third recovery diode 3 has a third current specification. The magnitude of the third current specification is greater than the magnitude of the first current specification and greater than the magnitude of the second current specification. In a specific example, the magnitude of the third current specification of the third recovery diode 3 includes 300A, the magnitude of the first current specification of the first recovery diode 1 includes 100A, and the magnitude of the second current specification of the second recovery diode 2 includes 150A. Therefore, in this application, a first recovery diode 1 and a second recovery diode 2 with different current specifications are combined into the second region 12, and a third recovery diode 3 with a different current specification is arranged in the first region 11. When performing electrical performance testing (Chip Probing, CP) on the wafer 100, since the overall size of the first region 11 and the second region 12 is the same or consistent, and they are regularly distributed on the wafer 101, the first region 11 and the second region 12 can meet the requirement that the step size of the test equipment is a fixed value during testing (the step size is the distance from one test region to another adjacent test region, such as from the first region 11 to the second region 12, or from one first region 11 to another adjacent first region, or from one second region 12 to another adjacent second region 12). Therefore, in one test program, the first region 11 and the second region 12 can be tested as a test unit in sequence. That is, the electrical performance testing of the first recovery diode 1, a second recovery diode 2 and a third recovery diode 3 with different current specifications can be realized in one test program, which can reduce the setting of test programs, reduce the number of tests, and increase production capacity. Furthermore, during testing, a probe card with a specific structure can be used to perform electrical performance tests on recovery diodes of various current specifications, eliminating the need to set up a probe card for each type of recovery diode and reducing the cost of probe cards.
[0056] In some embodiments, reference Figure 3The second region 12 has a first recovery diode 1 and a second recovery diode 2, with the second recovery diode 2 located to one side of the first recovery diode 1 in the row direction. The first recovery diode 1 has a first current specification, and the second recovery diode 2 has a second current specification. The first region 11, in addition to a third recovery diode 3, also has a fourth recovery diode 4, located to one side of the third recovery diode 3 in the row direction. The fourth recovery diode 4 has a fourth current specification, smaller than both the first and second current specifications. In a specific example, the third current specification of the third recovery diode 3 is 100A, the first current specification of the first recovery diode 1 is 60A, the second current specification of the second recovery diode 2 is 80A, and the fourth current specification of the fourth recovery diode 4 is 40A. In this application, a first recovery diode 1 and a second recovery diode 2 with different current specifications are combined into the second region 12, and a third recovery diode 3 and a fourth recovery diode 4 with different current specifications are combined into the first region 11. This is used for electrical performance testing (probe testing, chip testing) of the wafer 100. During probing (CP), since the first region 11 and the second region 12 are of the same or identical size and are regularly distributed on the wafer 101, the first region 11 and the second region 12 can satisfy the requirement that the step size of the test equipment during testing is a fixed value (the step size is the distance to move from one test region to another adjacent test region, such as from the first region 11 to the second region 12, or from one first region 11 to another adjacent first region, or from one second region 12 to another adjacent second region 12). Therefore, in one test program, the first region 11 and the second region 12 can be tested as a single test unit. That is, the electrical performance testing of a first recovery diode 1, a second recovery diode 2, a third recovery diode 3, and a fourth recovery diode 4 with different current specifications can be achieved in one test program. This reduces the number of test programs, the number of tests, and the throughput. Furthermore, a probe card with a specific structure can be used during testing to perform electrical performance testing on recovery diodes with multiple current specifications, eliminating the need for a separate probe card for each current specification recovery diode, thus reducing the cost of probe cards.
[0057] The current rating of a recovery diode is directly proportional to its size; that is, the larger the size of the recovery diode, the larger its current rating. In some embodiments, when the third current rating of the third recovery diode 3 is greater than the first current rating of the first recovery diode 1 and the second current rating of the second recovery diode 2, the size of the third recovery diode 3 is correspondingly greater than the size of the first recovery diode 1 and the second recovery diode 2.
[0058] In other embodiments, when the third current specification of the third recovery diode 3 is greater than the first current specification of the first recovery diode 1 and the second current specification of the second recovery diode 2, the fourth current specification of the fourth recovery diode 4 is less than the first current specification of the first recovery diode 1 and less than the second current specification of the second recovery diode 2. Accordingly, the size of the third recovery diode 3 is greater than the size of the first recovery diode 1 and the second recovery diode 2, and the size of the fourth recovery diode 4 is less than the size of the first recovery diode 1 and less than the size of the second recovery diode 2.
[0059] This application also provides a probe card, as referenced in the embodiments. Figure 4 The probe card includes a first probe 21 and a second probe 22 located on one side of the first probe 21. The first probe 21 is coupled to a first power supply through a first control switch, and the second probe 22 is coupled to a second power supply through a second control switch.
[0060] In some embodiments, the first probe portion 21 and the second probe portion 22 each have multiple rows, each row of the first probe portion 21 and each row of the second probe portion 22 each have multiple probes, and each row of the first probe portion 21 and each row of the second probe portion 22 are arranged along the column direction ( Figure 4 Arranged along the Y-axis. In a specific example, such as... Figure 4 As shown, the first probe 21 has two rows of probes, each row of the first probe 21 includes 5 probes, and the second probe 22 has three rows of probes, each row of the second probe 22 also includes 5 probes.
[0061] The first part of probe 21 is coupled to a first power supply via a first control switch, and the second part of probe 22 is coupled to a second power supply via a second control switch. In a specific example, there can be one first control switch, and all the first part probes 21 are controlled to be switched on and off by one first control switch. When the first control switch is closed, all the first part probes 21 are connected to the first power supply, and test current can be applied to the corresponding fast recovery diodes on the wafer through the first part probes 21. When the first control switch is open, all the first part probes 21 are disconnected from the first power supply. Alternatively, there can be one second control switch, and all the second part probes 22 are controlled to be switched on and off by one first control switch. When the second control switch is closed, all the second part probes 22 are connected to the second power supply, and test current can be applied to the corresponding fast recovery diodes on the wafer through the second part probes 22. When the second control switch is open, all the second part probes 22 are disconnected from the second power supply.
[0062] In another specific example, there can be multiple first control switches and multiple second control switches. Each row of first probes 21 is connected to a first power supply, that is, the connection between the first probes 21 of the corresponding row and the first power supply can be controlled by the corresponding first control switch. Test current can be applied to the corresponding fast recovery diode on the wafer by the first probes 21 of the corresponding row. Each row of second probes 22 is connected to a second power supply, that is, the connection between the second probes 22 of the corresponding row and the second power supply can be controlled by the corresponding second control switch. Test current can be applied to the corresponding fast recovery diode on the wafer by the second probes 22 of the corresponding row.
[0063] Therefore, by using the aforementioned probe card, and by controlling the first part of the probe 21 to be connected to the first power supply, and / or controlling the second part of the probe 22 to be connected to the second power supply, only one probe card is needed to test the electrical performance of the corresponding fast recovery diodes in the first region 11 and the second region 12, thereby reducing the cost of the probe card.
[0064] This application also provides a testing method, including:
[0065] refer to Figure 4 A probe card is provided, which includes a first probe 21 and a second probe 22 located on one side of the first probe 21. The first probe 21 is coupled to a first power supply through a first control switch, and the second probe 22 is coupled to a second power supply through a second control switch.
[0066] refer to Figure 1 and Figure 3 , or refer to Figure 3 The aforementioned layout structure of the fast recovery diode is provided;
[0067] refer to Figure 5 Align the probe card with a second region 12, with the first part of the probe 21 contacting the first recovery diode 1 and the second part of the probe 22 contacting the second recovery diode 2;
[0068] Close the first control switch, apply a test current to the first recovery diode 1 through the first probe 21, and measure the forward voltage drop of the first recovery diode 1;
[0069] Turn off the first control switch, close the second control switch, apply a test current to the second recovery diode 2 through the second probe 22, and measure the forward voltage drop of the second recovery diode 2.
[0070] refer to Figure 6 Turn off the second control switch, move the wafer 100 or the probe card so that the probe card is aligned with a first region 11, and the first part of the probe 21 and the second part of the probe 22 are in contact with the third recovery diode 3.
[0071] Close the first control switch and the second control switch, apply a test current to the third recovery diode 3 through the first probe 21 and the second probe 22, and measure the forward voltage drop of the third recovery diode 3.
[0072] In some embodiments, when a test current is applied through the first probe 21, the magnitude of the test current is gradually increased;
[0073] When applying the test current through the second probe 22, the magnitude of the test current is gradually increased.
[0074] In some embodiments, when there are multiple first control switches and second control switches, in the case of... Figure 2 or Figure 3 When performing electrical performance tests on the fast recovery diode layout shown, the probes of the corresponding rows in contact with the corresponding recovery diode can be controlled to close to apply a test current. For example, refer to... Figure 3 When performing electrical performance testing, the probe card contacts the first region 11. When the probe card contacts the third recovery diode 3, including a row of first part probes 21 and three rows of second part probes 22, the first control switch corresponding to the row of first part probes 21 is closed, and the three second control switches corresponding to the three rows of second part probes 22 are closed, so that the test current is applied to the third recovery diode 3 through the row of first part probes 21 and the three rows of second part probes 22. At the same time, the probe card contacts the fourth recovery diode 4 with only a row of first part probes 21. The first control switch corresponding to the row of first part probes 21 is closed, so that the test current is applied to the fourth recovery diode 4 through the row of first part probes 21.
[0075] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0076] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0077] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A layout structure for a fast recovery diode, characterized in that, include: The wafer includes alternating odd-numbered row regions and even-numbered row regions. Each odd-numbered row region includes a plurality of first regions arranged sequentially along the row direction, and each even-numbered row region includes a plurality of second regions arranged sequentially along the row direction. The size of the second regions is equal to the size of the first regions, and a plurality of first regions and second regions are arranged alternately in the column direction, which is perpendicular to the row direction. A first recovery diode and a second recovery diode are located in the second region, the second recovery diode being located on one side of the first recovery diode in the row direction, the first recovery diode having a first current specification, and the second recovery diode having a second current specification; A third recovery diode located in the first region, the third recovery diode having a third current specification, the magnitude of the third current specification being greater than the magnitude of the first current specification and greater than the magnitude of the second current specification.
2. The layout structure of the fast recovery diode according to claim 1, characterized in that, The size of the third recovery diode is larger than the size of the first recovery diode and the size of the second recovery diode.
3. The layout structure of the fast recovery diode according to claim 1 or 2, characterized in that, The first region has only one third recovery diode, and the second region has one first recovery diode and one second recovery diode.
4. The layout structure of the fast recovery diode according to claim 3, characterized in that, The third current specification of the third recovery diode is 300A, the first current specification of the first recovery diode is 100A, and the second current specification of the second recovery diode is 150A.
5. The layout structure of the fast recovery diode according to claim 1 or 2, characterized in that, In addition to a third recovery diode, the first region also has a fourth recovery diode. The fourth recovery diode is located on one side of the third recovery diode in the row direction. The fourth recovery diode has a fourth current specification, which is smaller than the size of the first current specification and smaller than the size of the second current specification.
6. The layout structure of the fast recovery diode according to claim 5, characterized in that, The third current specification of the third recovery diode includes 100A, the first current specification of the first recovery diode includes 60A, the second current specification of the second recovery diode includes 80A, and the fourth current specification of the fourth recovery diode includes 40A.
7. The layout structure of the fast recovery diode according to claim 1, characterized in that, The wafer also includes dicing channels located between adjacent first regions, between adjacent second regions, and between adjacent first and second regions.
8. A testing method, characterized in that, include: A probe card is provided, the probe card including a first part of probes and a second part of probes located on one side of the first part of probes, the first part of probes being coupled to a first power supply via a first control switch, and the second part of probes being coupled to a second power supply via a second control switch; Provides a layout structure for the fast recovery diode according to any one of claims 1-7; Align the probe card with a second region, with the first portion of the probes contacting the first recovery diode and the second portion of the probes contacting the second recovery diode; Close the first control switch, apply a test current to the first recovery diode through the first part of the probe, and measure the forward voltage drop of the first recovery diode; Turn off the first control switch, close the second control switch, apply a test current to the second recovery diode through the second part of the probe, and measure the forward voltage drop of the second recovery diode; Turn off the second control switch, move the wafer or the probe card so that the probe card is aligned with one of the first regions, and the first part of the probe and the second part of the probe contact the third recovery diode; Close the first control switch and the second control switch, apply a test current to the third recovery diode through the first part probe and the second part probe, and measure the forward voltage drop of the third recovery diode.
9. The test method according to claim 8, characterized in that, Both the first part of the probe and the second part of the probe have multiple rows, and each row of the first part of the probe and each row of the second part of the probe have multiple probes.
10. The test method according to claim 8, characterized in that, When applying a test current through the first part of the probe, the magnitude of the test current is gradually increased; When applying the test current through the second probe, the magnitude of the test current is gradually increased.