Wafer test method and system, electronic equipment and storage medium
By querying the server before wafer testing to determine whether retesting is allowed, and continuing probing in coordinate order when not all chips are covered, the problem of wafer quality abnormalities caused by test interruption was solved, thus achieving the integrity and accuracy of testing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-14
- Publication Date
- 2026-04-07
AI Technical Summary
During wafer testing, some chips may not be tested due to reasons such as test machine failure, test software failure, or human error. This may result in some chips on the wafer not being probed, which may lead to quality abnormalities during retesting.
Before testing, the server is queried to determine whether the wafer is allowed to be retested. If not all chips are covered, probing continues in the order of coordinates and data is uploaded to avoid repeated testing of already tested chips.
This avoids repeated testing of chips already tested on the wafer, ensuring test integrity and preventing quality defects.
Smart Images
Figure CN121805818A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, and in particular to a wafer testing method and system, an electronic device, and a storage medium. BACKGROUND
[0002] Chip probing is a key link in the semiconductor production process, which is located after the completion of wafer manufacturing and before chip packaging. The core goal is to detect each die on the whole wafer to verify whether it meets the design specifications, including voltage, current, timing and functional parameters (such as threshold voltage, on-resistance, etc.). During testing, the probe card connects the tester to the exposed chip pins, and the tester applies input signals and collects output signals to determine whether the chip performance meets the standard. This process can directly feedback the yield of wafer manufacturing process and avoid invalid packaging of faulty chips.
[0003] Among them, some wafers require no retesting during testing, and the note on the shipping process card cannot be retested. However, misjudgment caused by human factors still occurs from time to time. SUMMARY
[0004] Therefore, the present application aims to provide a wafer testing method and system, an electronic device, and a storage medium to solve the above technical problems.
[0005] To achieve the above purpose, the first aspect of the present application provides a wafer testing method, which comprises: Before the tester tests the target wafer on the probe station, querying a server to determine whether the target wafer allows retesting; When the server queries that the target wafer does not allow retesting, querying whether there is measured data of the target wafer in the server; When the server cannot query the measured data of the target wafer, controlling the tester to test the chips on the target wafer in sequence according to a coordinate order, and uploading the test data to the server in real time; When the server queries the measured data of the target wafer, determining whether the measured data covers all chips on the target wafer; When the measured data does not cover all chips on the target wafer, determining the coordinates of the last tested chip on the target wafer, and controlling the tester to test the untested chips on the coordinates after the coordinates of the last tested chip, and testing all untested chips on the target wafer in sequence according to the coordinate order, and uploading the test data to the server in real time.
[0006] In one embodiment, after determining whether the measured data covers all chips on the target wafer, the method further comprises: When the measured data covers all chips on the target wafer, determining that the target wafer is a measured wafer. In one embodiment, before testing the target wafer on the probe station by the test machine, the method further comprises: uploading the batch number and process information of all wafers to be tested and whether retesting is allowed to the server; The method of querying the server to determine whether the target wafer allows retesting comprises: obtaining an image of the target wafer, obtaining the batch number of the target wafer according to the image, and querying the server according to the batch number and process information of the target wafer to determine whether the target wafer allows retesting.
[0007] In one embodiment, the method of querying whether the server has measured data of the target wafer comprises: querying whether the server has measured data of the target wafer according to the batch number, die number and process information of the target wafer; wherein the measured data includes coordinates of chips on the target wafer.
[0008] In one embodiment, after uploading the needle testing data to the server in real time, the method further comprises: integrating all test data of the target wafer to form a complete wafer map of the target wafer.
[0009] Based on the same inventive concept, the second aspect of the present application provides a wafer testing system, which comprises: a first query module for querying the server to determine whether the target wafer allows retesting before the test machine tests the target wafer on the probe station; a second query module for querying whether the server has measured data of the target wafer when the server queries that the target wafer does not allow retesting; a needle testing module for controlling the test machine to test chips on the target wafer in order according to the coordinate sequence when the server cannot query the measured data of the target wafer, and uploading the needle testing data to the server in real time; a determination module for determining whether the measured data covers all chips on the target wafer when the server queries the measured data of the target wafer; The needle test module is further configured to, when the measured data does not cover all chips on the target wafer, determine the coordinates of the last measured chip on the target wafer, control the tester to perform needle test on unmeasured chips on a coordinate next to the coordinates of the last measured chip, and sequentially perform needle test on all unmeasured chips on the target wafer according to the coordinate sequence, and upload the needle test data to the server in real time.
[0010] In one embodiment, the wafer test system further comprises: The determining module is configured to, when the measured data covers all chips on the target wafer, determine that the target wafer is a measured wafer.
[0011] In one embodiment, the wafer test system further comprises: The needle test information input module is configured to, before the tester performs needle test on a target wafer on a probe table, query the server to determine whether the target wafer is allowed to be retested, and upload the batch number and process information of all wafers to be tested and whether retesting is allowed to the server.
[0012] Based on the same inventive concept, a third aspect of the present application provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the wafer test method of the first aspect.
[0013] Based on the same inventive concept, a fourth aspect of the present application provides a non-transitory computer readable storage medium storing computer instructions for causing a computer to execute the wafer test method of the first aspect.
[0014] As can be seen from the above, the wafer test method provided by the present application obtains whether the target wafer is allowed to be retested by querying the server, when it is found that the target wafer is not allowed to be retested, queries whether there is measured data of the target wafer in the server, and when the measured data is not found, sequentially performs needle test on chips on the target wafer according to the coordinate sequence; when the measured data of the target wafer is found, it is further determined whether the measured data covers all chips on the target wafer, when the measured data does not cover all chips on the target wafer, the coordinates of the last measured chip on the target wafer are determined, the tester is controlled to perform needle test on unmeasured chips on a coordinate next to the coordinates of the last measured chip, and sequentially performs needle test on all unmeasured chips on the target wafer according to the coordinate sequence, and uploads the needle test data to the server in real time, thereby avoiding retesting of the measured chips on the target wafer and avoiding quality abnormalities of the wafer. BRIEF DESCRIPTION OF DRAWINGS
[0015] In order to make the technical solutions in the application or the related art clearer, the accompanying drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the accompanying drawings in the following description are only embodiments of the application, and other accompanying drawings can be obtained by those of ordinary skill in the art without any creative effort based on these accompanying drawings.
[0016] Figure 1 A flowchart of a wafer testing method provided by an embodiment of the application; Figure 2 A wafer map when the measured data does not cover all chips on a target wafer provided by an embodiment of the application; Figure 3 A wafer map obtained by sequentially performing needle testing on all unmeasured chips on a target wafer in a coordinate order provided by an embodiment of the application; Figure 4 A wafer map formed by integrating all testing data of a target wafer to form a complete wafer map of the target wafer provided by an embodiment of the application; Figure 5 A schematic diagram of a wafer testing system provided by another embodiment of the application; Figure 6 A schematic diagram of an electronic device of another embodiment of the application. DETAILED DESCRIPTION
[0017] In order to make the technical solutions in the application or the related art clearer, the accompanying drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the accompanying drawings in the following description are only embodiments of the application, and other accompanying drawings can be obtained by those of ordinary skill in the art without any creative effort based on these accompanying drawings.
[0018] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the application should be understood as the common meanings understood by those of ordinary skill in the art to which the embodiments of the application belong. The terms "first", "second", and similar terms used in the embodiments of the application do not represent any order, number, or importance, but are only used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, without excluding other elements or objects. The terms "connect" or "connected" and similar terms do not mean physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "up", "down", "left", "right", and the like only represent relative positional relationships, which can change when the absolute positions of the described objects change.
[0019] The inventors discovered that during probe testing, malfunctions in the testing machine, testing software, or accidental human intervention can cause the testing to stop halfway through. This results in incomplete data coverage of all chips on the wafer, meaning some chips on the wafer are not tested. When the testing machine or software restarts, it begins testing the entire wafer again from the first chip. This causes previously tested chips to be tested again, leading to quality issues on some wafers that are not permitted to be retested.
[0020] Based on this, this application provides a wafer testing solution to solve the above-mentioned technical problems.
[0021] Reference Figures 1-4 As shown, one embodiment of this application provides a wafer testing method, which includes the following steps: Step S10: Before the tester performs probe testing on the target wafer on the probe station, query the server to determine whether the target wafer is allowed to be retested. Step S20: When the server finds that the target wafer is not allowed to be retested, check if there is any test data of the target wafer in the server. Step S30: When the test data of the target wafer cannot be found in the server, control the test machine to perform probe tests on the chips on the target wafer in sequence according to the coordinate order, and upload the probe test data to the server in real time. Step S40: When the server retrieves the measured data of the target wafer, determine whether the measured data covers all chips on the target wafer. Step S50: When the measured data does not cover all chips on the target wafer, determine the coordinates of the last chip under test on the target wafer, and control the test machine to perform probe testing on the untested chip at the coordinates after the last chip under test. Perform probe testing on all untested chips on the target wafer in sequence according to the coordinate order, and upload the probe test data to the server in real time.
[0022] The wafer testing method provided in this application queries a server to determine whether a target wafer is allowed to be retested. If the server indicates that the target wafer is not allowed to be retested, it queries the server to see if there is any previously tested data for the target wafer. If no previously tested data is found, the chips on the target wafer are sequentially probed according to their coordinates. If previously tested data is found, it further determines whether the previously tested data covers all the chips on the target wafer. If the previously tested data does not cover all the chips on the target wafer, it determines the coordinates of the last chip under test on the target wafer and controls the testing machine to probe the untested chip at the coordinates following the last chip under test. The untested chips on the target wafer are then probed sequentially according to their coordinates, and the probe test data is uploaded to the server in real time. This avoids retesting the chips already tested on the target wafer and prevents wafer quality abnormalities.
[0023] Optionally, the process of the tester testing the wafer on the probe station is: first, fix the wafer corresponding to the process on the vacuum chuck of the probe station, the vision system of the probe station recognizes the alignment marks of the wafer and the probe card, and completes the micron-level accurate alignment of the probe and the chip pad / bump, then the probe card contacts the chip pin with controlled pressure, the tester inputs the preset test signal to the chip through the probe, collects the electrical response data of the chip, determines the state of the chip in real time, and stores the wafer batch number, chip number, process and chip coordinate information into the system, and the chuck of the probe station automatically moves the wafer after completing the detection of the single chip.
[0024] In one embodiment, after the server queries the measured data of the target wafer, and determines whether the measured data covers all chips on the target wafer, the step S40 further includes the following steps: Step S60, when the measured data covers all chips on the target wafer, determining that the target wafer is a measured wafer. At this time, it is not necessary to test the target wafer again to avoid retesting, and the target wafer can be directly unloaded.
[0025] In one embodiment, before the tester tests the target wafer on the probe station, and before the server is queried to determine whether the target wafer is allowed to be retested, the step S10 further includes the following steps: Step S01, uploading the batch number and process information of all wafers to be tested and whether retesting is allowed to the server.
[0026] For example, the following cases do not allow wafer retesting: I. Product test process limitation: The test program corresponding to the test process of the product contains a Trimming (trimming) test item. Through trimming, the internal circuit of the chip is corrected to make the chip performance meet the standard, so as to improve the yield. This item is mostly irreversible, and repeated testing will cause the actual correction value of the internal circuit of the chip to be wrong due to repeated Trimming of the product, thereby causing the chip to be scrapped. When such a product is imported, the customer will require that retesting is not allowed.
[0027] II. Product itself characteristic requirement: One-Time-Programmable (OTP) products will write specific data (code, configuration, key, serial number, etc.) into the chip during the first test. This programming operation can only be performed once, and once the information is written and finally determined, the data in the chip will be permanently fixed and cannot be erased, modified or rewritten. When such a product is imported, the customer will require that retesting is not allowed.
[0028] III. Product Test Procedure Limitations: Read Pass code is used to verify whether there is permission to read the data stored inside the chip, and Erase Pass Code is used to verify whether it is allowed to perform the operation of erasing the data of the chip. They are an important part of the chip security mechanism, which can prevent unauthorized data access and malicious erasure, and protect the information inside the chip. When the product test procedure contains the Read Pass code and / or Erase Pass Code function, the customer will require that the corresponding product not be allowed to be retested when providing the program.
[0029] IV. Limitation of Pinhole Number: Each CP test of the chip will form a pinhole due to the contact between the probe card and the chip. When the number of pinholes is too large, the area of the pinhole will be too large, which may cause abnormal wire bonding in the FT (Final Test) and thus cause low good products in the FT. The customer will limit the number of pinholes in the CP test.
[0030] In one embodiment, in step S10, the server is queried to determine whether the target wafer is allowed to be retested, including: An image of the target wafer is obtained, the batch number of the target wafer is obtained according to the image, and the server is queried according to the batch number and process information of the target wafer to determine whether the target wafer is allowed to be retested. Alternatively, a high-definition image of the edge mark area of the wafer is taken by a high-resolution industrial camera, after image preprocessing to eliminate stains, scratches and other interference, the character sequence in the image is recognized by an OCR (Optical Character Recognition) algorithm, that is, the batch number of the target wafer is obtained, and then according to the batch number and the process, the server can be queried to determine whether the target wafer is allowed to be retested. Wherein, the process information of the target wafer can be manually inputted by artificial.
[0031] In one embodiment, in step S20, whether the server has measured data of the target wafer, including: According to the batch number, die number and process information of the target wafer, whether the server has measured data of the target wafer is queried; wherein, the measured data includes the coordinates of the chips on the target wafer. Alternatively, the die number is obtained from the image of the target wafer.
[0032] In one embodiment, in step S50, after the probe test data is uploaded to the server in real time, the following steps are further included: Step S70, integrating all test data of the target wafer to form a complete wafer map of the target wafer.
[0033] Specifically, referring to Figure 2The image shown is a wafer diagram in one embodiment where the measured data does not cover all chips on the target wafer. This is because the test is interrupted due to reasons such as test machine malfunction, test software malfunction, or human error, resulting in the measured data not covering all chips on the target wafer, thus forming... Figure 2 The image shows an incomplete wafer diagram. Regions M and N are designated for automated pin inspection. To ensure pin quality, the chips in regions M and N are probed first, and then probed again from the beginning according to the coordinate sequence. Figure 2 As can be seen, there is a blank area between region M and the chip that has been tested above it, and there is also a blank area between region M and region N. The blank areas correspond to the untested chips.
[0034] Reference Figure 3 As shown, the control tester performs probe testing on the untested chip at the coordinates following the last tested chip, and sequentially performs probe testing on all untested chips on the target wafer according to the coordinate order, forming a wafer image. To avoid duplicate testing, regions M and N are skipped during probe testing. Figure 3 A blank area is formed in the middle.
[0035] Reference Figure 4 As shown, to... Figure 2 Wafer diagrams and Figure 3 The complete wafer map of the target wafer is formed by integrating the wafer map in the image.
[0036] Furthermore, in step S30, when pin mark inspection is required, the chips in regions M and N are first tested with pins, and then the chips are tested with pins in the coordinate order starting from the beginning.
[0037] In another embodiment, in step S30, when automatic pin mark inspection is not required, it is not necessary to perform pin inspection on the chips in regions M and N first, and the pin inspection on the chips can be performed directly from the beginning according to the coordinate sequence.
[0038] Optionally, probing the chips according to coordinate order can be performed by first testing each chip in a row along the row direction, and then switching to the next row to continue testing the chips in the next row; or by first testing each chip in a column along the column direction, and then switching to the next column to continue testing the chips in the next column, until all target chips on the wafer are covered. In other embodiments, testing can also be performed along a circular route.
[0039] It should be noted that the method of the embodiments of the present application can be executed by a single device, for example, a computer or a server, etc. The method of the embodiments can also be applied to a distributed scenario, and be completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only execute one or more steps in the method of the embodiments of the present application, and the multiple devices can interact with each other to complete the method.
[0040] It should be noted that some embodiments of the present application have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order and still achieve desirable results. Additionally, the processes depicted in the figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous.
[0041] Reference Figure 5 According to the same inventive concept, the present application also provides a wafer test system corresponding to the method of any of the above embodiments, which comprises the following modules: A first query module is configured to query a server to determine whether a target wafer is allowed to be retested before a tester tests the target wafer on a probe station; A second query module is configured to query the server whether there is measured data of the target wafer when the server queries that the target wafer is not allowed to be retested; A needle test module is configured to control the tester to sequentially test chips on the target wafer according to a coordinate order when the server cannot query the measured data of the target wafer, and upload the needle test data to the server in real time; A judgment module is configured to judge whether the measured data covers all chips on the target wafer when the server queries the measured data of the target wafer; The needle test module is further configured to determine the coordinate of the last tested chip on the target wafer when the measured data does not cover all chips on the target wafer, control the tester to test untested chips on a coordinate after the coordinate of the last tested chip, and sequentially test all untested chips on the target wafer according to the coordinate order, and upload the needle test data to the server in real time.
[0042] The wafer test system provided in the application obtains whether the target wafer is allowed to be retested by querying a server, when it is queried that the target wafer is not allowed to be retested, whether the measured data of the target wafer is in the server, and when the measured data cannot be queried, the chips on the target wafer are sequentially tested in the order of coordinates; when the measured data of the target wafer is queried, whether the measured data covers all the chips on the target wafer is further judged, when the measured data does not cover all the chips on the target wafer, the coordinates of the last measured chip on the target wafer are determined, the unmeasured chips on the coordinates after the coordinates of the last measured chip are controlled to be tested by the testing machine, all the unmeasured chips on the target wafer are sequentially tested in the order of coordinates, and the test data is uploaded to the server in real time, so that retesting of the measured chips on the target wafer is avoided, and quality abnormality of the wafer is avoided.
[0043] In one embodiment, the wafer test system further comprises: The determining module is configured to determine that the target wafer is a measured wafer when the measured data covers all the chips on the target wafer.
[0044] In one embodiment, the wafer test system further comprises: The information input module is configured to upload the batch number, process information and whether retesting is allowed of all the wafers to be tested to the server before the server determines whether the target wafer is allowed to be retested before the target wafer on the probe station is tested by the testing machine.
[0045] The wafer test system in the embodiment has the beneficial effects of the method embodiments, which will not be described herein.
[0046] Based on the same inventive concept, the application further provides an electronic device corresponding to the method of any of the above embodiments, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor executes the program to implement the wafer test method of any of the embodiments.
[0047] Figure 6 A more specific hardware structure of an electronic device provided in the embodiment is shown, which can include a processor 1101, a memory 1102, an input / output interface 1103, a communication interface 1104 and a bus 1105. The processor 1101, the memory 1102, the input / output interface 1103 and the communication interface 1104 are connected to each other through the bus 1105 for communication within the device.
[0048] The processor 1101 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits, etc., for executing relevant programs to implement the technical solutions provided by the embodiments of the present specification.
[0049] The memory 1102 can be implemented in the form of a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, etc. The memory 1102 can store an operating system and other application programs, and when the technical solutions provided by the embodiments of the present specification are implemented by software or firmware, the relevant program codes are stored in the memory 1102 and called and executed by the processor 1101.
[0050] The input / output interface 1103 is configured to connect an input / output module to implement information input and output. The input / output module can be configured as a component in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. The input device can include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device can include a display, a speaker, a vibrator, an indicator light, etc.
[0051] The communication interface 1104 is configured to connect a communication module (not shown in the figure) to implement the communication interaction between the device and other devices. The communication module can realize communication through a wired manner (such as USB, network cable, etc.) or through a wireless manner (such as mobile network, WIFI, Bluetooth, etc.).
[0052] The bus 1105 includes a channel for transmitting information between various components (such as the processor 1101, the memory 1102, the input / output interface 1103, and the communication interface 1104) of the device.
[0053] It should be noted that although the above device only shows the processor 1101, the memory 1102, the input / output interface 1103, the communication interface 1104, and the bus 1105, in the specific implementation process, the device can also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above device can also only include the components necessary to implement the solutions of the embodiments of the present specification, and does not have to include all the components shown in the figure.
[0054] The electronic device of the above embodiments is used to implement the wafer testing method of any of the above embodiments, and has the beneficial effects of the corresponding method embodiments, which are not repeated here.
[0055] Based on the same inventive concept, the present application also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the wafer testing method of any of the above embodiments.
[0056] The computer-readable medium of the present embodiments includes permanent and non-permanent, removable and non-removable media, which can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device.
[0057] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to perform the wafer testing method of any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which are not repeated here.
[0058] Those skilled in the art should understand that the above discussion of any of the embodiments is only exemplary and is not intended to imply that the scope (including claims) of the present application is limited to these examples; the above embodiments or technical features between different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of the aspects of the embodiments of the present application as described above. In order to be brief, they are not provided in detail.
[0059] Additionally, to simplify the description and discussion, and so as not to obscure the embodiments of the application being presented, the well-known functions or constructions of integrated circuit (IC) chips and other components can or can not be shown in the figures and will be omitted as not to unnecessarily obscure the embodiments of the application being presented. Moreover, the devices can be shown in block diagram form in order to avoid obscuring the embodiments of the application, and this also acknowledges the fact that the details in regard to how the devices are implemented in regard to the embodiments of the application are highly dependent on the platform within which the embodiments of the application are being implemented (i.e., these details should be readily apparent to those of ordinary skill in the art). Where specific details are set forth in order to describe an illustrative embodiment of the application, it will be apparent to one of ordinary skill in the art that the embodiments of the application can be practiced without, or with variation of, these specific details. Thus, the description is to be considered as illustrative and not restrictive, and the scope of the application should be determined not with reference to the above description, but should be given to the appended claims.
[0060] While the application has been described in connection with specific embodiments thereof, many alternatives, modifications and variations will be apparent to those of ordinary skill in the art. For example, other memory architectures (e.g., dynamic RAM (DRAM)) can use the embodiments discussed.
[0061] The embodiments of the application are intended to cover all such alternatives, modifications and variations as falling within the broad scope of the appended claims. Accordingly, any and all such modifications, variations or equivalents that fall within the spirit and scope of the embodiments of the application are intended to be included within the scope of the application.
Claims
1. A wafer testing method, characterized in that, include: Before the tester performs probe testing on the target wafer on the probe station, it queries the server to determine whether the target wafer is allowed to be retested. When the server finds that the target wafer is not allowed to be retested, it queries whether there is already tested data for the target wafer in the server. When the server cannot find the measured data of the target wafer, the control tester performs probe tests on the chips on the target wafer in the order of coordinates and uploads the probe test data to the server in real time. When the server retrieves the measured data of the target wafer, it determines whether the measured data covers all the chips on the target wafer. When the measured data does not cover all chips on the target wafer, the coordinates of the last chip under test on the target wafer are determined, and the test machine is controlled to perform probe testing on the untested chip at the coordinates after the coordinates of the last chip under test. Probe testing is then performed on all untested chips on the target wafer in sequence according to the coordinate order, and the probe test data is uploaded to the server in real time.
2. The wafer testing method according to claim 1, characterized in that, When the server retrieves the measured data of the target wafer, after determining whether the measured data covers all chips on the target wafer, the process further includes: When the measured data covers all chips on the target wafer, the target wafer is determined to be a measured wafer.
3. The wafer testing method according to claim 1, characterized in that, Before the tester performs probe testing on the target wafer on the probe station, and before querying the server to determine whether the target wafer is allowed to be retested, the process also includes: Upload the batch number, process information, and whether retesting is allowed for all wafers to be tested to the server; The query server, in determining whether the target wafer is permitted to undergo retesting, includes: An image of the target wafer is acquired, and the batch number of the target wafer is obtained based on the image. The batch number and process information of the target wafer are then used to query the server to determine whether the target wafer is allowed to be retested.
4. The wafer testing method according to claim 3, characterized in that, The query to see if the server has measured data for the target wafer includes: The server is queried based on the batch number, wafer number, and process information of the target wafer to determine if there is any measured data for the target wafer; wherein the measured data includes the coordinates of the chips on the target wafer.
5. The wafer testing method according to claim 3, characterized in that, After uploading the probe data to the server in real time, the method further includes: Integrate all test data of the target wafer to form a complete wafer map of the target wafer.
6. A wafer testing system, characterized in that, include: The first query module is used to query the server to determine whether the target wafer is allowed to be retested before the tester performs probe testing on the target wafer on the probe station. The second query module is used to query whether there is already measured data for the target wafer in the server when the server finds that the target wafer is not allowed to be retested. The probe testing module is used to control the testing machine to perform probe testing on the chips on the target wafer in the order of coordinates when the server cannot find the test data of the target wafer, and upload the probe testing data to the server in real time. The judgment module is used to determine whether the measured data of the target wafer covers all chips on the target wafer when the measured data of the target wafer is found in the server. The probe testing module is further configured to determine the coordinates of the last chip under test on the target wafer when the measured data does not cover all chips on the target wafer, and control the testing machine to perform probe testing on the untested chip at the coordinates after the coordinates of the last chip under test, and perform probe testing on all untested chips on the target wafer in sequence according to the coordinate order, and upload the probe testing data to the server in real time.
7. The wafer testing system according to claim 6, characterized in that, The wafer testing system also includes: The determination module is used to determine that the target wafer is a measured wafer when the measured data covers all chips on the target wafer.
8. The wafer testing system according to claim 6, characterized in that, The wafer testing system also includes: The pre-test information entry module is used to upload the batch number, process information, and whether retesting is allowed of all wafers to be tested to the server before the tester performs probe testing on the target wafer on the probe station and queries the server to determine whether the target wafer is allowed to be retested.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the wafer testing method as described in any one of claims 1 to 5.
10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the wafer testing method according to any one of claims 1 to 5.