Multifunctional airborne storage module

Abstract

The invention discloses a multifunctional airborne storage module, which comprises an FPGA (Field Programmable Gate Array), the FPGA is configured with Flash and is provided with three partitions, and acquisition and storage, data export and image excitation programs are respectively solidified; the mode switching circuit is in communication connection with the FPGA, sends a mode selection signal to the FPGA through an externally connected switching control panel, and reloads a program from a corresponding partition in the module operation process according to the mode selection signal; the storage unit is connected with the FPGA and is used for storing airborne data; the module integrates an Aurora, a 10-gigabit Ethernet and an RS422 interface, main control data is received in real time through the Aurora in the air, cached and written into an SSD, files are exported at a high speed through the 10-gigabit Ethernet on the ground, image data can be read out through the SSD during debugging and actively sent out according to an Aurora time sequence, and a main control system is simulated. According to the invention, three functions of acquisition and storage, data export and image excitation are realized based on the same hardware, external field equipment is reduced, and the maintenance efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of electronic information technology, and in particular to a multifunctional airborne storage module. Background Technology

[0002] Airborne data recording and playback are crucial aspects of avionics system testing, flight testing, and field troubleshooting. Common airborne storage modules typically employ an FPGA-high-speed interface-large-capacity non-volatile memory architecture. During flight, high-speed data such as telemetry, images, and radar data generated by the main control system are received in real-time via Aurora, PCIe, or Ethernet and written to the SSD without frame loss. On the ground, the recorded data is quickly exported to a host computer for post-event analysis, performance evaluation, or fault reproduction. With the increasing complexity of avionics systems, field support teams not only require storage modules to complete a closed-loop "record-export" process but also hope they can proactively output image data during ground debugging and load calibration to replace expensive and bulky dedicated exciters, thereby simplifying test equipment and shortening troubleshooting cycles.

[0003] However, current airborne storage modules generally adopt an architecture of FPGA + SSD + single-protocol interface; during flight: data is received from the main control system via Aurora or PCIe and written to the SSD; during ground maintenance: data is exported to the host computer via Gigabit Ethernet or USB 3.0. Existing technology has the following drawbacks: 1. The existing storage module architecture only supports recording and exporting, and does not have data stimulation capabilities. It cannot simulate the main control system sending image data to the outside during the ground debugging phase, which means that a dedicated exciter needs to be carried out for troubleshooting in the field, increasing the amount of equipment and the complexity of the assurance.

[0004] 2. Changing the working mode requires disassembling the device and reprogramming the FPGA image or replacing the entire device, which cannot achieve online switching in the field, resulting in low maintenance efficiency.

[0005] 3. Aurora is used in the air and Gigabit Ethernet is used on the ground. The two physical interfaces / protocol stacks cannot be reused, resulting in more connectors, more complex wiring, and increased weight and power consumption. In addition, the line rate of Aurora and the export rate of Gigabit Ethernet differ greatly. There is no hardware-level caching and flow control mechanism, which makes it easy for frame loss and overwriting to occur, resulting in incomplete data. Summary of the Invention

[0006] To address the above problems, this invention provides a multifunctional airborne storage module, the specific technical solution of which is as follows: Including FPGA, its configuration Flash is divided into a first partition, a second partition and a third partition. The first partition contains a data acquisition and storage program, the second partition contains a data export program, and the third partition contains an image excitation program. The mode switching circuit is communicatively connected to the FPGA. It sends a mode selection signal to the FPGA through an externally connected switching control board and reloads the program from the corresponding partition during module operation according to the mode selection signal. A storage unit, connected to the FPGA, stores onboard data; a first communication interface circuit, connected to the FPGA, interacts with the main control system in data acquisition and storage mode, and interacts with external devices in image excitation mode. The second communication interface circuit is connected to the FPGA and interacts with the host computer in data export mode. The third communication interface circuit is connected to the FPGA and receives control commands from the host computer in data export mode and image excitation mode.

[0007] Furthermore, the FPGA integrates a DDR cache control module; the DDR cache control module includes a frame packet assembly module, which frames the received data according to a predetermined length. The DDR cache management module manages the DDR cache data. The frame parsing module transforms the data in the DDR cache into its bit width and outputs it to the storage unit.

[0008] Furthermore, the FPGA also integrates an SSD management module; The SSD management module has the following states: idle state, identification state, file information state, user command waiting state, write file state, read file state, erase state, and file list state. Based on host commands, the system jumps between different states to read and write files in the storage unit, erase the entire disk, and record file information.

[0009] Furthermore, the execution logic for transitioning between different states is as follows: In idle state, wait for external device initialization to complete; After initialization, it enters the identification state to obtain the SSD disk size; and then enters the file information state to search the SSD file information storage area and obtain the latest storage location. Then it enters the user command waiting state, waiting for user commands or waiting for user data to be written; When external data needs to be written, it enters the file writing state and begins writing data to the SSD until it receives the current data packet completion signal, at which point it ends the current data writing and updates the contents of the file information storage area. When a user command to retrieve file information is received, the system enters file read mode and reads the contents of the SSD file information storage area. When a disk erase command is received, the disk enters the erase state and completes the erasure of the entire SSD disk. When a user's file read command is received, the system enters the file list state, retrieves the corresponding file content based on the passed file information, and outputs it.

[0010] Furthermore, the FPGA also integrates a network protocol module, a network data parsing module, and a network data transmission module; The network protocol module performs frame integrity detection and packet loss retransmission based on each protocol stack in data export mode. The network data parsing module parses the host computer commands into read, erase, or file list retrieval operations for the storage unit; The network data transmission module reads data from the storage unit, encapsulates it into Ethernet frames, and then sends it to the host computer.

[0011] Furthermore, the network protocol module includes a data preprocessing module, a network frame generation module, a data integrity detection module, and a received data parsing module; The specific execution logic is as follows: The data preprocessing module receives user data input, packages it according to length, MAC address, and IP address, and sends it to the network frame generation module. The network frame generation module receives information from each frame to be sent, generates a checksum value, forms a complete network frame, and sends it to the data integrity detection module via the network MAC. The data integrity detection module calculates the current frame length based on the received network frame, detects whether the current frame has errors, and transmits the network frame that passes the integrity detection to the received data parsing module. The received data parsing module parses the received network frames. If it is a frame that requires a response, the information is written into the network frame generation module. If not, the information is parsed out and output to the user.

[0012] Furthermore, the FPGA integrates an SSD management module; the SSD management module has: idle state, waiting state, file read state, erase state, file list state, and retransmission state; the network data parsing module parses the data from the host, generates SSD control information, and sends it to the SSD management module, switching between different states. The specific execution logic is as follows: In idle state, it waits for the external device to complete initialization and then enters the waiting state; Based on the SSD control information generated from the parsed data, if a user command to retrieve file information is received, the system enters the file read state and reads the contents of the SSD file information storage area. When a disk erase command is received, the disk enters the erase state and completes the erasure of the entire SSD disk. When a user's file read command is received, the system enters the file list state, retrieves the corresponding file content based on the passed file information, and outputs it. When a network retransmission command is received, the system enters retransmission mode, obtains retransmission information, and sends it to the network data sending module.

[0013] Furthermore, the network data sending module is internally equipped with a cache write state machine and a cache read state machine. The cache write state machine writes to 127 buffers in a loop and clears the write pointer after waiting for the host computer's response flag. The cache read state machine sets the read pointer to the retransmission address when it receives a retransmission instruction; otherwise, it increments the read pointer.

[0014] Furthermore, the FPGA also integrates an Aurora transmission control module, which receives data from the SSD, packages it according to the Aurora protocol, and sends it from the Aurora IP.

[0015] The beneficial effects of this invention are as follows: This invention utilizes a single hardware FPGA to configure three Flash partitions and switch modes to achieve three functions: data acquisition and storage, data export, and image excitation. Ground debugging does not require an additional exciter, reducing the need for field support equipment. Furthermore, by connecting an external control board and switching the operating mode control switch, the FPGA can be loaded from a specified partition, resulting in fast switching speeds, no need for disassembly, and significantly improved maintenance efficiency. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the storage module architecture of the present invention.

[0017] Figure 2 This is a schematic diagram of the data acquisition and storage functional framework of the present invention.

[0018] Figure 3 This is a functional logic diagram of the DDR cache control module of the present invention.

[0019] Figure 4 This is a schematic diagram of the state logic of the SSD management module of the present invention.

[0020] Figure 5 This is a schematic diagram of the data export function framework of the present invention.

[0021] Figure 6 This is a functional logic diagram of the network protocol processing module of the present invention.

[0022] Figure 7 This is a functional logic diagram of the network data parsing module of the present invention.

[0023] Figure 8 This is a schematic diagram of the functional framework of the network data sending module of the present invention.

[0024] Figure 9 This is a schematic diagram of the cache write control logic of the present invention.

[0025] Figure 10 This is a schematic diagram of the cache read control logic of the present invention.

[0026] Figure 11 This is a schematic diagram of the image excitation function framework of the present invention. Detailed Implementation

[0027] The technical solutions in the embodiments of the present invention are clearly and completely described in the following description. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0028] In the description of the embodiments of the present invention, it should be noted that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is conventionally placed during use, or the orientation or positional relationship in which those skilled in the art conventionally understand it during use. This is only for the convenience of describing the present invention and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of the present invention. Furthermore, the terms "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0029] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0030] Example 1 Embodiment 1 of the present invention discloses a multifunctional airborne storage module, such as Figure 1 As shown, the FPGA is configured with Flash memory physically divided into a first partition, a second partition, and a third partition. The first partition contains a data acquisition and storage program, the second partition contains a data export program, and the third partition contains an image excitation program. When the FPGA powers on, it loads the program from the first partition by default and executes the data acquisition and storage mode. The FPGA integrates a clock module and a power module.

[0031] It also includes: a mode switching circuit, which is communicatively connected to the FPGA and sends a mode selection signal to the FPGA through an externally connected switching control board, so that the FPGA loads the program from the first partition by default when it is powered on, or reloads the program from the second or third partition according to the mode selection signal during the operation of the module. The control board sends a single-byte mode code to the FPGA via the RS422 protocol. After the FPGA parses the mode code, it triggers a partial reconfiguration or a global reload to complete the mode switch without powering down the entire device.

[0032] It also includes: a storage unit connected to the FPGA to store onboard data, wherein the storage unit uses SSD storage.

[0033] It also includes: a first communication interface circuit, which is connected to the FPGA and at least supports the Aurora protocol, enabling high-speed data interaction with the main control system in data acquisition and storage mode, and high-speed data interaction with external devices in image excitation mode; The second communication interface circuit is connected to the FPGA and supports at least the 10 Gigabit Ethernet protocol, enabling high-speed data interaction with the host computer in data export mode. The third communication interface circuit is connected to the FPGA and supports at least the RS422 protocol, receiving control commands from the host computer in data export mode and image excitation mode.

[0034] When the FPGA runs the first partition program, it writes the data received through the first communication interface circuit into the storage unit after internal buffering and bit width transformation; when the second partition program runs, it sends the data in the storage unit to the host computer through the second communication interface circuit; when the third partition program runs, it actively sends the image data in the storage unit to an external device through the first communication interface circuit to simulate the behavior of the main control system.

[0035] Based on the above storage module, after power-on, the FPGA chip loads the data acquisition and storage program from the first partition, enters the data acquisition and storage mode, and receives data from the main control system in real time through the Aurora protocol and writes it into the storage unit. The first mode code is sent through the mode switching circuit. The FPGA chip loads the data export program from the second partition, enters the data export mode, and sends the specified file in the storage unit to the host computer through the 10 Gigabit Ethernet protocol. The second mode code is sent through the mode switching circuit. The FPGA chip loads the image stimulus program from the third partition and enters the image stimulus mode. The image data in the storage unit is actively sent to the external device frame by frame through the Aurora protocol to simulate the behavior of the main control system. Seamless switching of the three functions of acquisition, export and stimulus is realized on the same hardware platform.

[0036] like Figure 2 As shown, in a preferred embodiment, the FPGA integrates a DDR cache control module and an SSD management module, which are used to cache the parsed data in the data acquisition and storage mode, and store the cached data according to instructions. like Figure 3 As shown, the DDR cache control module includes a frame packet assembly module, which frames the data received via the Aurora protocol into frames of a predetermined length. The DDR cache management module schedules the read and write operations of DDR cache data. The frame parsing module converts the data in the DDR cache into bit width and outputs it to the SSD management module; Specifically, it also includes the MIG control module, which is used to meet the timing requirements of Xilinx MIG IP, thereby solving the problem of mismatch between Aurora's high-speed data stream and the write speed of storage units.

[0037] like Figure 4 As shown, the SSD management module has: idle state ST_IDLE, identification state ST_IDENT, file information state ST_FINFO, user command waiting state ST_UCMD, write file state ST_WFILE, read file state ST_GFLIST, erase state ST_ERASE, and file list state ST_RFILE. Based on host commands, the system jumps between different states to read and write files in the storage unit, erase the entire disk, and record file information to support fast retrieval and resume interrupted downloads.

[0038] In the data acquisition and storage mode, the execution logic for switching between different states is as follows: In idle state, wait for external device initialization to complete; After initialization, it enters the identification state, requests the IDENTIFY command to obtain the SSD disk size, and enters the file information state to search the SSD file information storage area to obtain the latest storage location. Then it enters the user command waiting state, waiting for user commands or waiting for user data to be written; When external data needs to be written, it enters the file writing state and begins writing data to the SSD until it receives the current data packet completion signal, at which point it ends the current data writing and updates the contents of the file information storage area. When a user command to retrieve file information is received, the system enters file read mode, reads the contents of the SSD file information storage area, and returns information such as the start and end addresses of the file and the file storage time. When a disk erase command is received, the disk enters the erase state and completes the erasure of the entire SSD disk. When a user's file read command is received, the system enters the file list state, retrieves the corresponding file content based on the passed file information, and outputs it.

[0039] As a preferred embodiment, such as Figure 5 As shown, the FPGA logic corresponding to the second communication interface circuit also includes: The network protocol module performs frame integrity detection and packet loss retransmission based on each protocol stack in data export mode. The network data parsing module parses the host computer commands into read, erase, or file list retrieval operations for the storage unit, that is, it parses and generates SSD control information. The network data transmission module encapsulates the data read from the storage unit into Ethernet frames and sends them to the host computer, completing functions such as user interaction data packet assembly and retransmission. This solves the data integrity and command response problems under the high-speed export of 10 Gigabit Ethernet, and enables functions such as receiving host commands, completing SSD reading and erasing operations, and completing status feedback in data export mode. The serial frame parsing module is used for the storage module and control software to interact via the serial port protocol.

[0040] As a preferred embodiment, such as Figure 6 As shown, the network protocol module includes a data preprocessing module, a network frame generation module, a data integrity detection module, and a received data parsing module; The specific execution logic is as follows: The data preprocessing module receives user data input, packages it according to length, MAC address, and IP address, and sends it to the network frame generation module. The network frame generation module receives information from each frame to be sent, generates a checksum, forms a complete network frame, and sends it to the data integrity detection module via the network MAC. The data integrity detection module calculates the current frame length based on the received network frame, detects whether the current frame has errors, and transmits the network frame that passes the integrity detection to the received data parsing module. The received data parsing module parses the received network frames. If the frame is an ICMP or ARP frame that requires a response, the information is written into the network frame generation module. If the frame is a UDP frame, it is parsed and output to the user.

[0041] The SSD management module also has a retransmission status; like Figure 7 As shown, in data export mode, the network data parsing module parses the data from the host, generates SSD control information, and sends it to the SSD management module, switching between different states. The specific execution logic is as follows: In the ST_IDLE idle state, it waits for external devices such as SATA and network to complete initialization, and then enters the ST_PARSE waiting state; Based on the SSD control information generated from the parsed data, if a user command to retrieve file information is received, the system enters the file read state ST_GFLIST, reads the contents of the SSD file information storage area, and returns information such as the start and end addresses of the file and the file storage time. When a disk erase command is received, it enters the erase state ST_ERASE and completes the erasure of the entire SSD disk. When a user's file read command is received, the system enters the file list state ST_RFILE, retrieves the corresponding file content based on the passed file information, and outputs it. When a network retransmission command is received, the system enters the retransmission state ST_RETRY, obtains retransmission information, and sends it to the network data sending module.

[0042] As a preferred embodiment, such as Figure 8 As shown, the network data sending module internally includes a cache write state machine and a cache read state machine. The cache write state machine writes data to 127 buffers in a loop and waits for the host computer's acknowledgment flag before clearing the write pointer. Figure 9 As shown, the specific process is as follows: WR_IDLE: Waiting for the SSD management module to input a number in the FIFO. Once the FIFO is not empty, proceed to the next state. WR_HEAD: Writes the interaction frame header to the current BUF; WR_WDAT: Reads data from the FIFO and writes the data to the corresponding buffer BUF. After writing the specified length of data, it enters the next state. WR_UPDAT: Updates the BUF write pointer and checks if the pointer is equal to 127. If it is, it enters WR_WAIT; otherwise, it enters WR_HEAD. WR_WAIT: Waits for the host to acknowledge the response. Once the acknowledgement is received, the write pointer is cleared to 0, and the program enters WR_IDLE.

[0043] The cache read state machine sets the read pointer to the retransmission address when it receives a retransmission instruction; otherwise, it increments the read pointer to achieve reliable transmission and retransmission functionality. Figure 10 As shown, the specific process is as follows: RD_IDLE: Wait for the buffer to become non-empty before proceeding to the next state; RD_RDAT: Reads data frames from the buffer and sends them to the network protocol module; RD_PCTL: Determines whether to retransmit. If retransmission is required, update the read pointer to the specified retransmission address, or increment the read address and enter RD_IDLE.

[0044] As a preferred embodiment, such as Figure 11 As shown, the FPGA also integrates an Aurora transmission control module. In image excitation mode, it receives data from the SSD, packages it according to the Aurora protocol, and sends it from the Aurora IP.

[0045] This invention is not limited to the specific embodiments described above. The invention extends to any new feature or combination disclosed in this specification, as well as any new method or process step or combination disclosed herein.

Claims

1. A multi-functional airborne storage module, characterized in that, Including FPGA, its configuration Flash is divided into a first partition, a second partition and a third partition. The first partition contains a data acquisition and storage program, the second partition contains a data export program, and the third partition contains an image excitation program. The mode switching circuit is communicatively connected to the FPGA. It sends a mode selection signal to the FPGA through an externally connected switching control board and reloads the program from the corresponding partition during module operation according to the mode selection signal. The storage unit is connected to the FPGA and stores onboard data; The first communication interface circuit is connected to the FPGA and interacts with the main control system in the data acquisition and storage mode, and interacts with external devices in the image excitation mode. The second communication interface circuit is connected to the FPGA and interacts with the host computer in data export mode. The third communication interface circuit is connected to the FPGA and receives control commands from the host computer in data export mode and image excitation mode.

2. The multifunctional airborne storage module according to claim 1, characterized in that, The FPGA integrates a DDR cache control module. The DDR cache control module includes a frame packet assembly module, which frames the received data according to a predetermined length. The DDR cache management module manages the DDR cache data. The frame parsing module transforms the data in the DDR cache into its bit width and outputs it to the storage unit.

3. The multifunctional airborne storage module according to claim 1, characterized in that, The FPGA also integrates an SSD management module. The SSD management module has the following states: idle state, identification state, file information state, user command waiting state, write file state, read file state, erase state, and file list state. Based on host commands, the system jumps between different states to read and write files in the storage unit, erase the entire disk, and record file information.

4. The multifunctional airborne storage module according to claim 3, characterized in that, The execution logic for transitioning between different states is as follows: In idle state, wait for external device initialization to complete; After initialization, it enters the identification state to obtain the SSD disk size; and then enters the file information state to search the SSD file information storage area and obtain the latest storage location. Then it enters the user command waiting state, waiting for user commands or waiting for user data to be written; When external data needs to be written, it enters the file writing state and begins writing data to the SSD until it receives the current data packet completion signal, at which point it ends the current data writing and updates the contents of the file information storage area. When a user command to retrieve file information is received, the system enters file read mode and reads the contents of the SSD file information storage area. When a disk erase command is received, the disk enters the erase state and completes the erasure of the entire SSD disk. When a user's file read command is received, the system enters the file list state, retrieves the corresponding file content based on the passed file information, and outputs it.

5. The multifunctional airborne storage module according to claim 1, characterized in that, The FPGA also integrates a network protocol module, a network data parsing module, and a network data sending module; The network protocol module performs frame integrity detection and packet loss retransmission based on each protocol stack in data export mode. The network data parsing module parses the host computer commands into read, erase, or file list retrieval operations for the storage unit; The network data transmission module reads data from the storage unit, encapsulates it into Ethernet frames, and then sends it to the host computer.

6. The multifunctional airborne storage module according to claim 5, characterized in that, The network protocol module includes a data preprocessing module, a network frame generation module, a data integrity detection module, and a received data parsing module; The specific execution logic is as follows: The data preprocessing module receives user data input, packages it according to length, MAC address, and IP address, and sends it to the network frame generation module. The network frame generation module receives information from each frame to be sent, generates a checksum value, forms a complete network frame, and sends it to the data integrity detection module via the network MAC. The data integrity detection module calculates the current frame length based on the received network frame, detects whether the current frame has errors, and transmits the network frame that passes the integrity detection to the received data parsing module. The received data parsing module parses the received network frames. If it is a frame that requires a response, the information is written into the network frame generation module. If not, the information is parsed out and output to the user.

7. The multifunctional airborne storage module according to claim 5, characterized in that, The FPGA integrates an SSD management module; the SSD management module has the following states: idle, waiting, file read, erase, file list, and retransmission; the network data parsing module parses the data from the host, generates SSD control information, and sends it to the SSD module, switching between different states. The specific execution logic is as follows: In idle state, it waits for the external device to complete initialization and then enters the waiting state; Based on the SSD control information generated from the parsed data, if a user command to retrieve file information is received, the system enters the file read state and reads the contents of the SSD file information storage area. When a disk erase command is received, the disk enters the erase state and completes the erasure of the entire SSD disk. When a user's file read command is received, the system enters the file list state, retrieves the corresponding file content based on the passed file information, and outputs it. When a network retransmission command is received, the system enters retransmission mode, obtains retransmission information, and sends it to the network data sending module.

8. The multifunctional airborne storage module according to claim 5, characterized in that, The network data sending module is internally equipped with a cache write state machine and a cache read state machine. The cache write state machine writes to 127 buffers in a loop and clears the write pointer after waiting for the host computer's response flag. The cache read state machine sets the read pointer to the retransmission address when it receives a retransmission instruction, otherwise it increments the read pointer.

9. The multifunctional airborne storage module according to claim 1, characterized in that, The FPGA also integrates an Aurora transmit control module, which receives data from the SSD, packages it according to the Aurora protocol, and sends it from the Aurora IP.

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