SSD PCIe link self-adaptive link establishment method and related equipment

Abstract

The invention provides an SSD PCIe link adaptive link establishment method and related equipment, and the method comprises the steps: in a link training stage, detecting a training sequence sent by an opposite terminal PCIe port on all available physical channels, and analyzing logic channel number information from the training sequence; dynamically constructing a mapping relation between the logic channel and the physical channel based on the analyzed logic channel number information; according to the mapping relation, configuring a corresponding logic channel number for each physical channel of the local data to be sent; and generating and sending a training sequence on a corresponding physical channel by using the configured logical channel number so as to complete link training negotiation with an opposite end. The method has the advantages that the mapping relation is reconstructed in a dynamic self-adaption mode, and it is ensured that the logic link is successfully established on any available physical channel.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive link failure handling technology, and in particular to an SSD PCIe link adaptive link establishment method and related equipment. Background Technology

[0002] With the widespread adoption of solid-state drives (SSDs) in data centers and high-performance computing, the reliability of their high-speed data interaction with the host via the PCIe bus has become crucial. In actual deployments, SSDs require frequent hot-swapping for maintenance or replacement, a process that can cause physical wear on the SSD's PCIe interface gold fingers and the server hard drive bay's connector gold fingers. This wear can trigger a hardware failure known as Lane Break, where the electrical connection of one or more physical lanes in the PCIe link breaks, while the other physical lanes on the link remain intact.

[0003] Currently, while the standard PCIe Link Training and State Machine (LTSSM) protocol defines the basic process of link training, it is insufficient in handling asymmetric lane break failures. Especially in existing SSD implementations, the mapping between logical lanes (lane numbers) and physical lanes is usually fixed and preset. For example, logical lane 0 is associated with and can only be associated with physical lane 0 by default. This rigid mapping mechanism has a significant drawback: when the physical lane experiencing a lane break happens to be the logical master lane (such as the physical lane 0 to which logical lane 0 is fixed), even though other intact physical lanes may exist on the link, the entire link training negotiation process will fail because the logical master lane cannot migrate to these available lanes, resulting in the device being unable to recognize it.

[0004] Therefore, the main problem with existing technologies is their inability to dynamically and adaptively reconstruct the mapping relationship between logical and physical channels in failure scenarios where some physical channels are damaged. This not only reduces the robustness of the PCIe link but also affects the overall availability and reliability of the storage system by causing complete disk failure even in the event of non-serious hardware failures. The industry urgently needs a solution that can intelligently handle Lane Break failures, maximize the utilization of remaining intact channels, and successfully establish stable links. Summary of the Invention

[0005] The technical problem to be solved by this invention is the failure of link establishment caused by the fixed mapping relationship between logical channels and physical channels when a partial physical channel hardware failure occurs in the PCIe link of existing SSDs.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: an adaptive link establishment method for SSD PCIe links, comprising the following steps: During the link training phase, the training sequences sent by the peer PCIe port on all available physical channels are detected, and the logical channel number information is parsed from them. Based on the parsed logical channel number information, a mapping relationship between logical channels and physical channels is dynamically constructed; Based on the mapping relationship, configure a corresponding logical channel number for each physical channel of data to be sent locally; Using the configured logical channel number, a training sequence is generated and sent on the corresponding physical channel to complete the link training negotiation with the peer.

[0007] Furthermore, the step of dynamically constructing the mapping relationship between logical channels and physical channels based on the parsed logical channel number information includes: In the Configuration.LinkNum.wait state of the link training state machine, start a timer; During the operation of the timer, the logical channel numbers in the training sequences received from all available physical channels are monitored and recorded; The correspondence between each logical channel number and the physical channel that received that number is stored in a mapping register.

[0008] Furthermore, the mapping register is a bitmap register, where each bit represents a physical channel, and the state of the bit is used to indicate whether it is associated with a specific logical channel.

[0009] Furthermore, after storing the correspondence between each logical channel number and the physical channel in the mapping register, the following steps are executed after the timer expires: Read the mapping register to determine whether the register value representing the main logic channel is valid; If the register value representing the main logic channel is invalid, continue sending training sequences without configured logic channel numbers on all physical channels; If the register value representing the main logic channel is valid, the final link width is determined based on the mapping relationship register.

[0010] Furthermore, determining the final link width based on the mapping relationship register includes: If only the main logical channel is valid, then the link width is determined to be x1; If the primary and secondary logical channels are valid, but the higher-order logical channels are invalid, then the link width is determined to be x2. If the main logic channel and all higher-order logic channels are valid, then the link width is determined to be x4.

[0011] Furthermore, the step of generating and sending training sequences on the corresponding physical channels using the configured logical channel number specifically includes: sending a training sequence carrying the corresponding logical channel number on each valid physical channel indicated by the mapping relationship, according to the determined link width.

[0012] The present invention also provides an SSD PCIe link adaptive connection establishment device, comprising: The detection module is used to detect the training sequences sent by the peer PCIe port on all available physical channels during the link training phase, and to parse the logical channel number information from them. The mapping construction module is used to dynamically construct the mapping relationship between logical channels and physical channels based on the parsed logical channel number information; The channel configuration module is used to configure a corresponding logical channel number for each physical channel of data to be sent locally, according to the mapping relationship. The training sequence sending module is used to generate and send training sequences on the corresponding physical channels using the configured logical channel numbers, so as to complete the link training negotiation with the peer.

[0013] Furthermore, the mapping construction module is specifically used for: Start the timer in the Configuration.LinkNum.wait state of the link training state machine; During the operation of the timer, the logical channel numbers in the training sequences received from all available physical channels are monitored and recorded; The correspondence between each logical channel number and the physical channel that received that number is stored in a mapping register.

[0014] The present invention also provides a computer device, the computer device including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the SSD PCIe link adaptive connection establishment method as described above.

[0015] The present invention also provides a storage medium storing a computer program, which, when executed by a processor, can implement the SSD PCIe link adaptive connection establishment method as described above.

[0016] The beneficial effects of this invention are as follows: by dynamically constructing and applying the mapping relationship between logical channels and physical channels, adaptive link reconstruction is achieved when a partial channel hardware failure occurs in the PCIe link. It can effectively utilize all available physical channel resources, ensure accurate alignment of logical channels with the peer device, thereby significantly improving the success rate of link training and the quality of the finally established link, and enhancing the robustness and reliability of SSD under non-ideal hardware connection conditions. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating the overall process of adaptively identifying the relationship between logical lanes and physical lanes and establishing a link, as described in this embodiment of the invention. Figure 2 This is a flowchart of adaptive link establishment based on the logical lane matrix register in an embodiment of the present invention; Figure 3 This is a diagram showing the relationship between the logical lane matrix register and the physical lane in an embodiment of the present invention. Figure 4 This is a link diagram of the SSD establishing a link to x4 under normal conditions when no LaneBreak failure occurs, according to an embodiment of the present invention. Figure 5 This is a link diagram for establishing a link to x2 when an SSD experiences a LaneBreak failure, as described in this embodiment of the invention. Figure 6 The link diagram for establishing a link to x1 when the SSD experiences a LaneBreak failure is shown in this embodiment of the invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that the descriptions involving "first," "second," etc., in this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Furthermore, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0021] Explanation of technical terms: (1) PCIe: Peripheral Component Interconnect Express, a high-speed peripheral interconnect interface.

[0022] (2) USP: PCIe protocol term, PCIe upstream port, PCIe port of SSD, or PCIe port of PCIe Switch chip near RC chip.

[0023] (3) DSP: PCIe protocol term, PCIe downstream port, PCIe port of the server host RC chip, or PCIe port of the PCIeSwitch chip on the side away from the RC chip.

[0024] (4) TX: PCIe protocol term, short for the Transmitter of PCIe port.

[0025] (5) RX: PCIe protocol term, short for Receiver of PCIe port.

[0026] (6) Lane number: PCIe protocol term, channel number.

[0027] (7) Link number: PCIe protocol term, link number.

[0028] (8) TS1: A link training bitstream specified by the PCIe protocol.

[0029] (9) Logical lane: PCIelan / full-duplex path with logical lane numbering distinguished by the lane number of TS1 code stream.

[0030] (10) Physical lane: PCIe lane / full-duplex path determined by PCB silkscreen.

[0031] (11) Lane Break: Describes a hardware connection failure that occurs in one or more physical lanes of a PCIe link in the TX direction, RX direction, or TX and RX direction.

[0032] (12) Logical lane0 / 1 / 2 / 3 matrix register: Stores the correspondence between logical lane0 / 1 / 2 / 3 and physical lane0 / 1 / 2 / 3. When a lane break fault occurs, the value of this register can be used to ensure optimal link establishment.

[0033] (13) Detect, Polling, Configuration, Configuration.LinkWidth.Start, Configuration.LinkWidth.Accept, Configuration.LinkNum.wait, Configuration.LinkWidth.Accept: PCIe protocol terms, which are LTSSM state names.

[0034] like Figure 1 As shown, an embodiment of the present invention is: an adaptive link establishment method for SSD PCIe links, comprising the following steps: S1. During the link training phase, detect the training sequences sent by the peer PCIe port on all available physical channels and parse out the logical channel number information from them.

[0035] S2. Based on the parsed logical channel number information, dynamically construct the mapping relationship between logical channels and physical channels.

[0036] Specifically, the dynamic construction of the mapping relationship between logical channels and physical channels based on the parsed logical channel number information includes: S21. In the Configuration.LinkNum.wait state of the link training state machine, start a timer.

[0037] In this embodiment, the timeout period of the timer is set to T microseconds, which provides a stable time window for the establishment of the relationship matrix.

[0038] S22. During the operation of the timer, listen to and record the logical channel numbers in the training sequences received from all available physical channels.

[0039] S23. Store the correspondence between each logical channel number and the physical channel that received the number in a mapping register.

[0040] Specifically, the mapping register is a bitmap register, where each bit represents a physical channel, and the state of the bit is used to indicate whether it is associated with a specific logical channel.

[0041] In this embodiment, the mapping register adopts a bitmap structure, such as... Figure 3 As shown, each bit represents a physical channel. For example, a register value of 0001 for logical lane0 indicates that a TS1 stream from the peer was received on physical lane0 and Lane Number = 0; a value of 0010 indicates that Lane Number = 1 was received on physical lane1. This bitmap representation clearly records the correspondence between logical lanes and physical lanes. A register value of 0 indicates that this logical lane is not associated with any physical lane.

[0042] Specifically, after storing the correspondence between each logical channel number and the physical channel in the mapping register, the following steps are executed after the timer expires: Read the mapping register to determine whether the register value representing the main logic channel is valid; If the register value representing the main logic channel is invalid, continue sending training sequences without configured logic channel numbers on all physical channels; If the register value representing the main logic channel is valid, the final link width is determined based on the mapping relationship register.

[0043] Specifically, determining the final link width based on the mapping relationship register includes: If only the main logical channel is valid, then the link width is determined to be x1; If the primary and secondary logical channels are valid, but the higher-order logical channels are invalid, then the link width is determined to be x2. If the main logic channel and all higher-order logic channels are valid, then the link width is determined to be x4.

[0044] Specifically, such as Figure 2 As shown, after the timer expires, the adaptive link establishment process based on the relationship matrix begins: First, the relationship matrix between logical lanes and physical lanes is scanned to determine whether the matrix register value of the logical main lane (i.e., logical lane0) is 0. In this embodiment, if the register value of logical lane0 is 0, it indicates that all physical lanes are disconnected or have not received the TS1 stream from the peer logical main lane. In this case, link establishment is not possible, and all physical lanes continue to send the TS1 stream with Lane Number PAD until the protocol times out. If the register value is not 0, it indicates that link establishment is possible, and the subsequent link width determination process continues.

[0045] In this embodiment, the link width determination process specifically includes: determining whether the matrix register value of logical lane1 is 0; if it is 0, the link width is determined to be x1; if logical lane1 exists and the register values ​​of logical lane2 and lane3 are all non-zero, the link width is determined to be x4; otherwise, the link width is determined to be x2. This determination mechanism can adaptively select the optimal link width based on the actual number of available logical lanes.

[0046] S3. Based on the mapping relationship, configure the corresponding logical channel number for each physical channel of data to be sent locally.

[0047] S4. Using the configured logical channel number, generate and send training sequences on the corresponding physical channel to complete the link training negotiation with the peer.

[0048] In this embodiment, in the Configuration.LinkNum.wait state, port TX sends TS1 streams to all available physical lanes. At this time, the Link Number is set to a valid value and matches the Link Number received in the Configuration.LinkWidth.Accept state, but the Lane Number is set to PAD. After the timer expires, based on the established relationship matrix, the Lane Number value of the TS1 stream sent by the corresponding physical lane is changed from PAD to the corresponding logical lane number.

[0049] Specifically, the step of generating and sending training sequences on the corresponding physical channels using the configured logical channel number includes: sending a training sequence carrying the corresponding logical channel number on each valid physical channel indicated by the mapping relationship, based on the determined link width.

[0050] In this embodiment, as Figure 4 As shown, under normal circumstances without a LaneBreak failure, successful x4 link establishment can be achieved by detecting the peer TS1 on all available physical lanes and establishing a complete relationship matrix. Figure 5 As shown, when Lane 2 fails, the correct TS1 is adaptively sent on physical lanes 0 and 1 via the relation matrix, allowing a link width of x2 to be established. Figure 6 As shown, when Lanes 0, 1, and 2 all fail, sending the correct TS1 on the only available physical lane 3 via the relation matrix still successfully establishes a link of width x1. This design ensures successful link establishment as long as logical lane 0 exists, effectively solving the Lane Break failure problem caused by wear on the gold fingers.

[0051] This embodiment also considers special application scenarios. When there is a flip board on the hardware link or the lane order of the PCIe port on the other end is flipped, this method can adaptively send the TS1 code stream carrying the correct lane number on the corresponding physical lane, which enhances the applicability and robustness of the solution.

[0052] This invention also provides an SSD PCIe link adaptive connection establishment device, comprising: The detection module is used to detect the training sequences sent by the peer PCIe port on all available physical channels during the link training phase, and to parse the logical channel number information from them. The mapping construction module is used to dynamically construct the mapping relationship between logical channels and physical channels based on the parsed logical channel number information; The channel configuration module is used to configure a corresponding logical channel number for each physical channel of data to be sent locally, according to the mapping relationship. The training sequence sending module is used to generate and send training sequences on the corresponding physical channels using the configured logical channel numbers, so as to complete the link training negotiation with the peer.

[0053] Specifically, the mapping construction module is used for: Start the timer in the Configuration.LinkNum.wait state of the link training state machine; During the operation of the timer, the logical channel numbers in the training sequences received from all available physical channels are monitored and recorded; The correspondence between each logical channel number and the physical channel that received that number is stored in a mapping register.

[0054] In this embodiment, the mapping construction module is also responsible for scanning the relation matrix after the timer expires, determining the final link width based on the value of the logical lane0 / 1 / 2 / 3 matrix register, and guiding the training sequence sending module to send the TS1 code stream with the correct Lane Number on the corresponding physical lane.

[0055] This invention also provides a computer device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the SSDPCIe link adaptive connection establishment method as described above.

[0056] This invention also provides a storage medium storing a computer program, which, when executed by a processor, can implement the SSD PCIe link adaptive connection establishment method as described above.

[0057] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. An adaptive link establishment method for SSD PCIe links, characterized in that, Includes the following steps: During the link training phase, the training sequences sent by the peer PCIe port on all available physical channels are detected, and the logical channel number information is parsed from them. Based on the parsed logical channel number information, a mapping relationship between logical channels and physical channels is dynamically constructed; Based on the mapping relationship, configure a corresponding logical channel number for each physical channel of data to be sent locally; Using the configured logical channel number, a training sequence is generated and sent on the corresponding physical channel to complete the link training negotiation with the peer.

2. The SSD PCIe link adaptive connection establishment method according to claim 1, characterized in that, The dynamic construction of the mapping relationship between logical channels and physical channels based on the parsed logical channel number information includes: In the Configuration.LinkNum.wait state of the link training state machine, start a timer; During the operation of the timer, the logical channel numbers in the training sequences received from all available physical channels are monitored and recorded; The correspondence between each logical channel number and the physical channel that received that number is stored in a mapping register.

3. The SSD PCIe link adaptive connection establishment method according to claim 2, characterized in that, The mapping register is a bitmap register, where each bit represents a physical channel, and the state of the bit is used to indicate whether it is associated with a specific logical channel.

4. The SSD PCIe link adaptive connection establishment method according to claim 2, characterized in that, After storing the correspondence between each logical channel number and the physical channel in the mapping register, the following steps are executed after the timer expires: Read the mapping register to determine whether the register value representing the main logic channel is valid; If the register value representing the main logic channel is invalid, continue sending training sequences without configured logic channel numbers on all physical channels; If the register value representing the main logic channel is valid, the final link width is determined based on the mapping relationship register.

5. The SSD PCIe link adaptive connection establishment method according to claim 4, characterized in that, Determining the final link width based on the mapping relationship register includes: If only the main logical channel is valid, then the link width is determined to be x1; If the primary and secondary logical channels are valid, but the higher-order logical channels are invalid, then the link width is determined to be x2. If the main logic channel and all higher-order logic channels are valid, then the link width is determined to be x4.

6. The SSD PCIe link adaptive connection establishment method according to claim 1, characterized in that, The step of generating and sending training sequences on the corresponding physical channels using the configured logical channel number specifically includes: sending a training sequence carrying the corresponding logical channel number on each valid physical channel indicated by the mapping relationship, according to the determined link width.

7. An SSD PCIe link adaptive connection establishment device, characterized in that, include: The detection module is used to detect the training sequences sent by the peer PCIe port on all available physical channels during the link training phase, and to parse the logical channel number information from them. The mapping construction module is used to dynamically construct the mapping relationship between logical channels and physical channels based on the parsed logical channel number information; The channel configuration module is used to configure a corresponding logical channel number for each physical channel of data to be sent locally, according to the mapping relationship. The training sequence sending module is used to generate and send training sequences on the corresponding physical channels using the configured logical channel numbers, so as to complete the link training negotiation with the peer.

8. The SSD PCIe link adaptive connection establishment device according to claim 7, characterized in that, The mapping construction module is specifically used for: Start the timer in the Configuration.LinkNum.wait state of the link training state machine; During the operation of the timer, the logical channel numbers in the training sequences received from all available physical channels are monitored and recorded; The correspondence between each logical channel number and the physical channel that received that number is stored in a mapping register.

9. A computer device, characterized in that, The computer device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the SSD PCIe link adaptive connection establishment method as described in any one of claims 1 to 6.

10. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, can implement the SSD PCIe link adaptive connection establishment method as described in any one of claims 1 to 6.

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