Automatic power-on and power-off test system and method

Abstract

The invention provides an automatic power-on and power-off test system and method. The automatic power-on and power-off test system comprises an upper computer, a single-chip microcomputer system connected with the upper computer, and a storage chip, a power switch and a power monitor chip which are connected with the single-chip microcomputer system. The upper computer and the single-chip microcomputer system are connected with a tested device. The power switch and the power monitor chip are connected with a tested device. The upper computer is used for sending a control instruction including test parameters to the single-chip microcomputer system. The single-chip microcomputer system is used for controlling the power switch and the power monitor chip to complete power-on and power-off tests on the tested equipment according to the control instruction, and the power switch is used for controlling the on-off of the power supply of the tested equipment according to the instruction of the single-chip microcomputer system; the power monitor chip is used for acquiring test data of operation of the tested equipment according to an instruction of the single-chip microcomputer system; and the storage chip is used for storing test parameters and test data of the tested equipment. According to the invention, a complex and configurable power-on and power-off test cycle can be automatically executed through research and development and mass production stages.

Description

Technical Field

[0001] This invention relates to the field of equipment testing, and more specifically, to an automatic power-on / power-off testing system. Background Technology

[0002] Modern electronic products (such as computers and communication devices based on SOCs, FPGAs, and multi-core processors) are becoming increasingly functional, and their hardware and software systems are becoming more complex. Power-on and power-off testing is a crucial step in ensuring product reliability, safety, and stability during their design and manufacturing. Currently, power-on and power-off testing presents significant differences and common challenges at different stages of product development.

[0003] During the R&D verification phase, testing focuses on identifying design flaws and requires in-depth, iterative, and often destructive testing of complex scenarios such as power parameters, inrush current, and abnormal power outages. This process relies on professional engineers manually debugging and analyzing using precision instruments (such as programmable power supplies and oscilloscopes), which results in low efficiency, poor consistency, and high labor costs.

[0004] During the mass production screening phase, the testing objective shifts to quickly eliminating manufacturing defects, typically involving only basic short-circuit testing, power consumption measurement, and simple power-on / off cycles. Limited by testing efficiency and cost pressures, it's difficult to simulate the complex and stringent power state switching scenarios verified during the R&D phase, resulting in some potential quality issues not being effectively identified and resolved before leaving the factory.

[0005] Currently, power-on / power-off testing of equipment is typically performed manually. A typical operating procedure is as follows: If the device under test (DUT) has an interface such as a console serial port or Ethernet port, connect this port to a host computer; assess the load voltage and current, and then set the power supply's output voltage and protection current accordingly; then press the power switch and observe the power supply voltage and current, as well as the information printed by the host computer's serial port or Ethernet port, during the device's power-on startup process; if the voltage, current, and information displayed by the host computer's serial port or Ethernet port are all normal during the device's power-on startup, wait for the DUT to complete startup and run for a period of time. If the power supply voltage and current, as well as the information displayed by the host computer's serial port or Ethernet port, are all normal during this period, then the DUT is considered to have successfully powered on; finally, turn off the power to complete one power-on test. After powering off the DUT for a period of time, turn the power back on and repeat the above power-on test. This manual operation of power-on / off testing requires manually operating the power switch, visually observing voltage and current readings, serial port or Ethernet port information, and mentally judging whether the measured values ​​and information are normal, making the entire testing process extremely inefficient. For embedded devices with high reliability requirements, occasional power-on failures must be avoided. Therefore, such devices need to undergo extreme power-on / off testing. During repeated manual power-on and power-off cycles, especially when the intervals between power-on and power-off are very short, operators are prone to misjudgment, i.e., overlooking occasional power-on failures.

[0006] In summary, current technologies lack a system capable of automating complex and configurable power-on and power-off test cycles throughout the R&D and mass production stages. This leads to a trade-off between test coverage and efficiency, resulting in insufficient or costly verification of product power supply reliability. Summary of the Invention

[0007] To address the aforementioned problems, this invention provides an automatic power-on / power-off testing system and method, enabling automated execution of complex and configurable power-on / power-off testing cycles throughout the R&D and mass production stages.

[0008] In a first aspect, the present invention provides an automatic power-on and power-off testing system, comprising a host computer, a microcontroller system connected to the host computer, and a memory chip, a power switch, and a power monitor chip connected to the microcontroller system; the host computer and the microcontroller system are connected to the device under test; the power switch and the power monitor chip are connected to the device under test. The host computer is used to send control commands, including test parameters, to the microcontroller system; The microcontroller system is used to control the power switch and power monitor chip to perform power-on and power-off tests on the device under test according to control commands. The power switch is used to control the power supply to the device under test according to the instructions of the microcontroller system; The power monitor chip is used to acquire test data of the device under test according to the instructions of the microcontroller system; The memory chip is used to store the test parameters and test data of the device under test.

[0009] In a preferred embodiment, the host computer and the microcontroller system are connected to the device under test via a branched cable, so that the data transmitted between the device under test and the host computer during power-on is also received and monitored by the microcontroller system.

[0010] In a preferred embodiment, the host computer is connected to the microcontroller system via an Ethernet port, serial port, or USB interface.

[0011] In a preferred embodiment, the USB interface is also used to provide DC power to the microcontroller system, memory chip, and power monitor chip; and this DC power is independent of the power supply of the device under test.

[0012] In a preferred embodiment, the automatic power-on / power-off test system further includes a test indicator for displaying the test process, test errors, and test results.

[0013] In a preferred embodiment, the test indicator includes a light-emitting diode and a buzzer, used to indicate the test process, test errors, and test results through different light and sound signals.

[0014] In a preferred embodiment, the automatic power-on / power-off test system further includes a protection circuit; the protection circuit is connected to the power MOSFET U3 and is used to protect the power supply path of the device under test; the protection circuit includes a gas discharge tube, a varistor, a transient voltage suppression diode, and a fast recovery diode connected in parallel.

[0015] Secondly, the present invention provides an automatic power-on / power-off testing method, implemented based on the aforementioned automatic power-on / power-off testing system, the method comprising: Perform system initialization; The system reads the stored test parameters from the memory chip and prints the system information and test parameters; the system information indicates the available control commands. Wait for user input to modify test parameters, and start automatic power-on and power-off testing based on the saved test parameters; Initiate automatic power-on / power-off testing, using a state machine for looping. The loop process is as follows: IDLE->POWERING_UP->STABILIZING->MEASURING->POWERING_DOWM; among them, In IDLE state, check the test time and test parameters; In POWERING_UP state, power on and record time; In STABILIZING mode, wait for the power supply to stabilize; In MEASURING state, measure the current, voltage, and power of the device under test according to the set measurement interval, monitor the serial port data of the device under test console, and check for overcurrent, undercurrent, and abnormal serial port data volume; if so, jump to POWERING_DOWN and mark failure; if all are negative, continue to measure the current, voltage, and power of the device under test in MEASURING state according to the set measurement interval until the set single power-on time ends, and then jump to POWERING_DOWN state; In the POWERING_DOWM state, power is turned off to the device under test, the test validity is checked, and the test statistics are updated. If it is the first failure, subsequent power-on and power-off tests are stopped. After the power-on test is completed, the power-off period lasts for a period of time set by the power-on and power-off interval in the test parameters before starting the next power-on test; the power-on and power-off test is repeated until the set total power-on and power-off time ends. After the power-on and power-off tests are completed, the final results are printed and saved to the memory chip.

[0016] In a preferred embodiment, the states of LED D1 and buzzer B1 are updated during and after the power-on / power-off test: During the power-on and power-off test, if normal, the LED D1 will slowly flash and the buzzer B1 will sound at a low frequency to indicate that the test is in progress. The test will also print the current, voltage, and power, as well as statistical data during the test, including test time, number of power-on attempts, number of successes, number of failures, and pass rate. After the power-on and power-off tests are completed, the LED D1 will remain constantly lit and the buzzer B1 will sound continuously to indicate that the test has passed. The LED D1 will flash rapidly and the buzzer B1 will sound at a high frequency to indicate that the test has failed.

[0017] In a preferred embodiment, when the microcontroller system is running, it can receive and immediately execute control commands sent by the user through the host computer, regardless of which stage the automatic power-on / power-off test is in.

[0018] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: 1. This invention performs automatic power-on and power-off tests based on user-set test parameters, measures the current, voltage, and power of the device under test, monitors the serial port data of the device under test, and judges the measurement results. It can realize complex and configurable power-on and power-off test cycles that can be automatically executed throughout the R&D and mass production stages.

[0019] 2. This invention uses a microcontroller system to control the power supply of the device under test. The microcontroller system receives and executes control commands sent by the user through a host computer. When the automatic power-on / power-off test system interacts with the user, it prompts the user with available control commands through system prompts, which facilitates operation and ensures efficient completion of automatic power-on / power-off tests.

[0020] 3. The serial port of the device under test (DUT) in this invention is connected to the microcontroller system and the host computer via a branched cable, enabling parallel serial port monitoring. This allows the microcontroller system to receive and monitor the data transmitted via serial port during the DUT's power-on startup. After the microcontroller system initiates the power-on test of the DUT, it monitors the data transmitted via serial port during the DUT's power-on startup according to the time and data volume set in the test parameters "serial port monitoring time" and "serial port monitoring data volume". If the serial port data volume is a single digit or all data is 00 or FF within the set time, it can be determined that the DUT's power-on startup is abnormal, replacing the need for human observation of the DUT's power-on print information and manual judgment of whether the DUT's power-on startup is normal.

[0021] 4. Compared to manual power-on and power-off testing of the device under test (DUT), which requires both manual operation of the power switch and visual observation of the voltage, current, and serial port information printed on the DUT's control panel, the current-voltage and current-current tests are inefficient and prone to overlooking occasional power-on failures during rapid power-on / off cycles. This invention's microcontroller system uses power MOSFETs to turn the DUT's power supply on and off, eliminating the need for manual operation of an external power switch. A power monitor chip measures the DUT's current, voltage, and power, comparing these values ​​to normal settings to identify abnormalities such as power-on failures or potential short-circuit faults. If an abnormality is detected, the power-on test is stopped, the DUT's power supply is shut off, and alarm feedback is provided through printed prompts, rapid flashing of LEDs, and a high-frequency buzzer.

[0022] 5. The microcontroller system of this invention runs an automatic power-on / power-off test program, supporting the setting and saving of test parameters. Especially for embedded devices with high reliability requirements, during extreme power-on / power-off tests, if manual operation of the power switch is used, the shortest power-on / power-off interval is measured in seconds. This invention achieves a power-on / power-off interval measured in milliseconds, making it more suitable for conducting rapid power switching tests on such devices. This invention has no limit on the single power-on time or the total power-on / power-off time, making it particularly suitable for long-term stability testing of devices over days. Therefore, this invention uses a microcontroller system to run an automatic power-on / power-off test program, allowing for flexible setting of test parameters and automatic power-on / power-off testing. It offers significant advantages such as high testing efficiency, controllable testing process, detailed test data, and intuitive error alarms. Attached Figure Description

[0023] Figure 1 The present invention provides a schematic diagram of an automatic power-on / power-off testing system.

[0024] Figure 2a This is a circuit diagram of a microcontroller system in an embodiment of the present invention.

[0025] Figure 2b This is a schematic diagram of the power supply circuit of the device under test in an embodiment of the present invention.

[0026] Figure 2c This is a circuit schematic diagram of the power monitor chip U2 in an embodiment of the present invention.

[0027] Figure 2d This is a circuit schematic diagram of the memory chip U1 in an embodiment of the present invention.

[0028] Figure 2e This is a circuit diagram of the protection circuit in an embodiment of the present invention.

[0029] Figure 3 The flowchart illustrates an automatic power-on / power-off testing method provided in this embodiment of the invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0031] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0032] like Figure 1 As shown, this embodiment of the invention provides an automatic power-on / power-off testing system, including a host computer, a microcontroller system connected to the host computer, and a memory chip, a power switch, and a power monitor chip connected to the microcontroller system; the host computer and the microcontroller system are connected to the device under test; the power switch and the power monitor chip are connected to the device under test. The host computer is used to send control commands, including test parameters, to the microcontroller system; The microcontroller system is used to control the power switch and power monitor chip to perform power-on and power-off tests on the device under test according to control commands. The power switch is used to control the power supply to the device under test according to the instructions of the microcontroller system; The power monitor chip is used to acquire test data of the device under test according to the instructions of the microcontroller system; The memory chip is used to store the test parameters and test data of the device under test.

[0033] The following details the implementation of the aforementioned automatic power-on / power-off test system.

[0034] like Figure 2a The diagram shows the circuit schematic of the microcontroller system. The host computer connects to the microcontroller system J3 via Ethernet port J1, serial port J4, or USB interface J5. It receives control commands sent by the user through the host computer, executes these commands, and feeds back status information to the host computer through the aforementioned interfaces, enabling interaction between the computer and the user. Furthermore, USB interface J5 also provides +5V DC power to the microcontroller system J3, memory chip U1, and power monitor chip U2. This DC power supply is independent of the power supply to the device under test (DUT), avoiding interference with the +5V when controlling the power supply to the DUT, thus preventing impact on measurement accuracy and the stability of the test system.

[0035] The microcontroller system J3 is connected to the device under test via serial port J2 and a branched cable. Specifically, the branched cable has three serial port connectors. The host computer, the microcontroller system J3, and the device under test are connected via the branched cable. The serial port transmit signals TX, the serial port receive signals RX, and the ground wires GND of the branched cable are connected in parallel. This allows the data transmitted between the device under test and the host computer during power-on to be received and monitored by the microcontroller system. In addition, the automatic power-on / power-off test system also includes test indicators, such as LED D1 and buzzer B1, used to indicate the test process, test errors, and test results through different light and sound signals. Specifically, the microcontroller system J3 is connected to LED D1 and buzzer B1 via GPIO signals STATUS and BUZZ, respectively. The STATUS and BUZZ signals output fixed high or low levels or square waves of different frequencies, causing LED D1 to be constantly lit, off, flashing slowly, or flashing rapidly, and buzzer B1 to be constantly sounding, silent, beating at low frequencies, or beating at high frequencies, ensuring intuitive feedback on the test process, test errors, and test results. For example, a constantly lit LED D1 indicates a successful test, while an off LED D1 indicates the test has not yet started; a difference in the sound frequency of buzzer B1 indicates the test is in progress or a test error, a constantly sounding buzzer B1 indicates a successful test, and a silent buzzer B1 indicates the test has not yet started.

[0036] like Figure 2b The diagram shows the power supply circuit schematic of the device under test (DUT). An external power supply is connected to the input terminal of a power switch via power input terminal J6. The output terminal of the power switch is connected to the DUT via power output terminal J7 to supply power to the DUT. The control terminal of the power switch is connected to a microcontroller system to control the power supply to the DUT according to instructions from the microcontroller system. In this embodiment, the power switch uses a power MOSFET U3. Taking a PMOS transistor as an example, the source of the power MOSFET U3 is the input terminal of the power switch, the drain of the power MOSFET U3 is the output terminal of the power switch, and the gate of the power MOSFET U3 is the control terminal of the power switch. Specifically: The GPIO signal SBC_VCC_EN of the microcontroller system is connected to the gate of the signal field-effect transistor Q1 (taking an NMOS transistor as an example). The source of the signal field-effect transistor Q1 is grounded. The drain of the signal field-effect transistor Q1 is connected to the gate of the power field-effect transistor U3 via resistor R15, and to the drain of the power field-effect transistor U3 via resistor R16 and capacitor C8. The gate of the power field-effect transistor U3 is also connected to the source of the power field-effect transistor U3 via resistor R14. The external power input terminal J6 provides voltage VCC, which is connected to the source of the power field-effect transistor U3. The drain of the field-effect transistor U3 provides voltage SBC_VCC via resistors R12 and R13 in parallel, and then connects to the power supply terminal of the device under test via the power output terminal J7. Its working principle is as follows: When the GPIO signal SBC_VCC_EN of the microcontroller system J3 is low, the signal field-effect transistor Q1 is cut off, and one end of resistor R15 is floating. Therefore, resistor R15 does not perform a voltage divider function, so the voltage across resistor R14 is VCC. Consequently, the gate and source voltages of the power field-effect transistor U3 are both VCC, and its gate-source voltage V... GS The value is 0, which does not meet the conduction condition of power MOSFET U3. Therefore, power MOSFET U3 is in the cut-off state, and the power supply to the device under test is turned off. When the GPIO signal SBC_VCC_EN of the microcontroller system J3 is high, the signal field-effect transistor Q1 is turned on, and one end of resistor R15 is grounded. Therefore, resistor R15 acts as a voltage divider, so the voltage at one end of resistor R14 is voltage VCC. The voltage at the other end of resistor R14 is obtained by the voltage divider between resistors R14 and R15, resulting in the gate-source voltage V of the power field-effect transistor U3. GS The gate-source voltage V is less than 0 (by appropriately selecting the values ​​of resistors R14 and R15). GS (It can be set to a more ideal value) to meet the conduction condition of power MOSFET U3, so power MOSFET U3 is in the conducting state, and the power supply of the device under test is turned on at this time.

[0037] like Figure 2c The diagram shows the circuit schematic of the power monitor chip U2. Resistors R12 and R13, connected in parallel, serve as sampling resistors in series within the power supply path of the device under test (DUT). The ends of resistors R12 and R13 are connected to analog input pins 9 and 10 of the power monitor chip U2 via series resistors R10 and R11, respectively. The power supply voltage VBUS is connected to analog input pin 8 of the power monitor chip U2. Resistors R12 and R13 convert current into voltage. The use of two sampling resistors in parallel accommodates situations where the DUT requires a large current. In such cases, the high current increases the power consumption and temperature of the sampling resistors. This increased current is shared between the two sampling resistors, effectively avoiding the impact of temperature rise on resistor accuracy and ensuring the accuracy of current, voltage, and power measurements.

[0038] The power monitor chip U2 processes the analog voltage signals input through its analog input pins 8, 9, and 10, performing noise reduction, amplification, analog-to-digital conversion, and calculations internally to obtain the current, voltage, and power of the device under test. For example, the power monitor chip converts the current in the power supply path of the device under test into a voltage through a sampling resistor, inputs it to the power monitor chip U2 through analog input pins 9 and 10, processes it internally to restore it to current, and directly obtains the voltage of the power supply path of the device under test through analog input pin 8. The power is then calculated from the current and voltage to obtain the power of the power supply path of the device under test. The microcontroller system J3 is connected to the power monitor chip U2 via the IIC bus signals C_SDA and C_SCL. The microcontroller system J3 uses the IIC bus to configure the measurement parameters of the power monitor chip U2, correct the measurement data, control the start / stop of the measurement, and read the measured current, voltage and power.

[0039] like Figure 2d The diagram shows the circuit schematic of the memory chip. In this embodiment of the invention, the memory chip is an EEPROM chip U1. The microcontroller system J3 is connected to the EEPROM chip U1 via the IIC bus signals E_SDA and E_SCL to store test parameters and test results, ensuring data is not lost even when power is off. The test parameters can be queried and modified, and the test results can also be queried. The test parameters include normal current, voltage, and power; single power-on time; power-on / power-off interval; current, voltage, and power measurement interval; total power-on / power-off time; serial port monitoring time; and serial port monitoring data volume. By default, the microcontroller system J3 starts the automatic power-on / power-off test of the device under test after reading the test parameters from the EEPROM chip.

[0040] like Figure 2e The diagram shows the circuit schematic of the protection circuit. The protection circuit is connected to the power MOSFET U3. Specifically, the protection circuit includes a gas discharge tube G1, a varistor R17, a transient voltage suppressor diode D2 (TVS), and a fast recovery diode D3 connected in parallel. These components protect the power supply path of the device under test, eliminating back electromotive force and voltage spikes caused by rapid power supply switching. Specifically, the fast recovery diode D3 forms a freewheeling loop near the power output terminal, ensuring rapid energy discharge; the transient voltage suppressor diode D2 clamps the back electromotive force voltage to a safe value, ensuring it does not exceed the maximum withstand voltage of the drain of the power MOSFET U3; the gas discharge tube G1 and the varistor R17 provide additional protection for the power MOSFET U3.

[0041] The above Figure 2a , Figure 2b , Figure 2c , Figure 2d , Figure 2e Some components are appropriately configured based on the functional implementation of the aforementioned circuit, and will not be elaborated upon here. For example... Figure 2a Resistors R6 and R8 are included. Figure 2b The capacitors C4, C5, C6, C7, C9, and pull-down resistor R18 are included. Figure 2cThe components are capacitor C2, capacitor C3, resistor R4, resistor R5, resistor R7, and resistor R9. Figure 2d The components include capacitor C1, resistor R1, resistor R2, and resistor R3.

[0042] like Figure 3 As shown, the process for performing power-on / power-off tests based on the above-mentioned automatic power-on / power-off test system is as follows: First, perform system initialization: Set the GPIO signals SBC_VCC_EN, STATUS, and BUZZ of the single-chip microcomputer system J3 to turn off the power supply to the device under test, turn off the LED D1, and mute the buzzer B1. Initialize the power monitor chip U2 to complete the measurement parameter configuration and measurement data calibration; Initialize the USB interface (if connected to the host computer via USB interface), and set the USB to CDC communication mode; initialize the communication serial port (if connected to the host computer via serial port), and set serial port parameters such as baud rate and data bits; initialize the communication Ethernet port (if connected to the host computer via Ethernet port), and set Ethernet port parameters such as MAC and IP address; initialize the monitoring serial port connected to the device under test, and set serial port parameters such as baud rate and data bits. Then, the stored test parameters are read from the memory chip, and system information and test parameters are printed. The system information prompts available control commands, enabling the automatic power-on / power-off testing system to provide rich information during user interaction, facilitating operation and ensuring efficient completion of the automatic power-on / power-off testing of the device under test. The control commands include: S: Stop the test. R: Restart the test. C: Modify parameters. P: Printing status, H: Display help; Then, wait for user input (C to modify parameters, or exit after 5 seconds or when the user presses Enter to exit), and start automatic power-on and power-off testing according to the saved test parameters; Initiate automatic power-on / power-off testing, using a state machine for looping. The loop process is as follows: IDLE->POWERING_UP->STABILIZING->MEASURING->POWERING_DOWM; among them, (1) In IDLE state, check the test time and test parameters; (2) In POWERING_UP state, turn on the power and record the time; (3) In STABILIZING state, wait for the power supply to stabilize; (4) In MEASURING state, measure the current, voltage, and power of the device under test according to the measurement interval set in the test parameter "Current, Voltage, and Power Measurement Interval". Monitor the serial port data of the device under test console and check for overcurrent (≥2 times the normal current), undercurrent (milliampere level), and serial port data volume that is a single digit, all data is 00, or FF. If so, jump to POWERING_DOWN and mark as failed; for example: if the normal current is set to amperes but the measured current is milliamperes, it can be determined that the device under test has not started, print a message indicating that the device under test has not started, stop the power-on test and turn off the power supply to the device under test, and provide alarm feedback through the rapid flashing of the LED and the high-frequency sounding of the buzzer; if the measured current is more than twice the normal current, it can be determined that there is a suspected short circuit or the normal current is set too low, print the message "Suspected short circuit or the normal current is set too low, please eliminate the short circuit or set the normal current before continuing the test", stop the power-on test and turn off the power supply to the device under test, and provide alarm feedback through the LED flashing rapidly and the buzzer sounding at a high frequency; The LED flashes rapidly and the buzzer sounds at a high frequency to provide alarm feedback. When the measured value reaches more than 10% of the set normal value, the measurement is considered valid, and subsequent power-on tests continue. The serial port data transmitted during the power-on startup of the device under test is monitored according to the time and data volume set by the test parameters "serial port monitoring time" and "serial port monitoring data volume". If the serial port data volume is a single digit or all data is 00 or FF within the set time, it can be determined that the power-on startup of the device under test is abnormal. A prompt message indicating that the device under test has not started is printed, the power-on test is stopped, the power supply to the device under test is turned off, and the LED flashes rapidly and the buzzer sounds at a high frequency to provide alarm feedback.

[0043] If all are negative, continue measuring the current, voltage, and power of the device under test in the MEASURING state at the set measurement interval until the set single power-on time ends, and then jump to the POWERING_DOWN state. (5) In the POWERING_DOWM state, turn off the power supply to the device under test, check the test validity, update the test statistics (pass / fail count), and stop subsequent power-on and power-off tests if it is the first failure. After this round of power-on test is completed, the power-off period lasts for an interval set by the test parameter "Power-on / Power-off Interval" before starting the next round of power-on test. The power-on / power-off test is repeated until the set "Total Power-on / Power-off Time" expires. During the power-on / power-off test, the test will stop if the user requests a stop (S command), or if a test fails (overcurrent, undercurrent, or abnormal serial port data being monitored). After the power-on and power-off tests are completed, the final results are printed and saved to the memory chip.

[0044] During the power-on / power-off test, if normal, the test will be indicated by the slow flashing of LED D1 and a low-frequency beeping of buzzer B1. The system will also print the current, voltage, and power readings, as well as statistical data including test time, number of power-on cycles, number of successes, number of failures, and pass rate. After the power-on / power-off test is completed, a continuous light from LED D1 and a constant beep from buzzer B1 will indicate a successful test. A rapid flashing of LED D1 and a high-frequency beep from buzzer B1 will indicate a failed test.

[0045] When the J3 microcontroller system is running, it can receive and immediately execute control commands sent by the user through the host computer, regardless of the stage of the automatic power-on / power-off test. This ensures that test parameters can be modified, tests can be started, and tests can be stopped at any time, thus efficiently completing the automatic power-on / power-off test.

[0046] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An automatic power-on / power-off testing system, characterized in that, It includes a host computer, a microcontroller system connected to the host computer, and a memory chip, a power switch, and a power monitor chip connected to the microcontroller system; the host computer and the microcontroller system are connected to the device under test; the power switch and the power monitor chip are connected to the device under test. The host computer is used to send control commands, including test parameters, to the microcontroller system; The microcontroller system is used to control the power switch and power monitor chip to perform power-on and power-off tests on the device under test according to control commands. The power switch is used to control the power supply to the device under test according to the instructions of the microcontroller system; The power monitor chip is used to acquire test data of the device under test according to the instructions of the microcontroller system; The memory chip is used to store the test parameters and test data of the device under test.

2. The automatic power-on / power-off testing system according to claim 1, characterized in that, The host computer and the microcontroller system are connected to the device under test via a branched cable, so that the data transmitted between the device under test and the host computer during power-on is also received and monitored by the microcontroller system.

3. The automatic power-on / power-off testing system according to claim 1, characterized in that, The host computer is connected to the microcontroller system via an Ethernet port, serial port, or USB interface.

4. The automatic power-on / power-off testing system according to claim 3, characterized in that, The USB interface is also used to provide DC power to microcontroller systems, memory chips, and power monitor chips; and this DC power is independent of the power supply of the device under test.

5. The automatic power-on / power-off testing system according to claim 1, characterized in that, The automatic power-on / power-off test system also includes a test indicator to indicate the test process, test errors, and test results.

6. The automatic power-on / power-off testing system according to claim 5, characterized in that, The test indicator includes an LED and a buzzer, used to indicate the test process, test errors, and test results through different light and sound signals.

7. The automatic power-on / power-off testing system according to claim 1, characterized in that, It also includes a protection circuit; the protection circuit is connected to the power MOSFET U3 and is used to protect the power supply path of the device under test; the protection circuit includes a gas discharge tube, a varistor, a transient voltage suppression diode and a fast recovery diode connected in parallel.

8. An automatic power-on / power-off testing method, implemented based on the automatic power-on / power-off testing system according to any one of claims 1-7, characterized in that, The method includes: Perform system initialization; The system reads the stored test parameters from the memory chip and prints the system information and test parameters; the system information indicates the available control commands. Wait for user input to modify test parameters, and start automatic power-on and power-off testing based on the saved test parameters; Initiate automatic power-on / power-off testing, using a state machine for looping. The loop process is as follows: IDLE->POWERING_UP->STABILIZING->MEASURING->POWERING_DOWM; among them, In IDLE state, check the test time and test parameters; In POWERING_UP state, power on and record time; In STABILIZING mode, wait for the power supply to stabilize; In MEASURING state, measure the current, voltage, and power of the device under test according to the set measurement interval, monitor the serial port data of the device under test console, and check for overcurrent, undercurrent, and abnormal serial port data volume; if so, jump to POWERING_DOWN and mark failure; if all are negative, continue to measure the current, voltage, and power of the device under test in MEASURING state according to the set measurement interval until the set single power-on time ends, and then jump to POWERING_DOWN state; In the POWERING_DOWM state, power is turned off to the device under test, the test validity is checked, and the test statistics are updated. If it is the first failure, subsequent power-on and power-off tests are stopped. After the power-on test is completed, the power-off period lasts for a period of time set by the power-on and power-off interval in the test parameters before starting the next power-on test; the power-on and power-off test is repeated until the set total power-on and power-off time ends. After the power-on and power-off tests are completed, the final results are printed and saved to the memory chip.

9. The automatic power-on / power-off testing method according to claim 8, characterized in that, Update the status of LED D1 and buzzer B1 during and after the power-on / power-off test: During the power-on and power-off test, if normal, the LED D1 will slowly flash and the buzzer B1 will sound at a low frequency to indicate that the test is in progress. The test will also print the current, voltage, and power, as well as statistical data during the test, including test time, number of power-on attempts, number of successes, number of failures, and pass rate. After the power-on and power-off tests are completed, the LED D1 will remain constantly lit and the buzzer B1 will sound continuously to indicate that the test has passed. The LED D1 will flash rapidly and the buzzer B1 will sound at a high frequency to indicate that the test has failed.

10. The automatic power-on / power-off testing method according to claim 8, characterized in that, When the microcontroller system is running, it can receive and immediately execute control commands sent by the user through the host computer, regardless of which stage the automatic power-on / power-off test is in.

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