Board card signal test method, test equipment and electronic equipment

Abstract

The invention discloses a board card signal testing method, testing equipment and electronic equipment, and relates to the field of computers.The method comprises the steps that a request for testing a board card signal detection function of a server mainboard is received, and the board card signal detection function is used for recognizing a server board card connected to the server mainboard; the test request is responded, a test signal conforming to the target electrical characteristic is generated, under the condition that the server board card belongs to the target board card type, the server board card has the target electrical characteristic, and the test signal is used for simulating the plugging operation of the server board card on the board card interface of the server mainboard; sending a test signal to the board card interface, and detecting server information generated when the server mainboard responds to the test signal; and testing a board card signal detection function of the server mainboard according to the test signal and the server information. The technical problem that the test efficiency of the board card signal is low is solved, and the technical effect of improving the test efficiency of the board card signal is achieved.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically, to a method, testing equipment, and electronic equipment for testing board signals. Background Technology

[0002] During the development, production, and maintenance phases of servers, the signal detection function of the board interface is crucial to ensuring the stable operation of the server system. The server motherboard needs to be able to accurately identify the presence status of the expansion card inserted into the interface in order to carry out subsequent resource allocation and initialization work.

[0003] In related technologies, testing the signal detection function of board interfaces typically involves physical insertion and removal of components. Testers need to move actual physical components and manually insert and remove them repeatedly from the expansion slots to trigger in-situ detection signals and verify the server's recognition accuracy. This method has significant drawbacks: firstly, relying on physical components for testing leads to high resource consumption and is prone to component damage during high-frequency insertion and removal; secondly, manual operation is inefficient and cannot simulate specific electrical timing sequences such as rapid continuous insertion and removal and signal jitter, resulting in insufficient test coverage and difficulty in detecting potential signal detection problems under extreme timing conditions.

[0004] No effective solution has yet been proposed to address the technical problems of low testing efficiency for board signals in related technologies. Summary of the Invention

[0005] This application provides a method, equipment, and electronic device for testing board signals, in order to at least solve the technical problems of low testing efficiency of board signals in related technologies.

[0006] According to one embodiment of this application, a method for testing board signals is provided, comprising:

[0007] Receive a test request, wherein the test request is used to request a test of the board signal detection function of the server motherboard, and the board signal detection function is used to identify the server boards connected to the server motherboard;

[0008] In response to the test request, a test signal conforming to the target electrical characteristics is generated. If the server board belongs to the target board type, then the server board has the target electrical characteristics. The test signal is used to simulate the insertion and removal operation of the server board on the board interface of the server motherboard.

[0009] Send test signals to the board interface and detect the server information generated by the server motherboard in response to the test signals;

[0010] The board signal detection function of the server motherboard is tested based on the test signals and server information.

[0011] According to another embodiment of the present application, a test apparatus for board signals is also provided, comprising:

[0012] The receiving module is used to receive test requests, wherein the test requests are used to request the testing of the board signal detection function of the server motherboard, and the board signal detection function is used to identify the server boards connected to the server motherboard.

[0013] The generation module is used to respond to test requests and generate test signals that conform to the target electrical characteristics. If the server board belongs to the target board type, then the server board has the target electrical characteristics. The test signals are used to simulate the insertion and removal operations of the server board on the board interface of the server motherboard.

[0014] The sending module is used to send test signals to the board interface and detect the server information generated by the server motherboard in response to the test signals;

[0015] The test module is used to test the board signal detection function of the server motherboard based on test signals and server information.

[0016] This application also provides a board signal testing device, including: a tester, a signal interface and an information interface, wherein the tester is connected to both the signal interface and the information interface, the signal interface is used to connect to the board interface of the server motherboard under test, and the information interface is used to connect to the server motherboard.

[0017] The tester receives test requests, which in turn request testing of the server motherboard's board signal detection function. This board signal detection function identifies server boards connected to the server motherboard. In response to the test requests, the tester generates test signals that conform to the target electrical characteristics. If the server board belongs to the target board type, then the server board possesses the target electrical characteristics. The test signals simulate the insertion and removal operations of the server board on the board interface. The tester sends test signals to the board interface via a signal interface and detects the server information generated by the server motherboard in response to the test signals via an information interface. Finally, the tester tests the server motherboard's board signal detection function based on the test signals and the server information.

[0018] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the test method for any of the above-described board signals.

[0019] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the test method for any of the above-described board signals.

[0020] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the test method for any of the above-described board signals.

[0021] This application first receives a test request for the signal detection function of a server motherboard board; then, without relying on the server board itself, it generates a test signal that conforms to the target electrical characteristics of the server board type; next, it sends the test signal to the board interface and detects the server information generated by the server motherboard in response to the test signal; finally, it tests the signal detection function of the server motherboard board based on the sent test signal and the feedback server information. By using a test signal conforming to the target electrical characteristics to replace the physical plugging and unplugging of the physical server board, the testing process is freed from dependence on physical components, avoiding the hardware damage and high manpower consumption caused by frequent physical plugging and unplugging in the prior art. This achieves low-cost, high-efficiency, and safe and reliable board signal detection, thus solving the technical problem of low board signal testing efficiency in related technologies and achieving the technical effect of improving the testing efficiency of board signals. Attached Figure Description

[0022] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a hardware structure block diagram of a computer device for a method of testing board signals according to an embodiment of this application;

[0024] Figure 2 This is a flowchart of a method for testing board signals according to an embodiment of this application;

[0025] Figure 3 This is a structural frame of a board signal testing device according to an embodiment of this application. Figure 1 ;

[0026] Figure 4 This is a structural frame of a board signal testing device according to an embodiment of this application. Figure 2 ;

[0027] Figure 5 This is a structural frame of a board signal testing device according to an embodiment of this application. Figure 3 ;

[0028] Figure 6 This is a structural block diagram of a board signal testing device according to an embodiment of this application;

[0029] Figure 7 This is a schematic diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0031] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0032] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] The methods and embodiments provided in this application can be executed on a server device or a similar computing device. Taking running on a server device as an example, Figure 1 This is a hardware structure block diagram of a computer device for a method of testing board signals according to an embodiment of this application. For example... Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the image. A processor 102 (which may include, but is not limited to, a central processing unit (CPU), microprocessor (MCU), or programmable logic device (FPGA), etc.) and a memory 104 for storing data are also shown. The server device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the server equipment described above. For example, the server equipment may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0034] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the board signal testing method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to server devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0035] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the server device. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0036] This embodiment provides a method for testing board signals. Figure 2 This is a flowchart of a method for testing board signals according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps:

[0037] Step S12, receive a test request, wherein the test request is used to request a test of the board signal detection function of the server motherboard, and the board signal detection function is used to identify the server boards connected to the server motherboard.

[0038] Step S14: Respond to the test request and generate a test signal that conforms to the target electrical characteristics. If the server board belongs to the target board type, then the server board has the target electrical characteristics. The test signal is used to simulate the insertion and removal operation of the server board on the board interface of the server motherboard.

[0039] Step S16: Send a test signal to the board interface and detect the server information generated by the server motherboard in response to the test signal;

[0040] Step S18: Test the board signal detection function of the server motherboard based on the test signal and server information.

[0041] This application first receives a test request for the signal detection function of a server motherboard board; then, without relying on the server board itself, it generates a test signal that conforms to the target electrical characteristics of the server board type; next, it sends the test signal to the board interface and detects the server information generated by the server motherboard in response to the test signal; finally, it tests the signal detection function of the server motherboard board based on the sent test signal and the feedback server information. By using a test signal conforming to the target electrical characteristics to replace the physical plugging and unplugging of the physical server board, the testing process is freed from dependence on physical components, avoiding the hardware damage and high manpower consumption caused by frequent physical plugging and unplugging in the prior art. This achieves low-cost, high-efficiency, and safe and reliable board signal detection, thus solving the technical problem of low board signal testing efficiency in related technologies and achieving the technical effect of improving the testing efficiency of board signals.

[0042] Optionally, in this embodiment, the server motherboard may be, but is not limited to, an Artificial Intelligence (AI) server motherboard, a general-purpose computing server motherboard, or a storage server motherboard. The server motherboard may be in a bare board state or in a complete machine state installed in a chassis. The board type may include, but is not limited to, a Graphics Processing Unit (GPU) card, a network interface card, a Redundant Array of Independent Disks (RAID) card, a Peripheral Component Interconnect Express (PCIe) switch board, or server head unit components, etc. The differences in board types mainly lie in their corresponding physical interface forms and electrical characteristics. The specific type of the target board may be one or more of the above-mentioned board types. The board signal detection function is used to identify the presence or reset state of the above-mentioned board on the server motherboard.

[0043] In the embodiment provided in step S12 above, receiving a test request can be, but is not limited to, receiving it through a human-machine interface on the test device, such as physical buttons or touch commands on a touchscreen; it can also be, but is not limited to, receiving automated test commands from a host computer through a communication interface, such as sending them through a universal asynchronous receiver / transmitter, Ethernet port, or universal serial bus. It should be noted that the test request can include specific test parameters, such as the number of simulated plugging / unplugging operations and the frequency.

[0044] In the embodiment provided in step S14 above, generating a test signal that conforms to the target electrical characteristics may include, but is not limited to, obtaining it by looking up a table through the microcontroller unit (MCU) or complex programmable logic device (CPLD) built into the test equipment. The target electrical characteristics may include, but are not limited to, the high and low level thresholds of the signal, the timing parameters of the signal (such as rise time, pulse width), and the drive current capability. It should be noted that the target board type determines the electrical characteristics that need to be simulated in subsequent steps; different board types may correspond to different pin definitions or level standards (such as 3.3V or 1.8V logic).

[0045] Optionally, in this embodiment, the test signal may be, but is not limited to, a voltage pulse sequence, such as a "high-level-low-high-level" changing sequence, or a square wave signal containing specific frequency jitter. Simulating the insertion and removal of server boards on the server motherboard's board interface can, but is not limited to, simulating the physical contact process through changes in electrical signals. For example, sending a low-level signal to simulate board insertion (assuming low level is active) and sending a high-level signal to simulate board removal. The target electrical characteristics may also include simulation of signal setup and hold times to verify the motherboard's detection capabilities under extreme timing conditions. It should be noted that "simulation" here specifically refers to electrical-level simulation, not mechanical-level physical insertion and removal. After the test equipment is connected to the motherboard via a connector, it remains physically stationary, only changing the electrical signal states of the pins to deceive the server motherboard's main control logic.

[0046] Optionally, in this embodiment, the board interface may be, but is not limited to, an interface that matches a server board of the target board type, such as a standard PCIe slot (e.g., x16, x8 slot), a high-density interconnect interface, or an M.2 interface. Sending a test signal to the board interface may, but is not limited to, injecting a generated pulse signal into a "presence detection pin" (e.g., PRESENT# pin) defined by the board interface. It should be noted that sending the test signal and detecting server information are usually parallel processes or time-correlated processes. For example, information may be detected within a preset time window after the signal is sent.

[0047] In the embodiment provided in step S16 above, the server information generated by the server motherboard's response to the test signal can be read, but is not limited to, through an out-of-band management interface or a debug serial port. The server information may include, but is not limited to, system event logs generated by the Baseboard Management Controller (BMC), sensor readings, CPLD register status values, etc. It should be noted that the server information not only includes the final identification result (such as "GPU connected"), but may also include intermediate state information (such as "Pin level transition interrupt detected") for more precise debugging.

[0048] In the embodiment provided in step S18 above, testing the board signal detection function of the server motherboard based on the test signal and server information can be achieved, but is not limited to, by comparing logical consistency. For example, the timing logic of the test signal (such as simulating insertion at time T1) can be compared with the event record in the server information (such as recording "Slot1 Present" at time T1+Δt).

[0049] Optionally, in this embodiment, the test results may include, but are not limited to, "functionally normal," "functionally faulty," "response delay," or "signal jitter false alarm." It should be noted that if no corresponding log is found in the server information, or if the log record status is opposite to the status of the sent test signal, the board's signal detection function is determined to be faulty.

[0050] As an optional approach, generating test signals that conform to the target electrical characteristics includes:

[0051] S21, Extract the target electrical characteristics corresponding to the target board type from the board types and electrical characteristics that have a corresponding relationship;

[0052] S22, Generate a target pulse sequence as a test signal, wherein the high-level signal in the target pulse sequence conforms to the target electrical characteristics, the high-level signal in the target pulse sequence is used to indicate that the server board is in place on the board interface, and the low-level signal in the target pulse sequence is used to indicate that the server board is not in place on the board interface.

[0053] Optionally, in this embodiment, extracting the target electrical characteristics corresponding to the target board type can be achieved, but is not limited to, by reading the configuration file stored in the internal storage medium of the test equipment. The mapping relationship can be stored in the form of a lookup table, a key-value database, or structured text (such as JSON or XML). It should be noted that the electrical characteristic data in the mapping relationship supports dynamic updates. For example, support for new board models can be added by issuing new configuration files from a host computer without replacing the test equipment hardware.

[0054] Optionally, in this embodiment, the extraction operation may, but is not limited to, indexing the corresponding electrical parameter set in the configuration file based on the board type identifier carried in the test request. This parameter set may, but is not limited to, include logic level voltage standards (such as 1.8V, 3.3V), drive current magnitude, and signal setup / hold time requirements. It should be noted that the extraction process may also include a data verification step to ensure that the stored electrical characteristic parameters are not corrupted and are within the coverage of the test equipment's hardware capabilities.

[0055] Optionally, in this embodiment, generating the target pulse sequence as a test signal can be achieved, but is not limited to, using the MCU's general-purpose input / output (GPIO) pins for level toggling, using a pulse width modulation module to output a modulated waveform, or outputting an analog voltage waveform via a digital-to-analog converter. The target pulse sequence can be, but is not limited to, a step signal simulating a single insertion / removal, or a periodic square wave signal simulating multiple consecutive insertions / removals. It should be noted that the target pulse sequence not only includes stable high and low levels, but may also include glitches intentionally generated to test the motherboard's anti-interference capability or critical width pulses generated to test timing boundaries.

[0056] Optionally, in this embodiment, a high-level signal may refer to, but is not limited to, a signal whose voltage amplitude is within the high-level logic threshold range defined by the target electrical characteristics; a low-level signal may refer to, but is not limited to, a signal whose voltage amplitude is within the low-level logic threshold range defined by the target electrical characteristics. It should be noted that the transition rate between high-level and low-level signals is also an important parameter for signal generation, and can be adjusted according to the target electrical characteristics to simulate signal edge changes at different insertion and removal speeds.

[0057] Optionally, in this embodiment, the high-level indication being in place and the low-level indication not being in place can be, but is not limited to, a system architecture where the PRESENT signal is active high; for an architecture where the signal is active low, the signal logic generated by the test device is reversed, but the principle is the same.

[0058] In the above embodiments, by using simulated signals to replace physical plugging and unplugging, not only is the dependence on high-value physical boards eliminated, reducing hardware costs and damage risks, but the timing of signals can also be precisely controlled through programming (such as simulating rapid jitter and critical levels), covering test scenarios that cannot be achieved by traditional manual plugging and unplugging. This effectively solves the problems of high testing costs, low efficiency, and insufficient coverage in related technologies, and achieves the technical effect of improving testing efficiency and reliability.

[0059] As an optional approach, detecting server information generated by the server motherboard's response to test signals also includes:

[0060] S31, Locate multiple server logs generated on the server motherboard. These multiple server logs are generated by the target controller on the server motherboard, which is used to perform board signal detection functions.

[0061] S32 filters the target server log corresponding to the test signal from multiple server logs. The target server log records the board identifier of the server board and the server information includes: target server log.

[0062] Optionally, in this embodiment, a log query command can be sent via the information interface (such as a network port or serial port) of the test device to search for multiple server logs generated on the server motherboard. This can be done by sending an Intelligent Platform Management Interface (IPMI) command (ipmitool sel list) or requesting the Redfish API interface (GET / redfish / v1 / Systems / Logs). The multiple server logs may include, but are not limited to, system event logs recorded by the BMC, sensor readings, CPLD register status values, etc. It should be noted that the search operation can be either real-time monitoring or delayed reading, such as monitoring the serial port print stream or waiting a few seconds after sending a test signal before batch retrieving log files.

[0063] Optionally, in this embodiment, the target controller can be, but is not limited to, a BMC or a CPLD. The process of the target controller generating logs can, but is not limited to, triggering the firmware code to record a log entry containing a timestamp and event type when a level transition (interrupt event) is detected on the board interface's presence signal pin. It should be noted that the target controller is not limited to a single chip; it can also be a collection of multiple chips working collaboratively (e.g., a CPLD detecting level changes and notifying the BMC to record logs). In this case, the entity generating the logs can be considered this collaborative system.

[0064] Optionally, in this embodiment, the target server log corresponding to the test signal may, but is not limited to, refer to a log that records an event (such as "detected in place") that matches the intent of the test signal (such as simulated insertion).

[0065] Optionally, in this embodiment, the target server logs can be filtered from multiple server logs by time window matching, for example, only logs generated after the time point of sending the test signal and before the preset timeout period can be filtered; or, for example, log entries containing keywords such as "Slot", "Presence", "Asserted", or "Deasserted" can be filtered. It should be noted that the filtering algorithm needs to have a certain degree of fault tolerance, such as being able to handle the situation where the server system time and the test device time are not synchronized (by calculating the time difference offset for alignment).

[0066] Optionally, in this embodiment, the board identifier recorded in the target server log can be, but is not limited to, the physical number (e.g., "PCIe Slot 1"), logical number, or board type code of the expansion slot. The board identifier is used to confirm that the object described in the log is indeed the interface connected to the test device, and not some other interfering interface. It should be noted that if the filtering result is empty, or if the status displayed in the filtered log does not match the test signal (e.g., a simulated insertion signal was sent, but the log shows "Removed"), this will be used as the basis for subsequently determining that the test failed.

[0067] In the above embodiments, a test signal conforming to the target electrical characteristics is generated and sent to the board interface in response to a test request. Furthermore, multiple server logs generated by the target controller performing the board signal detection function are searched, and the target server log that records the board identifier and corresponds to the test signal is selected as server information. This allows the test equipment to automatically and accurately correlate and match the simulated signal excitation at the physical layer with the system log feedback at the logic layer, thereby confirming that the server motherboard not only senses signal changes at the electrical layer but also correctly identifies the specific board at the logic layer and records the corresponding state changes. This achieves end-to-end verification of the server motherboard's signal identification logic without manual intervention, ensuring the objectivity and consistency of test results, and significantly improving the automation level, accuracy, and efficiency of board signal testing.

[0068] As an optional approach, the signal detection function of the server motherboard is tested based on test signals and server information, including:

[0069] S41, Identify the in-situ status identifier sequence of the server board from the server information, wherein the in-situ status identifier sequence includes the in-situ status identifiers of the server board recorded in the server information arranged in chronological order.

[0070] S42 compares the in-situ status identifier sequence with the in-situ status indicated by each level signal in the target pulse sequence to obtain the comparison result. The test signal includes the target pulse sequence. The high-level signal in the target pulse sequence conforms to the target electrical characteristics. The high-level signal in the target pulse sequence is used to indicate that the server board is in-situ on the board interface, and the low-level signal in the target pulse sequence is used to indicate that the server board is not in-situ on the board interface.

[0071] S43, determine the functional reliability of the board signal detection function based on the comparison results, wherein the functional reliability is used to indicate whether the board signal detection function can operate normally on the server board.

[0072] Optionally, in this embodiment, identifying the presence status sequence of the server board from the server information can be achieved, but is not limited to, extracting key status fields from the log file using a text parsing algorithm (such as regular expression matching). The presence status identifier can include, but is not limited to, text descriptions (such as "Present", "Absent", "Inserted", "Removed"), numeric codes (such as 0x01", "0x00"), or boolean values ​​("True", "False"). It should be noted that the identification process may require deduplication. For example, if multiple identical status identifiers are recorded consecutively within a short period (such as three consecutive "Present" entries), they may need to be merged into a single status event according to the testing strategy, or retained for analysis of the debouncing logic.

[0073] Optionally, in this embodiment, the presence status identifier sequence may be, but is not limited to, a list of states arranged in ascending order of timestamps (e.g., [T1: Present, T2: Absent, T3: Present]), which reflects the entire process of board status changes perceived by the server motherboard during testing. It should be noted that the specific form of the presence status identifier depends on the server firmware vendor's definition, and the identification algorithm must be configurable to adapt to different vendors' log formats.

[0074] Optionally, in this embodiment, the in-situ state identifier sequence is compared with the in-situ states indicated by each level signal in the target pulse sequence. This includes: converting the target pulse sequence (voltage waveform) into a desired logic state sequence (e.g., high level -> in-situ, low level -> not in-situ), and then comparing this desired sequence with the actually identified in-situ state identifier sequence item by item. It should be noted that the comparison process typically allows for a certain time error. For example, if the test signal flips at time T0 and the log is recorded at time T0+Δt, as long as Δt is within the allowable response delay range (e.g., within 500ms), it is still considered a successful match.

[0075] Optionally, in this embodiment, the comparison result may include, but is not limited to, a state description of "complete match," "partial match," or "complete mismatch," or may contain specific difference information (e.g., the second pull-out operation was not detected). It is important to note that the comparison not only focuses on the correctness of the state but also on whether the order of state transitions strictly matches the transmitted pulse sequence.

[0076] Optionally, in this embodiment, the high-level signal in the target pulse sequence indicates presence and the low-level signal indicates absence based on the positive logic assumption; if the server motherboard uses low-level active logic, then high level corresponds to "absence" and low level corresponds to "present", and the test logic will automatically adapt to this mapping relationship.

[0077] Optionally, in this embodiment, determining the functional reliability of the board's signal detection function based on the comparison results can be achieved, but is not limited to, through logical judgment: if the comparison result is "perfect match," the functional reliability is determined to be "normal / reliable"; if there are missed reports (pulses were sent but no logs), false reports (no pulses but logs), or state reversals, the functional reliability is determined to be "abnormal / unreliable." It should be noted that the criteria for determining functional reliability can be adjusted according to testing requirements. In strict mode, any timing deviation may lead to a determination of unreliability; in lenient mode, a small amount of jitter logs may be allowed.

[0078] Optionally, in this embodiment, functional reliability can also be, but is not limited to, a quantitative indicator, such as "detection success rate" (number of successful identifications / total number of pulses) or "average response delay time". It should be noted that if the comparison result consistently shows "not in place", the functional reliability is determined to be abnormal, and may trigger subsequent fault diagnosis procedures (such as checking whether the link is open).

[0079] In the above embodiments, a test signal containing a target pulse sequence is generated in response to a test request to simulate the insertion and removal operation of the board. The in-situ status identifier sequence arranged in time sequence is further identified from the server information, and the sequence is compared one by one with the in-situ status indicated by each level signal in the target pulse sequence. The functional reliability is determined based on the comparison results. This allows for the accurate capture and verification of the dynamic response capability and logical correctness of the server motherboard when faced with continuous, rapid, or time-specific insertion and removal simulation signals. This avoids the problem in related technologies that usually only focus on the final static in-situ status and fail to capture the intermediate process, resulting in the difficulty in detecting hidden faults such as signal loss, false status alarms, excessive response delay, or abnormal dejitter logic in rapid insertion and removal or signal jitter scenarios. This achieves the technical effect of significantly improving test coverage.

[0080] As an optional approach, after determining the functional reliability of the board's signal detection function based on the comparison results, the method further includes:

[0081] S51, when the functional reliability indicates that the board signal detection function cannot operate normally on the server board, a first test point signal and a second test point signal are acquired. The first test point signal is a test signal acquired at the output terminal of the test signal on the board interface during the process of sending a test signal to the board interface. The second test point signal is a test signal acquired at the input terminal of the test signal on the target controller of the server motherboard during the process of sending a test signal to the board interface. The target controller is used to execute the board signal detection function.

[0082] S52, detect the cause of the abnormality based on the signals from the first test point and the second test point.

[0083] Optionally, in this embodiment, acquiring the first test point signal and the second test point signal can be achieved, but is not limited to, using a multi-channel oscilloscope, a logic analyzer, or a data acquisition unit built into the test equipment. The first test point signal can be, but is not limited to, the voltage waveform at the output terminal of the test signal on the board interface; the second test point signal can be, but is not limited to, the voltage waveform at the GPIO pin of the target controller on the server motherboard. The output terminal can be, but is not limited to, the physical pin on the board interface used to receive external presence signals; the input terminal can be, but is not limited to, the physical pin on the target controller chip package used to sense the signal. It should be noted that the acquisition process needs to ensure the consistency of the ground potential (GND), which is usually referenced to the digital ground of the server motherboard.

[0084] Optionally, in this embodiment, the acquisition operation may, but is not limited to, real-time sampling while sending test signals, or sampling triggered by a reproduction test after detecting a functional reliability anomaly.

[0085] In the above embodiments, when an anomaly is detected in the board signal detection function, the first test point signal located at the test signal output end of the board interface and the second test point signal located at the test signal input end of the target controller on the server motherboard are further collected. Based on the signal characteristics of these two key nodes, a differential comparison is performed to detect the cause of the anomaly. This allows for a clear distinction between whether the fault originates from poor quality of the test signal itself, physical link transmission loss or device damage between the board interface and the controller, or a logic processing error within the target controller. This improves fault diagnosis efficiency and avoids the problem in related technologies where, when a test fails, it is impossible to distinguish whether the fault is due to a test equipment failure, a motherboard hardware circuit failure, or a firmware logic failure. This leads to maintenance personnel having to rely on oscilloscopes for tedious manual point-by-point troubleshooting, or even blindly replacing parts, resulting in inefficient troubleshooting and wasted resources.

[0086] As an optional approach, the cause of the anomaly is detected based on the signals from the first and second test points, including:

[0087] S61, detect the first signal attribute of the first test point signal and the second signal attribute of the second test point signal;

[0088] S62, compare the first signal attribute with the target signal attribute of the test signal, and compare the second signal attribute with the target signal attribute;

[0089] S63, if the attributes of the first signal are found to be inconsistent with the attributes of the target signal, the cause of the anomaly is determined to be a test anomaly;

[0090] S64, if the first signal attribute is consistent with the target signal attribute but the second signal attribute is inconsistent with the target signal attribute, the cause of the anomaly is determined to be an anomaly in the transmission link between the board interface and the target controller, and the target controller is used to perform the board signal detection function;

[0091] S65, if the first signal attribute matches the target signal attribute and the second signal attribute matches the target signal attribute, the cause of the abnormality is determined to be an abnormality in the board signal detection function.

[0092] Optionally, in this embodiment, the first signal attribute and the second signal attribute may include, but are not limited to, voltage amplitude (such as peak value, average value), timing parameters (such as rise time, pulse width), and signal quality indicators (such as overshoot, noise margin, signal-to-noise ratio). It should be noted that the selection of signal attributes should be strongly correlated with the electrical specifications of the target board type. For example, for high-speed signals, focus should be placed on eye diagram opening, while for low-speed in-situ signals, focus should be placed on logic levels and debouncing time.

[0093] Optionally, in this embodiment, the detection attributes can be, but are not limited to, extracting key feature values ​​by performing mathematical operations (such as fast Fourier transform, threshold comparison) on the acquired digital waveform data.

[0094] Optionally, in this embodiment, the target signal attributes can be, but are not limited to, standard electrical parameters preset in the test configuration file, such as "high level must be greater than 2.0V", "low level must be less than 0.8V", and "rise edge must be less than 50ns". It should be noted that the comparison can be a static value comparison at a single moment, or a dynamic waveform envelope comparison over a period of time.

[0095] Optionally, in this embodiment, if the first signal attribute is found to be inconsistent with the target signal attribute, determining the cause of the anomaly as a test anomaly can be, but is not limited to, a faulty signal generator in the test equipment itself, insufficient power supply to the test equipment, or poor physical connector contact between the test equipment and the board interface (such as poor soldering or oxidation of gold fingers). It should be noted that determining it as a test anomaly means the fault point is located outside the server motherboard or at the interface; in this case, the test fixture should be inspected rather than the motherboard repaired.

[0096] Optionally, in this embodiment, if the first signal attribute matches the target signal attribute but the second signal attribute does not, determining the cause of the anomaly as an abnormal transmission link between the board interface and the target controller can be, but is not limited to, an open / short circuit in the printed circuit board (PCB) traces, damage to isolation components (such as MOSFETs) on the link, incorrect pull-up / pull-down resistor values, or excessive parasitic capacitance causing a slowed signal edge. It should be noted that an abnormal transmission link specifically refers to signal attenuation or distortion during physical transmission, causing the signal reaching the controller to no longer conform to the logical decision criteria.

[0097] Optionally, in this embodiment, if the first signal attribute matches the target signal attribute and the second signal attribute matches the target signal attribute, determining the cause of the anomaly as a board signal detection function malfunction can be, but is not limited to, a logical design error within the target controller (such as a state machine freeze), a firmware code error (such as an interrupt handler not responding), or unreasonable dejitter parameter settings leading to signal loss. It should be noted that this conclusion assumes the physical layer signal is perfect (i.e., the hardware circuit is fault-free); therefore, the fault must lie in the controller's logic or software layer.

[0098] In the above embodiments, during the process of detecting the cause of the anomaly, the first signal attribute of the first test point signal located at the test signal output terminal and the second signal attribute of the second test point signal located at the target controller input terminal are detected respectively, and these two attributes are logically compared with the preset target signal attributes respectively: if the first signal attribute does not match, it is determined to be a test anomaly; if the first signal attribute matches but the second signal attribute does not match, it is determined to be a transmission link anomaly; if both match, it is determined to be an abnormality of the board signal detection function. This realizes the automated identification and precise isolation of the root cause of the fault, and the nature of the fault can be determined without manual intervention. This avoids the problem in related technologies where, when the board detection fails, maintenance personnel cannot distinguish whether it is an external test tool failure, a damage to the motherboard physical circuit, or an internal firmware logic error. They often have to rely on manual use of an oscilloscope to check segment by segment or blindly replace parts for trial and error, resulting in low troubleshooting efficiency.

[0099] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0100] Based on this understanding, the technical solution of this application, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0101] This embodiment also provides a test device for board signals. Figure 3 This is a structural frame of a board signal testing device according to an embodiment of this application. Figure 1 ,like Figure 3 As shown, the test device 20 includes: a tester 22, a signal interface 24 and an information interface 26. The tester 22 is connected to both the signal interface 24 and the information interface 26. The signal interface 24 is used to connect to the board interface 42 of the server motherboard 40 under test, and the information interface 26 is used to connect to the server motherboard 40.

[0102] Tester 22 is used to receive test requests, wherein the test requests are used to request testing of the board signal detection function of the server motherboard 40, and the board signal detection function is used to identify the server boards connected to the server motherboard 40; in response to the test requests, it generates test signals that conform to the target electrical characteristics, wherein if the server board belongs to the target board type, the server board has the target electrical characteristics, and the test signals are used to simulate the insertion and removal operations of the server board on the board interface 42; it sends test signals to the board interface 42 through the signal interface 24, and detects the server information generated by the server motherboard 40 in response to the test signals through the information interface 26; and tests the board signal detection function of the server motherboard 40 based on the test signals and the server information.

[0103] Tester 22 is used to execute the steps in the above-described server testing method embodiments. Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0104] Optionally, in this embodiment, the test device 20 may be, but is not limited to, a portable signal simulation module, a handheld tester, or a test board integrated in an automated test cabinet. The test device 20 may, but is not limited to, interconnect its internal components via PCB traces. It should be noted that the signal interface 24 is used to inject simulated physical layer electrical signals (such as presence signals), while the information interface 26 is mainly used for interacting with logic layer data (such as reading logs). The two may be physically separate interfaces or integrated into the same physical connector (if the connector also defines management bus pins).

[0105] Optionally, in this embodiment, the signal interface 24 may be, but is not limited to, a gold finger connector, a pin header connector, or a high-density interconnect connector. The physical form of the signal interface 24 matches the board interface 42, realizing a pin-to-pin connection. It should be noted that the power supply of the test device 20 may be, but is not limited to, directly drawn from the server motherboard 40 through the signal interface 24 (e.g., using the VCC pin of the board interface 42), or it may be powered by an external power supply.

[0106] Optionally, in this embodiment, the information interface 26 may be, but is not limited to, an Ethernet interface, a serial communication interface, or a universal serial bus interface. The information interface 26 is used to establish a management communication link between the test device 20 and the server motherboard 40.

[0107] Optionally, in this embodiment, the board interface 42 may be, but is not limited to, a PCIe expansion slot, an Open Compute Project network card slot, or a high-speed interconnect interface for a proprietary protocol.

[0108] Optionally, in this embodiment, the tester 22 may be, but is not limited to, an MCU, a CPLD, a field-programmable gate array, or an embedded system-on-a-chip. The tester 22 is electrically connected to the signal interface 24 and the information interface 26 via an internal bus or GPIO lines to control the transmission and reception of signals.

[0109] Optionally, in this embodiment, the tester 22 may receive test requests by detecting changes in the state of physical buttons on the test device 20, or by receiving remote commands sent by the host computer through the information interface 26. It should be noted that the process of generating test signals is entirely completed within the test device 20 and does not require mechanical insertion or removal of actual physical boards.

[0110] In one exemplary embodiment, Figure 4 This is a structural frame of a board signal testing device according to an embodiment of this application. Figure 2 ,like Figure 4 As shown, information interface 26 is connected to target controller 44 on server motherboard 40. Tester 22 is also used for:

[0111] Locate the multiple server logs generated on the target controller 44, which is used to perform board signal detection functions;

[0112] The target server log corresponding to the test signal is selected from multiple server logs. The target server log records the board identifier of the server board and server information including: target server log.

[0113] Optionally, in this embodiment, the connection between the information interface 26 and the target controller 44 on the server motherboard 40 can be, but is not limited to, a physical link, such as an I2C bus, system management bus, or universal asynchronous transceiver serial cable. It should be noted that the connection method depends on the communication protocol supported by the target controller 44. In some implementations, the information interface 26 and the signal interface 24 may be physically integrated in the same connector, for example, through simultaneous signal injection and management communication via the sideband pins of the PCIe slot.

[0114] Optionally, in this embodiment, the target controller 44 is responsible for monitoring changes in the physical state of the server motherboard and managing the logging system. It should be noted that the target controller 44 may not directly expose external interfaces; in this case, the information interface 26 may establish a logical connection with the target controller 44 through an intermediate gateway or hub.

[0115] Optionally, in this embodiment, the tester 22 can search for multiple server logs generated on the target controller 44 by sending query commands, such as sending IPMI commands, Redfish HTTP requests, or private serial port debugging commands through the information interface 26. It should be noted that the search operation can be passive, such as receiving information actively reported by the target controller 44, or it can be an active polling query.

[0116] In one exemplary embodiment, Figure 5 This is a structural frame of a board signal testing device according to an embodiment of this application. Figure 3 ,like Figure 5 As shown, the test device 20 also includes: a first test point interface 27 and a second test point interface 28, wherein the first test point interface 27 is used to connect to the output terminal of the test signal on the board interface 42, and the second test point interface 28 is used to connect to the input terminal of the test signal on the target controller of the server motherboard 40, and the target controller is used to perform the board signal detection function.

[0117] The first test point interface 27 is used to acquire the test signal at the output end during the process of the tester 22 sending the test signal to the board interface 42, and obtain the first test point signal.

[0118] The second test point interface 28 is used to acquire the test signal at the input end during the process of the tester 22 sending the test signal to the board interface 42, and obtain the second test point signal.

[0119] Tester 22 is used to acquire the first test point signal and the second test point signal when the test result of the board signal detection function indicates that the board signal detection function cannot operate normally on the server board; and to detect the cause of the abnormality based on the first test point signal and the second test point signal.

[0120] Optionally, in this embodiment, the first test point interface 27 and the second test point interface 28 can be, but are not limited to, physical probe interfaces, pin header interfaces, or feedback channels integrated in the main signal connector. The first test point interface 27 is used to connect the location where the test signal leaves the test equipment and enters the motherboard card interface (i.e., the output terminal); the second test point interface 28 is used to connect the location where the signal reaches the target controller pin (i.e., the input terminal). It should be noted that the second test point interface 28 typically requires a high-impedance input design to avoid pulling down or interfering with the weak signal originally transmitted to the target controller after being connected to the test equipment.

[0121] Optionally, in this embodiment, the output terminal may be, but is not limited to, a pin defined for an in-situ signal on the board interface 42 (such as pin B48 of a PCIe slot); the input terminal may be, but is not limited to, a GPIO input pin of the target controller (such as a CPLD) on the server motherboard 40 or a test pad reserved on the PCB board. It should be noted that "output terminal" is relative to the direction of the test signal flow (from the test device to the motherboard), while "input terminal" is relative to the target controller (entering the controller chip).

[0122] Optionally, in this embodiment, if the server motherboard design supports readback, the first test point interface 27 and the second test point interface 28 can also be routed back to the test device 20 through internal wiring on the motherboard, thus eliminating the need for external jumper wires.

[0123] Optionally, in this embodiment, in order to better understand the above-mentioned board signal testing method and testing equipment, the above-mentioned board signal testing method and testing equipment will be described below in conjunction with optional embodiments, but this is not intended to limit the technical solution of the embodiments of this application.

[0124] This embodiment provides a method and equipment for testing board signals, mainly including the following steps:

[0125] Step S301: Insert connector 1 (signal interface) of the board signal testing equipment into connector 2 (board interface) of the motherboard of the server under test to achieve pin-to-pin matching connection, establish connection and power supply startup. The testing equipment obtains power from the motherboard of the server under test through connector 2. After obtaining power, the testing equipment automatically starts its built-in MCU control unit (tester). This process does not require connecting an additional main unit or high-value expansion card (server board), achieving decoupling of physical components.

[0126] Step S302: After the MCU control unit starts, it generates a target presence detection signal (test signal) that matches the electrical characteristics of the physical board's presence signal according to the preset configuration. This test signal has specific target electrical characteristics, including level thresholds and timing parameters (such as rise / fall time, pulse width, and setup / hold time). The MCU control unit drives the test signal to be sent through connector 1 to a specific pin (such as the PRESENT pin) of connector 2 to simulate the insertion and removal operation of the server board on the board interface. For example, the MCU generates a periodic pulse sequence (target pulse sequence), where a high-level signal indicates presence and a low-level signal indicates absence, thereby simulating the repeated insertion and removal of the board.

[0127] Step S303: The test signal enters the motherboard of the server under test from connector 2, and is transmitted to the CPLD or BMC chip (target controller) on the motherboard via the transmission link on the motherboard (such as PCB traces, isolated MOSFETs). The CPLD / BMC continuously monitors the level changes of the input pins. When a transition of the test signal is detected, a corresponding interrupt is generated and a test log (server information) is recorded. This test log contains the recognition status of the target presence detection signal by the motherboard of the server under test, such as recording the status indicators "Slot X Present" or "Slot X Absent" and the corresponding timestamps.

[0128] Step S304: Functional Verification and Reliability Assessment. The test equipment obtains the test log from the target controller through an information interface (such as an out-of-band interface for communication with the CPLD / BMC). The test equipment extracts the "present / absent" status identifiers (present status identifier sequence) from the test log and compares them with the timing of the test signals generated by the MCU. If the status changes recorded in the log correspond perfectly with the sent test signals in logic and timing (e.g., when the MCU sends a high level, the log records "present"), then the present detection function (board signal detection function) of the motherboard under test is determined to be normal and its functional reliability is high; otherwise, it is determined to be functionally abnormal.

[0129] Step S305: If the function is determined to be unreliable (i.e., the test fails) in step S304, the test equipment will use its built-in data acquisition circuit or auxiliary probe to collect signals from two key measurement points of the signal transmission link:

[0130] Front-end test point TP1 signal (first test point signal): The acquisition point is located at the signal output end of connector 2, that is, the position where the test signal just leaves the test equipment and enters the motherboard.

[0131] Back-end test point TP2 signal (second test point signal): The acquisition point is located at the GPIO input terminal of the CPLD / BMC, that is, the signal reaches the controller pin through the motherboard link.

[0132] The data collected includes signal level parameters, timing characteristics, signal integrity data, impedance matching data, and noise margin data (signal attributes).

[0133] Step S306: The testing equipment performs logical judgments based on the collected front-end and back-end measurement point signals to detect the cause of the anomaly.

[0134] Test equipment failure (test anomaly): If the front-end test point signal is abnormal (the first signal attribute is inconsistent with the target signal attribute), such as high signal noise, non-steep edges, or no waveform output, it indicates that the test equipment itself is faulty and is unrelated to the motherboard.

[0135] Motherboard link failure (transmission link anomaly): If the front-end test point signal is normal (first signal attribute is consistent), but the back-end test point signal is abnormal (second signal attribute is inconsistent), it indicates that the signal has been distorted or interrupted during transmission. In this case, the cause of the anomaly can be determined to be a transmission link failure between the board interface and the target controller. This may include a damaged isolation MOSFET, incorrect pull-up / pull-down resistor configuration, or excessive parasitic parameters of the PCB traces.

[0136] Controller logic fault (abnormal board signal detection function): If both the front-end and back-end measurement point signals are normal (both have attributes consistent with the target signal attributes), it indicates that the signal conforming to the electrical standard has been perfectly transmitted to the controller's input pins, but the log is still incorrect. In this case, the cause of the abnormality can be determined to be an error in the detection logic inside the target controller (CPLD / BMC), improper debouncing parameter settings, or firmware errors.

[0137] Through the above steps S301 to S306, this application not only achieves low-cost and high-efficiency automated testing, but also improves the reliability of the test results of the board signals through the segmented detection mechanism of TP1 and TP2.

[0138] This embodiment also provides a board signal testing device, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0139] Figure 6 This is a structural block diagram of a board signal testing device according to an embodiment of this application; as shown... Figure 6 As shown, it includes:

[0140] The receiving module 602 is used to receive a test request, wherein the test request is used to request a test of the board signal detection function of the server motherboard, and the board signal detection function is used to identify the server boards connected to the server motherboard.

[0141] The generation module 604 is used to respond to test requests and generate test signals that conform to the target electrical characteristics. If the server board belongs to the target board type, then the server board has the target electrical characteristics. The test signals are used to simulate the insertion and removal operations of the server board on the board interface of the server motherboard.

[0142] The sending module 606 is used to send test signals to the board interface and detect the server information generated by the server motherboard in response to the test signals;

[0143] Test module 608 is used to test the board signal detection function of the server motherboard based on test signals and server information.

[0144] In one exemplary embodiment, the generation module includes:

[0145] The extraction unit is used to extract the target electrical characteristics corresponding to the target board type from the board types and electrical characteristics that have a corresponding relationship;

[0146] The generation unit is used to generate a target pulse sequence as a test signal. The high-level signal in the target pulse sequence conforms to the target electrical characteristics. The high-level signal in the target pulse sequence is used to indicate that the server board is in place on the board interface, and the low-level signal in the target pulse sequence is used to indicate that the server board is not in place on the board interface.

[0147] In one exemplary embodiment, the sending module includes:

[0148] The lookup unit is used to look up multiple server logs generated on the server motherboard. These multiple server logs are generated by the target controller on the server motherboard, which is used to perform board signal detection functions.

[0149] The filtering unit is used to filter out the target server log corresponding to the test signal from multiple server logs. The target server log records the board identifier of the server board and the server information includes: target server log.

[0150] In one exemplary embodiment, the test module includes:

[0151] The identification unit is used to identify the in-situ status identifier sequence of the server board from the server information, wherein the in-situ status identifier sequence includes the in-situ status identifiers of the server board recorded in the server information arranged in chronological order.

[0152] The first comparison unit is used to compare the in-situ status identification sequence with the in-situ status indicated by each level signal in the target pulse sequence to obtain the comparison result. The test signal includes the target pulse sequence. The high-level signal in the target pulse sequence conforms to the target electrical characteristics. The high-level signal in the target pulse sequence is used to indicate that the server board is in-situ on the board interface, and the low-level signal in the target pulse sequence is used to indicate that the server board is not in-situ on the board interface.

[0153] The first determining unit is used to determine the functional reliability of the board signal detection function based on the comparison results, wherein the functional reliability is used to indicate whether the board signal detection function can operate normally on the server board.

[0154] In one exemplary embodiment, the apparatus further includes:

[0155] The acquisition module is used to acquire a first test point signal and a second test point signal after determining the functional reliability of the board signal detection function based on the comparison results, and when the functional reliability indicates that the board signal detection function cannot operate normally on the server board. The first test point signal is the test signal collected at the output terminal of the test signal on the board interface during the process of sending the test signal to the board interface, and the second test point signal is the test signal collected at the input terminal of the test signal on the target controller of the server motherboard during the process of sending the test signal to the board interface. The target controller is used to execute the board signal detection function.

[0156] The detection module is used to detect the cause of the abnormality based on the signals from the first test point and the second test point.

[0157] In one exemplary embodiment, the detection module includes:

[0158] The detection unit is used to detect a first signal attribute of the first test point signal and a second signal attribute of the second test point signal.

[0159] The second comparison unit is used to compare the first signal attribute with the target signal attribute of the test signal, and to compare the second signal attribute with the target signal attribute.

[0160] The second determining unit is used to determine the cause of the anomaly as a test anomaly when the first signal attribute is found to be inconsistent with the target signal attribute.

[0161] The third determining unit is used to determine that the cause of the abnormality is an abnormality in the transmission link between the board interface and the target controller when the first signal attribute is consistent with the target signal attribute but the second signal attribute is inconsistent with the target signal attribute. The target controller is used to perform the board signal detection function.

[0162] The fourth determining unit is used to determine that the cause of the abnormality is a faulty board signal detection function when the first signal attribute is consistent with the target signal attribute and the second signal attribute is consistent with the target signal attribute.

[0163] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0164] For a description of the features in the embodiment corresponding to the board signal testing device, please refer to the relevant description in the embodiment corresponding to the board signal testing method, which will not be repeated here.

[0165] Embodiments of this application also provide an electronic device. Figure 7 This is a schematic diagram of an electronic device according to an embodiment of this application, such as... Figure 7 As shown, the electronic device includes a memory and a processor, the memory storing a computer program, and the processor being configured to run the computer program to perform the steps in any of the above-described test method embodiments for board signals.

[0166] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0167] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0168] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described test method embodiments for board signals when running.

[0169] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0170] Embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements the steps of the methods described in various embodiments of this application; the computer program product further includes a non-volatile computer-readable storage medium storing the computer program, which, when executed by a processor, implements the steps of the board signal testing method described in various embodiments of this application.

[0171] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0172] The above provides a detailed description of a board signal testing method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for testing board signals, characterized in that, include: Receive a test request, wherein the test request is used to request a test of the board signal detection function of the server motherboard, and the board signal detection function is used to identify the server boards connected to the server motherboard; In response to the test request, a test signal conforming to the target electrical characteristics is generated, wherein, if the server board belongs to the target board type, the server board has the target electrical characteristics, and the test signal is used to simulate the insertion and removal operation of the server board on the board interface of the server motherboard; Send the test signal to the board interface and detect the server information generated by the server motherboard in response to the test signal; The board signal detection function of the server motherboard is tested based on the test signal and the server information.

2. The method according to claim 1, characterized in that, The generation of test signals that conform to the target electrical characteristics includes: Extract the target electrical characteristics corresponding to the target board type from the corresponding board types and electrical characteristics; A target pulse sequence is generated as the test signal, wherein the high-level signal in the target pulse sequence conforms to the target electrical characteristics, the high-level signal in the target pulse sequence is used to indicate that the server board is in place on the board interface, and the low-level signal in the target pulse sequence is used to indicate that the server board is not in place on the board interface.

3. The method according to claim 1, characterized in that, The detection of server information generated by the server motherboard in response to the test signal includes: Locate multiple server logs generated on the server motherboard, wherein the multiple server logs are generated by a target controller on the server motherboard, and the target controller is used to perform the board signal detection function; The target server log corresponding to the test signal is selected from the plurality of server logs. The target server log records the board identifier of the server board. The server information includes the target server log.

4. The method according to claim 1, characterized in that, The step of testing the board signal detection function of the server motherboard based on the test signal and the server information includes: Identify the in-situ status identifier sequence of the server board from the server information, wherein the in-situ status identifier sequence includes the in-situ status identifiers of the server board recorded in the server information in chronological order; The in-situ status identifier sequence is compared with the in-situ status indicated by each level signal in the target pulse sequence to obtain a comparison result. The test signal includes the target pulse sequence. The high-level signal in the target pulse sequence conforms to the target electrical characteristics. The high-level signal in the target pulse sequence is used to indicate that the server board is in-situ on the board interface, and the low-level signal in the target pulse sequence is used to indicate that the server board is not in-situ on the board interface. The functional reliability of the board signal detection function is determined based on the comparison results, wherein the functional reliability is used to indicate whether the board signal detection function can operate normally on the server board.

5. The method according to claim 4, characterized in that, After determining the functional reliability of the board signal detection function based on the comparison results, the method further includes: When the functional reliability indicates that the board signal detection function cannot operate normally on the server board, a first test point signal and a second test point signal are acquired. The first test point signal is the test signal acquired at the output terminal of the test signal on the board interface during the process of sending the test signal to the board interface. The second test point signal is the test signal acquired at the input terminal of the test signal on the target controller of the server motherboard during the process of sending the test signal to the board interface. The target controller is used to execute the board signal detection function. The cause of the anomaly is detected based on the signals from the first test point and the second test point.

6. The method according to claim 5, characterized in that, The step of detecting the cause of the anomaly based on the first test point signal and the second test point signal includes: Detect the first signal attribute of the signal at the first test point and the second signal attribute of the signal at the second test point; The first signal attribute is compared with the target signal attribute of the test signal, and the second signal attribute is compared with the target signal attribute; If the first signal attribute is found to be inconsistent with the target signal attribute, the cause of the anomaly is determined to be a test anomaly. If the first signal attribute matches the target signal attribute but the second signal attribute does not match the target signal attribute, the cause of the anomaly is determined to be an anomaly in the transmission link between the board interface and the target controller, and the target controller is used to perform the board signal detection function. If the first signal attribute matches the target signal attribute and the second signal attribute matches the target signal attribute, the cause of the anomaly is determined to be an anomaly in the board's signal detection function.

7. A testing device for board signals, characterized in that, The testing equipment includes: a tester, a signal interface, and an information interface, wherein the tester is connected to both the signal interface and the information interface, the signal interface is used to connect to the board interface of the server motherboard under test, and the information interface is used to connect to the server motherboard. The tester is configured to receive a test request, wherein the test request requests testing of the board signal detection function of the server motherboard, the board signal detection function being used to identify server boards connected to the server motherboard; respond to the test request by generating a test signal conforming to the target electrical characteristics, wherein if the server board belongs to the target board type, then the server board has the target electrical characteristics, and the test signal is used to simulate the insertion and removal operation of the server board on the board interface; send the test signal to the board interface through the signal interface, and detect the server information generated by the server motherboard in response to the test signal through the information interface; and test the board signal detection function of the server motherboard based on the test signal and the server information.

8. The test equipment for board signals according to claim 7, characterized in that, The information interface is connected to the target controller on the server motherboard, and the tester is also used for: Locate multiple server logs generated on the target controller, wherein the target controller is used to perform the board signal detection function; The target server log corresponding to the test signal is selected from the plurality of server logs. The target server log records the board identifier of the server board. The server information includes the target server log.

9. The test equipment for board signals according to claim 7, characterized in that, The testing equipment further includes: a first test point interface and a second test point interface, wherein the first test point interface is used to connect to the output terminal of the test signal on the board interface, and the second test point interface is used to connect to the input terminal of the test signal on the target controller of the server motherboard, and the target controller is used to perform the board signal detection function; The first test point interface is used to acquire the test signal at the output terminal during the process of the tester sending the test signal to the board interface, and obtain the first test point signal; The second test point interface is used to acquire the test signal at the input terminal during the process of the tester sending the test signal to the board interface, and obtain the second test point signal; The tester is used to acquire the first test point signal and the second test point signal when the test result of the board signal detection function indicates that the board signal detection function cannot operate normally on the server board; and to detect the cause of the abnormality based on the first test point signal and the second test point signal.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the test method for board signals as described in any one of claims 1 to 6 when executing the computer program.

Images