Data processing method, data processing device, data processing equipment and product

Abstract

The invention provides a data processing method, a data processing device, data processing equipment and a product, and belongs to the technical field of storage management. The method comprises the following steps: determining a running state of a main memory; under the condition that the running state represents that the running load of the main memory is lower than a preset load threshold value, target dirty data in the buffer are written back to the main memory, and the target dirty data are at least part of dirty data in the buffer; wherein the priority of writing the target dirty data back to the main memory is lower than the priority of normal memory access operation on the main memory. According to the embodiment of the invention, the access pressure on the main memory when the unified write-back is indicated can be effectively relieved, and the normal memory access operation is not influenced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of storage management, and in particular, to a data processing method, a data processing apparatus, a data processing device, an electronic device, a computer readable storage medium, and a computer program product. BACKGROUND

[0002] A processing chip usually adopts a multi-level cache architecture. The last level cache (such as L2 cache) can use a write-back strategy to reduce the number of write accesses to the main memory. When a cache line is marked as dirty and needs to be vacated, the cache controller writes the dirty data line back to the main memory. In the related art, dirty data in the last level cache is usually accumulated until it is replaced or context switched, and then unified write-back is performed. Based on this, if multiple dirty cache lines need to be written back at the same time within a short period of time, a large number of write requests will be concentrated, and these write requests will compete with normal memory access requests for bandwidth on the memory bus, resulting in significant read-write conflict delays and reducing system performance. SUMMARY

[0003] The present disclosure provides a data processing method, a data processing apparatus, a data processing device, an electronic device, a computer readable storage medium, and a computer program product.

[0004] In a first aspect, the present disclosure provides a data processing method, comprising: determining a running state of a main memory; and writing back target dirty data in a cache to the main memory in a case where the running state indicates that a running load of the main memory is lower than a preset load threshold, the target dirty data being at least part of dirty data in the cache; wherein a priority of writing back the target dirty data to the main memory is lower than a priority of a normal memory access operation on the main memory.

[0005] In a second aspect, the present disclosure provides a data processing apparatus, comprising: a determining module configured to determine a running state of a main memory; and a write-back module configured to write back target dirty data in a cache to the main memory in a case where the running state indicates that a running load of the main memory is lower than a preset load threshold, the target dirty data being at least part of dirty data in the cache; wherein a priority of writing back the target dirty data to the main memory is lower than a priority of a normal memory access operation on the main memory.

[0006] In a third aspect, the present disclosure provides a data processing device, comprising: a main memory, a cache, a cache controller, and a state detection module; the state detection module is configured to determine a running state of the main memory, and send a refresh trigger signal to the cache when the running state indicates that a running load of the main memory is lower than a preset load threshold; the cache is configured to write back target dirty data to the main memory through the cache controller when the refresh trigger signal is received, the target dirty data being at least part of dirty data in the cache; and a priority of writing back the target dirty data to the main memory is lower than a priority of a normal memory access operation on the main memory.

[0007] In a fourth aspect, the present disclosure provides an electronic device, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the data processing method described above.

[0008] In a fifth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the data processing method described above.

[0009] In a sixth aspect, the present disclosure provides a computer program product comprising computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the data processing method described above.

[0010] The data processing method provided by the embodiments of the present disclosure can detect the running state of the main memory, and then determine whether the main memory is in a low load state or an idle state according to the running state, and write back at least part of dirty data to the main memory when the main memory is determined to be in a low load state or an idle state, thereby reducing the amount of dirty data to be written back, and thus effectively relieving the access pressure on the main memory when indicating unified write back; in addition, by setting the priority of writing back dirty data when the main memory is in a low load state or an idle state to be lower than the priority of a normal memory access operation on the main memory, the writing of dirty data can be interrupted quickly when a normal memory access request is received, and the memory access request can be responded in time, without affecting the normal memory access operation.

[0011] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and are used to explain the present disclosure and are not intended to limit the present disclosure. The above and other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 A flow chart of a data processing method provided by an embodiment of the present disclosure.

[0014] Figure 2 A schematic diagram of a data processing method provided by an embodiment of the present disclosure.

[0015] Figure 3 A block diagram of a data processing apparatus provided by an embodiment of the present disclosure.

[0016] Figure 4 A block diagram of a data processing device provided by an embodiment of the present disclosure.

[0017] Figure 5 A block diagram of an electronic device provided by an embodiment of the present disclosure.

[0018] Figure 6 A block diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of the present disclosure to help understanding, which should be considered only as exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Also, in order to be clear and concise, the description below omits the description of well-known functions and structures.

[0020] The embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0021] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Coupled" or "connected" or similar terms are not restricted to physical or mechanical connections or associations, but can also include electrical connections, whether direct or indirect.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0024] In the technical solutions of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved in the technical solutions comply with relevant laws and regulations and do not violate public order and good customs. The use of user data in the technical solutions complies with relevant national laws and regulations (for example, the Information Security Technology Personal Information Security Specification). For example, appropriate measures are taken for personal information access control; the display of personal information is limited by regulations; the use purpose of personal information does not exceed the direct or reasonably related range; the use of personal information eliminates the explicit identity pointing and avoids precise positioning to a specific individual.

[0025] In the related art, the main deficiency of the cache management scheme of a processor such as a graphics processing unit (GPU) is that when a large amount of dirty data is accumulated in the L2 cache, once centralized flushing occurs, the dirty data will be written back to the main memory in a burst manner in a short time, causing congestion and read-write conflict of the memory bus. Such burst traffic not only cannot fully utilize the main memory bandwidth, but also occupies the square memory request bandwidth, resulting in a significant decrease in system throughput and affecting system performance.

[0026] In view of this, the embodiments of the present disclosure provide a data processing method, a data processing apparatus, a data processing device, an electronic device, a computer readable storage medium and a computer program product.

[0027] In the embodiments of the present disclosure, at least part of the dirty data in the cache is written back to the memory during the idle or low-load period of the main memory, which relieves the access pressure of the memory when all dirty data is written back, and does not affect the normal memory access operation.

[0028] Figure 1 A flowchart of a data processing method provided by an embodiment of the present disclosure is shown in FIG. 1. Referring to FIG. 1, Figure 1 the data processing method can include the following steps:

[0029] Step S11, determining a running state of the main memory;

[0030] Step S12, in a case where the running state indicates that the running load of the main memory is lower than a preset load threshold, writing back target dirty data in the cache to the main memory, the target dirty data being at least part of the dirty data in the cache;

[0031] wherein the priority of writing back the target dirty data to the main memory is lower than that of a normal memory access operation to the main memory.

[0032] In other words, in the process of writing back the target dirty data according to the embodiment of the present disclosure, if a normal memory access request (corresponding to a normal memory access operation) to the main memory is detected, the writing back operation of the target dirty data can be interrupted in time, and the memory access operation corresponding to the normal memory access request can be performed.

[0033] In some optional embodiments, the data processing method is suitable for dirty data processing by a data processing device (or data processing equipment), which includes one or more processors (or processing cores), a main memory and a cache, the processor being configured to provide core data processing functions, the main memory being a main memory space directly accessible by the processor, and the cache being a high-speed buffer between the processor and the main memory, and the core function of the cache being to improve data access speed.

[0034] Therefore, according to the embodiment of the present disclosure, without increasing software overhead and without interfering with normal tasks, if it is detected that the main memory is low in load or idle, part of the dirty data in the cache can be written back to the main memory in advance, so that the write back pressure is greatly reduced when a large-scale refresh is really needed (such as receiving a unified write back instruction), and the impact of burst read-write traffic on system performance is fundamentally reduced.

[0035] It should be noted that, in addition to writing back the target dirty data to the main memory when the main memory is idle or low in load, a unified dirty data refresh strategy is also provided for the main memory, such as the aforementioned large-scale dirty data write back operation based on a unified write back instruction, and the data processing method of the embodiment of the present disclosure is only a supplementary processing method for relieving the dirty data write back pressure. Moreover, the data processing method of the embodiment of the present disclosure does not affect the execution of the original unified dirty data refresh strategy, and thus does not destroy data consistency, and therefore does not introduce additional write conflicts, and is a transparent operation that is not perceived by the system, and does not affect existing data processing and user experience.

[0036] To sum up, in the embodiments of the present disclosure, the running state of the main memory can be detected, and then when the main memory is in a low load or idle state, part of the dirty data is written back to the main memory, the amount of data to be written back is reduced, and thus the access pressure on the main memory when indicating unified write back can be effectively alleviated; and since the write back operation does not change the original dirty data refresh strategy and does not damage data consistency, no additional write conflict is introduced, and thus it is a transparent operation without system awareness, which does not affect the existing data processing and user experience; in addition, by setting the priority of writing back dirty data in a low load or idle state to be lower than the priority of normal memory access operations of the main memory, the write of dirty data can be quickly interrupted when a normal memory request is received, and the memory request can be responded in time, and the normal memory operation is not affected.

[0037] The data processing method of the embodiments of the present disclosure is described below.

[0038] In some optional embodiments, the main memory is a main memory (memory) that can be directly accessed by the processor or processing core. For example, the main memory includes a double data rate synchronous dynamic random access memory (DDR).

[0039] In some optional embodiments, the cache is a cache between the processor or processing core and the memory, which can include at least one of an L1 cache, an L2 cache, an L3 cache, etc.

[0040] For example, the GPU chip includes a plurality of GPU cores, and a DDR main memory and an L2 cache that provide storage functions for the GPU cores.

[0041] In some optional embodiments, the running state of the main memory can be determined through a plurality of running index data of the main memory and other signal data that can reflect the running state of the main memory, and the running state can represent that the main memory is in a low load state, a high load state, or an idle state.

[0042] In some optional embodiments, the running index data includes a command queue depth corresponding to the main memory, a number of memory requests in a preset period, and the like, and the signal data that can reflect the running state of the main memory includes an arbiter signal; and correspondingly, determining the running state of the main memory includes: determining the running state of the main memory according to at least one of the command queue depth corresponding to the main memory, the number of memory requests in the preset period, and the arbiter signal.

[0043] The command queue depth can represent a length L of a command queue in a controller corresponding to the main memory. If the length L is large, it indicates that there are more access requests to be processed by the main memory, and the main memory can be busy. If the length L is small, it indicates that there are fewer access requests to be processed by the main memory, and the main memory can be in a low-load state or an idle state.

[0044] For example, if it is detected that the command queue depth corresponding to the main memory is lower than a preset queue threshold, and the duration of the idle state of the main memory exceeds a plurality of time periods (for example, 100 clock periods), a refresh action is triggered once, and at least one write-back operation of dirty data (for example, one dirty cache line) is performed by one refresh action.

[0045] The number of access requests in the preset period indicates the number N of access requests to the main memory in the preset period. Alternatively, the preset period can include a plurality of statistical periods, and the number of access requests in the preset period can be the average N' of the number of access requests in the plurality of statistical periods. Accordingly, if the value of N (or N') is large, it indicates that the access requests to the main memory are intensive, and the main memory can be busy. If the value of N (or N') is small, it indicates that the access requests to the main memory are sparse, and the main memory can be in a low-load state or an idle state.

[0046] The arbiter signal is a signal of an arbiter of the main memory. The arbiter is a core module of the controller of the main memory for resolving memory access conflicts in multiple devices. The arbiter signal can be regarded as a precondition for triggering the access of the main memory. If all or most of the arbiter signals are invalid, the main memory is more likely to be idle or in a low-load state. For example, if the arbiter signal indicates that the read request and the write request to the main memory both correspond to a low level, it indicates that the main memory can be in a low-load state or an idle state.

[0047] For example, the above operating index data can be obtained by detecting the bus of the main memory, so as to determine the operating state of the main memory, and write the target dirty data in the cache back to the main memory when the operating load of the main memory is low or idle.

[0048] For example, the controller of the main memory can be detected in real time to obtain the command queue depth, the number of access requests in a preset clock period in a recent period of time, and the arbiter signal, so as to determine whether the current DDR bus is in an idle state, a low-load state or a busy state, and then determine the operating state of the main memory.

[0049] In some optional embodiments, the running load can reflect the amount of tasks carried by the main memory, which can be reflected by the command queue depth, the number of memory access requests in a preset period, and the arbiter signal. The preset load threshold is a critical value, and by comparing the size relationship between the running load and the preset load threshold, the running state of the main memory can be determined. Correspondingly, the preset load threshold includes at least one of a depth threshold corresponding to the command queue depth, a quantity threshold corresponding to the number of memory access requests in a preset period, and a signal threshold corresponding to the arbiter signal. Among them, if the arbiter signal represents that the read request and the write request corresponding to the main memory both correspond to a low level, it represents that the main memory can be in a low load or idle state, and the signal threshold includes a low level duration or a low level duration ratio in a preset period.

[0050] For example, if the command queue depth L is less than or equal to the first depth threshold thrL1, it indicates that the main memory is in an idle state, if the command queue depth L is greater than the first depth threshold thrL1 and less than or equal to the second depth threshold thrL2, it indicates that the main memory is in a low load state, and if the command queue depth L is greater than the second depth threshold thrL2, it indicates that the main memory is in a high load state; thrL1 is less than thrL2.

[0051] For example, if the number of memory access requests N in a preset period is less than or equal to the first quantity threshold thrN1, it indicates that the main memory is in an idle state, if the number of memory access requests N is greater than the first quantity threshold thrN1 and less than or equal to the second quantity threshold thrN2, it indicates that the main memory is in a low load state, and if the number of memory access requests N is greater than the second quantity threshold thrN2, it indicates that the main memory is in a high load state; thrN1 is less than thrN2.

[0052] For example, if the arbiter signal includes an arbiter idle signal (such as a low level signal), and correspondingly, the signal threshold includes a first duration threshold thrT1 and a second duration threshold thrT2; if the duration T corresponding to the arbiter idle signal is greater than or equal to the first duration threshold thrT1, it indicates that the main memory is in an idle state, if the duration T is less than the first quantity threshold thrN1 and greater than or equal to the second duration threshold thrT2, it indicates that the main memory is in a low load state, and if the duration T is less than the second duration threshold thrT2, it indicates that the main memory is in a high load state; thrT1 is greater than thrT2.

[0053] Further, in some optional embodiments, the write-back operation of the target dirty data can be performed when the main memory is in a low load or idle state; in some optional embodiments, the write-back operation of the target dirty data can be performed only when the main memory is in an idle state, and the embodiments of the present disclosure do not limit this.

[0054] It should be noted that, in the case of obtaining a plurality of running index data and signal data, the running state of the main memory can be comprehensively judged, so as to obtain a more accurate and reasonable running state of the main memory.

[0055] For example, if the command queue depth and the number of memory access requests are all indicative of the main memory being in a low load state according to the corresponding preset load threshold, it can be determined that the main memory is in a low load state.

[0056] For example, if the command queue depth and the number of memory access requests are all indicative of the main memory being in a low load state according to the corresponding preset load threshold, the low load state corresponds to two votes, and the main memory is determined to be in an idle state according to the arbiter idle signal, the idle state corresponds to one vote, based on which, the low load state with more votes can be selected as the actual running state of the main memory.

[0057] In some optional embodiments, before writing the target dirty data in the cache back to the main memory, the method further comprises: selecting the target dirty data from the dirty data in the cache according to a preset dirty data flushing strategy.

[0058] The dirty data in the cache is the dirty data to be written back in the cache, and since the dirty data is written back when the main memory is in a low load state, a part of the dirty data in the cache needs to be selected and written back to the main memory first. In other words, the dirty data flushing strategy can indicate how to select the dirty data in the cache to be written back to the main memory first.

[0059] In some optional embodiments, the target dirty data can be selected by using the preset dirty data flushing strategy, in other words, the dirty data flushing strategy is a processing strategy for performing dirty data flushing.

[0060] In some optional embodiments, the dirty data can be in the form of dirty cache lines, and the embodiments of the present disclosure do not make any limitation in this regard.

[0061] In some optional embodiments, the dirty data refreshing strategy includes at least one of a polling refreshing strategy, a refreshing strategy based on an access interval length, and a random refreshing strategy; the polling refreshing strategy is used to sequentially detect dirty data in the cache data of the cache from a starting position, and select at least part of the detected dirty data as target dirty data according to preset write-back granularity information, the starting position is used to indicate a starting address of the dirty data in the cache detected this time; the refreshing strategy based on the access interval length is used to select at least part of the dirty data in the cache as the target dirty data according to an access interval length of the dirty data in the cache and the write-back granularity information; the random refreshing strategy is used to randomly select at least part of the dirty data in the cache as the target dirty data according to the write-back granularity information; the write-back granularity information is used to indicate a data amount of the dirty data written back at a time and / or a duration of the dirty data written back at a time.

[0062] Exemplarily, the write-back granularity information can represent that at most 4 rows of data (such as 512 bytes) are written back each time, and / or the duration of occupying the memory bus does not exceed a preset time limit (for example, 1 μs), so as to avoid long-time occupation of the memory bus and affect normal access operations.

[0063] Exemplarily, in a case where the dirty data refreshing strategy is the polling refreshing strategy, the system can maintain a position pointer, which can indicate the starting position, and the starting position can be an ending position of the last time when the target dirty data is selected. Further, if the write-back granularity information indicates that the data amount of the dirty data written back at a time is K, the dirty flag or the dirty data tag can be scanned according to the position indicated by the position pointer to find a cache row with a dirty flag of dirty, filter out the dirty cache row with the data amount of K as the target dirty data, and send the address of the target dirty data to the memory controller so as to perform the write-back operation on the target dirty data. If an access request for the main memory occurs during the write-back process, the scheduler can pause the subsequent write-back operation and preferentially complete the normal access. In addition, if the write-back granularity information indicates that the duration of the dirty data written back at a time is T, on one hand, the cache row with the dirty flag of dirty is found and sent to the memory controller, and on the other hand, the memory controller performs the write-back operation on the corresponding data according to the address, and after the dirty data write-back operation with the duration of T is performed, the write-back operation this time is completed.

[0064] Exemplarily, in a case where the dirty data refreshing strategy is the refreshing strategy based on the access interval length, the dirty cache row data far from the last access can be preferentially selected to be written back to the main memory.

[0065] For example, if the write-back granularity information indicates that the data volume of the dirty data to be written back in a single write-back is K, the dirty cache line with a data volume of K and a longer access duration from the current access can be selected as the target dirty data to be written back from the cache according to the Least Recently Used (LRU) order.

[0066] For example, if the write-back granularity information indicates that the data volume of the dirty data to be written back in a single write-back is K, the dirty cache line with a data volume of K and a longer access duration from the current access can be selected as the target dirty data to be written back from the cache according to the Least Recently Used (LRU) order.

[0067] It should be noted that when performing the dirty data write-back, a plurality of dirty data refresh strategies can be selected, such as using an access interval duration-based refresh strategy in the n th write-back and using a random refresh strategy in the n+1 th write-back, and the embodiments of the present disclosure do not limit this. In addition, the write-back operation on the target dirty data can follow the normal bus protocol, and no memory access conflict with the main memory is introduced due to the current write-back operation.

[0068] It should be further noted that in order to ensure that the above write-back operation does not affect normal business processing, after receiving a normal memory access request for the main memory, the write-back operation of the target dirty data needs to be interrupted in order to respond to the aforementioned memory access request in a timely manner. Among them, the normal memory access request is a conventional request for accessing the main memory, including a conventional read request and a write request for the main memory, and the normal memory access operation corresponding thereto is compared with the memory access operation generated by currently writing the target dirty data back to the main memory.

[0069] In some optional embodiments, the data processing method can further include: during the execution of the write-back of the target dirty data to the main memory, if a memory access request for the main memory is received, interrupting the write-back operation of the target dirty data and executing a memory access operation corresponding to the memory access request.

[0070] Among them, the interruption of the write-back operation can be immediate interruption, or the write-back operation of the subsequent target dirty data can be interrupted after the current write-back operation indicated by the write-back granularity information is completed, and the embodiments of the present disclosure do not limit this.

[0071] For example, based on the write-back granularity information, it is determined that the dirty data to be written back this time includes data1 to data5, and if a memory access request for the main memory is received while the write-back operation of the dirty data data3 is being performed, the write-back operation of data3 is directly interrupted, and the aforementioned memory access request is executed.

[0072] For example, if the write-back granularity information indicates that the dirty data to be written back this time includes data1 to data5, and a memory access request to the main memory is received while the write-back operation of the dirty data data3 is being performed, the write-back operation this time is continued until data5 is written back, and then the memory access request is executed.

[0073] It should be noted that in some optional embodiments, the dirty data written back to the main memory is not invalidated in the cache immediately, but can be retained in the cache as clean data after the dirty flag is cleared. Based on this, the subsequent processing core or processor such as GPU can still directly hit the cache when accessing this part of data, but if a data is modified again during data processing, the cache data corresponding to the data in the cache will be marked as dirty data again. In addition, in some optional embodiments, if the pre-configuration information requires that the dirty data written back to the main memory be cleared in the cache, the data can be deleted from the cache.

[0074] In some optional embodiments, after the target dirty data in the cache is written back to the main memory, the data processing method can further include: updating the dirty flag of the target dirty data in the cache from a first value to a second value; wherein the first value represents that the corresponding cache data is dirty data, and the second value represents that the corresponding cache data is clean data.

[0075] For example, after the target dirty data data1 in the cache is written back to the main memory, the dirty flag of data1 in the cache can be updated from "1" to "0", wherein the value of the dirty flag is "1" when the corresponding cache data is dirty data, and the value is "0" when the corresponding cache data is clean data.

[0076] The data processing method of the embodiments of the present disclosure will be described below. Figure 2 The data processing method of the embodiments of the present disclosure will be described below.

[0077] Figure 2 A schematic diagram of a data processing method provided by the embodiments of the present disclosure is shown. Referring to Figure 2 , the GPU implements data caching through the L2 cache and uses the DRAM as the main memory.

[0078] As Figure 2 shown, by detecting the state of the memory controller, it can be determined that the running load of the DRAM is lower than the preset load threshold. Further, if it is determined that the running load of the DRAM is lower than the preset load threshold, it can be determined that the DRAM is in an idle or low load state, based on which the L2 cache can be instructed to select the target dirty data and write the target dirty data back to the DRAM through the memory controller.

[0079] After the write-back operation of the target dirty data is completed, the dirty flag of the target dirty data that has been written back in the L2 cache can also be updated from the first value to the second value, so that the GPU can still directly hit the cache when accessing this part of data.

[0080] It should be noted that the above operation of writing back dirty data when the main memory is idle or low load can be performed multiple times. Based on this, by repeatedly writing back dirty data, the utilization rate of the memory bus can be balanced, which means that the idle bandwidth can be fully utilized to write back dirty data, and the normal data access will not be affected by excessive flushing (i.e., writing back dirty data).

[0081] In some optional embodiments, the dirty data includes intermediate operation data generated by the preset model during execution of the target task and stored in the cache in the form of a cache line; and the target task includes at least one of a text processing task, an image processing task, an audio processing task, and a video processing task.

[0082] For example, during the processing of the processor running the preset model to execute the target task, a plurality of dirty data (such as intermediate processing results) can be generated. This part of dirty data can be written back to the main memory during the idle or low load stage of the main memory during the inference of the preset model, so that the amount of data that needs to be written back to the main memory after the inference of the preset model is completed is reduced, and the performance jitter caused by synchronous write-back is reduced.

[0083] It should be noted that the data processing method of the embodiments of the present disclosure can be executed by an added flushing module. The flushing module is responsible for writing back the target dirty data to the main memory when the running load of the main memory is lower than the preset load threshold. In addition, the flushing module can be a hardware functional module, so that the data processing method of the embodiments of the present disclosure can be completely completed by hardware, without the participation of software, thereby not increasing the difficulty of software development and not affecting the normal operation of the existing application program. For the processing system such as the GPU system, the processing mechanism of the above-mentioned write-back dirty data is not perceived, so the consistency of the software and hardware interface is maintained.

[0084] In other words, the data processing method provided by the embodiments of the present disclosure introduces a fully hardware autonomous background flushing mechanism to gradually clean up the dirty data in the cache when the main memory is idle or low load, in order to solve the problems of bandwidth conflict and performance decline caused by the centralized write-back of the cache in the processing system. Therefore, part of the dirty data can be written back to the main memory in advance without triggering the normal replacement strategy, so as to reduce the memory traffic peak value during subsequent burst replacement, thereby improving the effective utilization rate of the main memory bandwidth and the system throughput performance, ensuring that the cache write-back process is transparent to the operating system and the application program (i.e., the system is not perceived), and thereby improving the performance stability of the processing system in the processing scene of long-time running and large data amount.

[0085] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form combined embodiments without deviating from the principle logic. Limited by the length of the present disclosure, the present disclosure will not be described again. Those skilled in the art can understand that in the above-mentioned method of the specific embodiment, the specific execution order of each step should be determined according to its function and possible internal logic.

[0086] In addition, the present disclosure also provides a data processing apparatus, a data processing device, an electronic device, and a computer readable storage medium, all of which can be used to implement any one of the data processing methods provided by the present disclosure. The corresponding technical solutions and descriptions are described in the method part and are not described again.

[0087] Figure 3 A block diagram of a data processing apparatus provided by an embodiment of the present disclosure.

[0088] Referring to Figure 3 The data processing apparatus provided by the embodiment of the present disclosure can include the following modules:

[0089] The determination module 301 is configured to determine the running state of the main memory.

[0090] The write-back module 302 is configured to write the target dirty data in the cache to the main memory in the case that the running state represents that the running load of the main memory is lower than the preset load threshold, the target dirty data being at least part of the dirty data in the cache.

[0091] The priority of writing the target dirty data to the main memory is lower than the priority of the normal memory access operation to the main memory.

[0092] The data processing apparatus of the embodiment of the present disclosure can refer to the related description of the above-mentioned data processing method, which will not be described again.

[0093] In the embodiment of the present disclosure, the running state of the main memory can be detected, and then it is determined whether the main memory is in a low load state or an idle state according to the running state, and at least part of the dirty data is written back to the main memory when it is determined that the main memory is in a low load state or an idle state, thereby reducing the amount of data to be written back to the dirty data, so that the access pressure on the main memory when indicating unified write-back can be effectively alleviated. In addition, since the write-back operation does not change the original dirty data refresh strategy and does not damage the data consistency, it does not introduce additional write conflicts, so it is a transparent operation without system awareness, and does not affect the existing data processing and user experience. In addition, by setting the priority of writing dirty data in a low load or idle state to be lower than the priority of the normal memory access operation to the main memory, the write of dirty data can be quickly interrupted when a normal memory access request is received, and the memory access request can be responded in time, without affecting the normal memory access operation.

[0094] Each of the modules in the data processing apparatus can be implemented wholly or partially by software, hardware, and a combination thereof. The modules can be embedded in or independent of a processor in the computer device in hardware form, or stored in a memory in the computer device in software form, so as to be invoked and executed by the processor to perform operations corresponding to the modules.

[0095] Figure 4 A block diagram of a data processing device according to an embodiment of the present disclosure is provided.

[0096] With reference to Figure 4 The data processing device 400 according to an embodiment of the present disclosure includes a main memory 410, a cache 420, a cache controller 421, and a state detection module 430.

[0097] The state detection module 430 is configured to determine a running state of the main memory 410, and send a refresh trigger signal to the cache 420 when the running state indicates that a running load of the main memory 410 is lower than a preset load threshold.

[0098] The cache 420 is configured to write target dirty data back to the main memory 410 through the cache controller 421 when the refresh trigger signal is received, the target dirty data being at least part of the dirty data in the cache 420.

[0099] The priority of writing the target dirty data back to the main memory 410 is lower than that of a normal memory access operation on the main memory 410.

[0100] It should be noted that the data processing device 400 can further include one or more processors or processing cores (not shown in the figure) for performing core data processing functions. In addition, compared with the related art, the data processing device 400 according to an embodiment of the present disclosure is additionally provided with the state detection module 430, which can monitor at least one of the command queue depth of the main memory 410, the number of memory access requests in a preset time period, and the arbiter signal in real time, so as to determine whether the memory bus is idle or busy, and further determine the running state of the main memory.

[0101] In some optional embodiments, the cache 420 includes a refresh module and a cache module; the refresh module is configured to send a refresh instruction signal to the cache controller 421 when the refresh trigger signal is received; and the cache controller 421 is configured to write the target dirty data from the cache module back to the main memory 410 when the refresh instruction signal is received.

[0102] It should be noted that in some optional embodiments, the refresh module can be independently arranged outside the cache 420 to perform the foregoing operations as an independent hardware function module in the data processing device 400, and the embodiments of the present disclosure do not make any limitation in this regard.

[0103] In some optional embodiments, the refresh module is configured to determine target dirty data from the dirty data in the cache 420 according to a preset dirty data refresh strategy, and generate a refresh instruction signal for instructing to write the target dirty data back to the main memory 410, the dirty data refresh strategy including at least one of a polling refresh strategy, an access interval duration-based refresh strategy, and a random refresh strategy; in the case that the dirty data refresh strategy is the polling refresh strategy, the refresh module is configured to sequentially detect the dirty data in the cache data of the cache 420 from a starting position, and select at least part of the detected dirty data as the target dirty data according to preset write-back granularity information, the starting position being used to indicate a starting address of detecting the dirty data in the cache 420 this time; in the case that the dirty data refresh strategy is the access interval duration-based refresh strategy, the refresh module is configured to select at least part of the dirty data in the cache 420 as the target dirty data according to an access interval duration of the dirty data in the cache 420 and the write-back granularity information; in the case that the dirty data refresh strategy is the random refresh strategy, the refresh module is configured to randomly select at least part of the dirty data in the cache 420 as the target dirty data according to the write-back granularity information; wherein the write-back granularity information is used to indicate a data amount of the dirty data in a single write-back and / or a duration of the dirty data in a single write-back.

[0104] In some optional embodiments, the state detection module 430 detects the running index data of the memory controller, and sends a refresh trigger signal to the cache 420 when it is determined according to the running index data that the main memory 410 is idle or low-load. The refresh module, upon receiving the refresh trigger signal, determines target dirty data from the dirty data in the cache 420 according to a preset dirty data refresh strategy, and generates a refresh instruction signal for instructing the target dirty data to be written back to the main memory 410, wherein the refresh instruction signal can include information such as the address of the target dirty data. Further, the refresh module sends the refresh instruction signal to the cache controller 421, and the cache controller 421 writes the corresponding target dirty data back to the main memory according to the refresh instruction signal. After the memory controller writes the target dirty data back to the main memory 410 according to the standard write-back process, it can return an acknowledgement signal to the refresh module, and the refresh module updates the dirty flag bit of the target dirty data that has been written back in the cache 420 to a clean identifier (i.e., clears the dirty flag bit). In other words, the cache line that has completed write-back is not invalidated in the cache 420 immediately, but is retained in the cache as clean data after the dirty flag is cleared. The data can still be directly hit in the cache when accessed by the subsequent processor. Through such a cycle, the utilization rate of the memory bus is improved, so that the idle bandwidth can be fully utilized to write back dirty data, and normal data access will not be affected by excessive refresh.

[0105] wherein for each refresh operation, the data amount of the cache lines that can be written back and / or the duration that can be written back can be preset to ensure that once a new high-priority storage request arrives, the refresh process can be quickly interrupted and the storage request can be responded to in time. When performing dirty data write-back, the same bus protocol as in the conventional replacement write-back can be used, but since it occurs during the idle or low-load period, it will not compete with other requests for bandwidth.

[0106] It should be noted that the main memory 410, the cache 420, the cache controller 421, and the state detection module 430 in the data processing device 400 are functional modules implemented based on corresponding hardware circuits, and the data control of such granularity shown in the data processing method is implemented by the hardware functional modules. The entire refresh process (i.e., the write-back operation of the target dirty data) can be completely automatically completed by hardware without the participation of software, so that the software development difficulty is not increased, and the normal operation of the existing application is not affected. The entire processing system (such as a GPU system) is not aware of this write-back mechanism, and the consistency of the software and hardware interfaces can be maintained.

[0107] The above modules can be embedded in or independent of the processor in the computer device in hardware form, so as to facilitate the processor to schedule the above modules to perform corresponding operations.

[0108] Figure 5A block diagram of an electronic device provided by an embodiment of the present disclosure.

[0109] With reference to Figure 5 An electronic device provided by an embodiment of the present disclosure includes at least one processor 501, at least one memory 502, and one or more I / O interfaces 503. The memory 502 stores one or more computer programs executable by the at least one processor 501. The one or more computer programs are executed by the at least one processor 501 to enable the at least one processor 501 to perform the data processing method described above.

[0110] Figure 6 A block diagram of an electronic device provided by an embodiment of the present disclosure.

[0111] With reference to Figure 6 An electronic device provided by an embodiment of the present disclosure includes a plurality of processing cores 601 and a network on chip 602. The plurality of processing cores 601 are connected to the network on chip 602. The network on chip 602 is configured to interact data between the plurality of processing cores 601 and external data.

[0112] The one or more processing cores 601 store one or more instructions. The one or more instructions are executed by the one or more processing cores 601 to enable the one or more processing cores 601 to perform the data processing method described above.

[0113] The modules in the electronic device described above can be implemented in whole or in part by software, hardware, or a combination thereof. The modules described above can be embedded in or independent of a processor in a computer device in hardware form, or stored in a memory in a computer device in software form, so as to be called and executed by a processor to perform operations corresponding to the modules described above.

[0114] An embodiment of the present disclosure further provides a computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the data processing method described above. The computer readable storage medium can be a volatile or non-volatile computer readable storage medium.

[0115] An embodiment of the present disclosure further provides a computer program product including computer readable code, or a non-volatile computer readable storage medium carrying the computer readable code. When the computer readable code is run in a processor of an electronic device, the processor in the electronic device performs the data processing method described above.

[0116] Those skilled in the art can understand that all or some of the steps in the methods disclosed above and the functional modules / units in the systems and devices can be implemented by software, firmware, hardware, or a combination thereof. In hardware implementation, the division between the functional modules / units referred to in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on computer-readable storage media, which can include computer storage media (or non-transitory media) and communication media (or transitory media).

[0117] As is well known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable program instructions, data structures, program modules or other data. Computer storage media include, but are not limited to, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), static random access memory (SRAM), flash memory or other memory technology, portable compact disc read only memory (CD-ROM), digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by a computer. Further, it is well known to those skilled in the art that communication media typically embodies computer readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. As a result, the desired information can be downloaded to various computing / processing devices from computer storage media or to external computers or external storage devices via networks, for example, the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in computer storage media within the respective computing / processing device.

[0118] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0119] Computer readable program instructions for carrying out operations of the present disclosure can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or any combination of one or more of the above in any combination, written in any combination of one or more programming languages, including object oriented programming languages such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0120] The computer program product described herein can be embodied in a specific manner by hardware, software, or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium. In another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK), and the like.

[0121] The various aspects of the present disclosure are described herein with reference to flow diagrams and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer readable program instructions.

[0122] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include a non-transitory computer readable storage medium that can be a computer- readable storage medium having no data storage cycles that change state. The instructions can be executed by one or more processors of a computer, other programmable data processing apparatus, or other devices to produce a computer-implemented process such that the instructions which execute via the one or more processors of the computer or other programmable data processing devices create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0123] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0124] The flow and block diagrams in the drawings show architectural, functional, and operational representations of possible implementations of systems, methods, and computer program products according to the present disclosure. In this regard, each block in the flow and block diagrams can represent a module, a segment, or a portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may

[0125] Example embodiments have been disclosed and, although a specific terminology is employed, it is merely for the convenience of the reader and is not intended to be limiting. In some instances, specific details have been included for the purpose of providing a thorough understanding of the embodiments presented, but it will be apparent to those skilled in the art that embodiments of the application can be practiced without these specific details. In some instances, features, characteristics and / or elements described in connection with a particular embodiment can be used in conjunction with, or switched to, features, characteristics and / or elements described in connection with other embodiments, unless otherwise explicitly stated. Accordingly, it will be understood that various changes in form and details can be made without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A data processing method, characterized in that, include: Determine the operating status of the main memory; When the operating state indicates that the operating load of the main memory is lower than a preset load threshold, the target dirty data in the cache is written back to the main memory, and the target dirty data is at least a portion of the dirty data in the cache; Specifically, writing the target dirty data back to the main memory has a lower priority than normal memory access operations to the main memory.

2. The method according to claim 1, characterized in that, Before writing the target dirty data in the cache back to the main memory, the method further includes: According to a preset dirty data refresh strategy, the target dirty data is selected from the dirty data in the cache; the dirty data refresh strategy includes at least one of a polling refresh strategy, a refresh strategy based on access interval, and a random refresh strategy; wherein... The polling refresh strategy is used to sequentially detect dirty data in the cache data of the cache from the starting position, and select at least a portion of the detected dirty data as the target dirty data according to the preset write-back granularity information. The starting position is used to indicate the starting address of the current detection of dirty data in the cache. The refresh strategy based on access interval duration is used to select at least a portion of the dirty data in the cache as the target dirty data according to the access interval duration of the dirty data in the cache and the write-back granularity information. The random refresh strategy is used to randomly select at least a portion of the dirty data in the cache as the target dirty data based on the write-back granularity information; The write-back granularity information is used to indicate the amount of dirty data written back in a single refresh operation and / or the duration of writing back dirty data in a single refresh operation.

3. The method according to claim 1 or 2, characterized in that, The method further includes: During the process of writing the target dirty data back to the main memory, if a memory access request for the main memory is received, the write-back operation of the target dirty data is interrupted, and the memory access operation corresponding to the memory access request is executed.

4. The method according to claim 1, characterized in that, After writing the target dirty data in the cache back to the main memory, the method further includes: Update the dirty flag of the target dirty data in the buffer from the first value to the second value; Wherein, the cached data corresponding to the first value is dirty data, and the cached data corresponding to the second value is clean data.

5. The method according to claim 1, characterized in that, Determining the operating state of the main memory includes: The operating state of the main memory is determined based on at least one of the following: the command queue depth corresponding to the main memory, the number of memory access requests within a preset time period, and the arbitrator signal.

6. The method according to claim 1 or 2, characterized in that, The dirty data includes intermediate computation data generated by the preset model during the execution of the target task and stored in the cache in the form of cache lines; The target task includes at least one of text processing, image processing, audio processing, and video processing tasks.

7. A data processing apparatus, characterized in that, include: The determination module is used to determine the operating status of the main memory; The write-back module is used to write target dirty data in the cache back to the main memory when the running state indicates that the running load of the main memory is lower than a preset load threshold. The target dirty data is at least a portion of the dirty data in the cache. Specifically, writing the target dirty data back to the main memory has a lower priority than normal memory access operations to the main memory.

8. A data processing device, characterized in that, include: Main memory, cache, cache controller, and status detection module; The status detection module is used to determine the operating status of the main memory, and send a refresh trigger signal to the cache when the operating status indicates that the operating load of the main memory is lower than a preset load threshold. The cache is configured to write target dirty data back to the main memory via the cache controller upon receiving the refresh trigger signal, wherein the target dirty data is at least a portion of the dirty data in the cache; Specifically, writing the target dirty data back to the main memory has a lower priority than normal memory access operations to the main memory.

9. The device according to claim 8, characterized in that, The cache includes a refresh module and a cache module; The refresh module is used to send a refresh instruction signal to the cache controller upon receiving the refresh trigger signal; The cache controller is configured to write the target dirty data back from the cache module to the main memory upon receiving the refresh indication signal.

10. The device according to claim 9, characterized in that, The refresh module is used to determine the target dirty data from the dirty data in the cache according to a preset dirty data refresh strategy, and generate a refresh indication signal to indicate that the target dirty data should be written back to the main memory. The dirty data refresh strategy includes at least one of a polling refresh strategy, a refresh strategy based on access interval duration, and a random refresh strategy. When the dirty data refresh strategy is the polling refresh strategy, the refresh module is used to sequentially detect dirty data in the cache data of the cache from the starting position, and select at least a portion of the detected dirty data as the target dirty data according to the preset write-back granularity information. The starting position is used to indicate the starting address of the current detection of dirty data in the cache. When the dirty data refresh strategy is the refresh strategy based on the access interval duration, the refresh module is used to select at least a portion of the dirty data in the cache as the target dirty data according to the access interval duration of the dirty data in the cache and the write-back granularity information; When the dirty data refresh strategy is the random refresh strategy, the refresh module is used to randomly select at least a portion of the dirty data in the cache as the target dirty data according to the write-back granularity information; The write-back granularity information is used to indicate the amount of dirty data written back in a single write-back and / or the duration of a single write-back of dirty data.

11. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs that can be executed by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the data processing method as described in any one of claims 1-6.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the data processing method as described in any one of claims 1-6.

13. A computer program product, characterized in that, It includes computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the data processing method as described in any one of claims 1-6.

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