Triggering reading method for time out-of-order data

Abstract

The invention discloses a trigger reading method for time out-of-order data, which comprises the following steps of: selecting the total depth of a hardware integrated cache, dividing a cache unit into a plurality of cache partitions, and mapping each cache partition with a corresponding time span on a time axis; determining the cache partition corresponding to the current data according to the mapping relationship between the cache partition and the time span, and reordering the time out-of-order data in the cache; constructing a global time counter according to a system clock, and obtaining a time range of trigger reading according to delay, offset and trigger window information of a system transmission trigger signal; according to the mapping relation between the cache partition and the time span, the cache partition range corresponding to the time range triggered to be read out is reversely determined, time information in the data is compared with the time range triggered to be read out, and all the data meeting the time range are screened out. According to the method, the time out-of-order data can be quickly sorted, so that the trigger reading speed is increased, and meanwhile, the cache capacity and the hardware complexity are reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method for triggering the reading of out-of-order time data. Background Technology

[0002] Triggered data readout using time information is a crucial technique widely needed in circuits and systems. For example, in physics experiments with high background noise and numerous background events, real-time triggered readout of large amounts of data is required. Selecting valid events in real-time from a large, continuous data stream within limited time and resources places high demands on the triggered readout of large amounts of out-of-order data. As experiments evolve towards higher speeds and brightness, not only is precise positional information required, but also accurate time and charge information is needed to correct timing errors and obtain more accurate experimental data. Precise measurement of multidimensional information also brings large-scale data channels and massive amounts of data. Therefore, rapid triggered readout is essential after obtaining multidimensional data to reduce the complexity of the transmission link and the storage pressure on the backend data processing system. Furthermore, time information measurement utilizes the leading edge of the analog signal to trigger a discriminator with a fixed threshold. The moment when the leading edge of the input signal exceeds the threshold is taken as timing information. Charge information measurement requires the trailing edge of the analog signal to cross the threshold. After digitization and framing, the final data is obtained and stored in a buffer according to the order of its generation, awaiting filtering. Within a pulse width range, new analog signals are constantly being generated, which causes the timing information in the sequentially output data stream to be out of order within the pulse width range of the analog signal.

[0003] The basic method of triggered read is that the system determines the time range for triggering read, then matches the time information in the data with the trigger time range to filter out valid data. If the time information in the data is sequential, it is only necessary to read the data sequentially for comparison; data shorter than the trigger time range can be discarded directly until the maximum boundary of the trigger time range is reached. However, for out-of-order data, it is necessary to search for matching data within at least a certain time range; data longer than the maximum value of the trigger time range still needs to be written back to the cache, waiting for the next trigger read. Although the time can be sorted sequentially when the data enters the cache, this faces problems such as excessive time complexity, severe cache unit consumption, unsuitability for large-scale data processing, and maintenance of complex cache unit read / write pointers. Using a read-and-compare approach, which does not satisfy the write-back requirement, is limited by experimental conditions; when the analog signal pulse width is large or the filtering frequency is high, it can lead to cache queue overflow.

[0004] In view of this, the present invention is hereby proposed. Summary of the Invention

[0005] The purpose of this invention is to provide a method for triggering the reading of out-of-time data, thereby solving the aforementioned technical problems in the prior art. The method described in this invention enables rapid sorting of out-of-time data, improving the triggering reading speed while reducing cache capacity and hardware complexity.

[0006] The objective of this invention is achieved through the following technical solution: A method for triggering the reading of out-of-time data, the method comprising: Step 1: Select the total depth of the hardware integrated cache, divide the cache unit into multiple cache partitions, allocate a corresponding cache depth to each cache partition, and then map each cache partition to the corresponding time span on the time axis. Step 2: Extract time information from the out-of-order data, determine the cache partition corresponding to the current data based on the mapping relationship between cache partition and time span, and obtain the mapping relationship between time information and cache address write pointer, and implement the reordering of out-of-order data in the cache; Step 3: Construct a global time counter based on the system clock, lock the global time corresponding to the trigger signal, and obtain the time range for trigger reading based on the delay, offset, and trigger window information of the system-transmitted trigger signal; Step 4: Based on the mapping relationship between cache partitions and time spans, reverse the process to determine the cache partition range corresponding to the time range that triggers the read. Read the data in each cache partition, compare the time information in the data with the time range that triggers the read, filter out all the data that meets the time range, and complete the trigger read process.

[0007] Compared with the prior art, the method provided by the present invention has the following advantages: 1) This invention maps out-of-order data to cache write pointers before writing the data to the cache partition. Since the time span between cache partitions is continuous, the cached data between partitions is arranged in chronological order on the long time axis, enabling rapid reordering of out-of-order data. 2) This invention determines the corresponding cache partition based on the time range of the trigger read. The data in each cache partition meets the filtering time range, so it can be directly compared and judged without repeatedly writing back to the cache, which can effectively reduce the time required for trigger read and the cache depth. 3) This invention adopts a strategy of randomization for short periods and sequentialization for long periods, which eliminates the need for complex sorting methods to trigger reading. In hardware implementation, it can be flexibly applied according to the experimental background, and the logic circuit is simple. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A schematic diagram of the method for triggering the reading of time-out-of-order data provided in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the mapping relationship between time information and cache read / write addresses according to an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the mapping relationship between cache partitions and cache write addresses according to an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the reordering process of time-disordered data in the example provided by the present invention. Figure 5 This is a schematic diagram illustrating the process of triggering the reading of out-of-order time data in an example of the present invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them, and do not constitute a limitation on the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0011] First, the following explanations are provided for the terms that may be used in this article: The term "and / or" means that either or both can be achieved simultaneously. For example, X and / or Y means that it includes both "X" or "Y" as well as the three cases of "X and Y".

[0012] The terms "comprising," "including," "containing," "having," or other similar semantic descriptions should be interpreted as non-exclusive inclusion. For example, including a technical feature element (such as raw material, component, ingredient, carrier, dosage form, material, size, part, component, mechanism, device, step, process, method, reaction conditions, processing conditions, parameter, algorithm, signal, data, product or article of manufacture, etc.) should be interpreted as including not only the expressly listed technical feature element, but also other technical feature elements that are not expressly listed and are well-known in the art.

[0013] The term "composed of" excludes any technical features not expressly listed. When used in a claim, it closes the claim to exclude all technical features other than those expressly listed, except for associated conventional impurities. If the term appears only in a clause of a claim, it limits the claim to the elements expressly listed in that clause; elements recited in other clauses are not excluded from the overall claim.

[0014] The technical solution provided by this invention will be described in detail below. Contents not described in detail in the embodiments of this invention are prior art known to those skilled in the art. Where specific conditions are not specified in the embodiments of this invention, they shall be performed according to conventional conditions in the art or conditions recommended by the manufacturer. Reagents or instruments used in the embodiments of this invention whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0015] like Figure 1 The diagram shows a flowchart of a method for triggering the reading of out-of-order time data according to an embodiment of the present invention. The method includes: Step 1: Select the total depth of the hardware integrated cache, divide the cache unit into multiple cache partitions, allocate a corresponding cache depth to each cache partition, and then map each cache partition to the corresponding time span on the time axis. In this step, the selection of the total cache depth is based on a comprehensive calculation of the rate and distribution of the simulated signal generation in the current experimental context, the delay time of the trigger signal for triggering readout, the rate and distribution of the trigger signal, and the read / write rate conditions of the cache; then, the minimum cache size required is determined in conjunction with the hardware implementation platform.

[0016] In the specific implementation, the product of the number of cache partitions in the cache unit and the cache depth within each cache partition is less than or equal to the total cache depth, as shown in equation (1): (1) in, This represents the total cache depth. The range for storing time information in the cache partition; The maximum number of units that can be cached within a single cache partition is calculated based on the analog signal generation rate and distribution. The maximum amount of data that can be generated within a given time frame; The total time span that the cache can cover is represented as: (2) in The delay time for the trigger signal; The processing time required to trigger the matching process depends on the read / write speed of the cache that the hardware platform can provide. The mapping relationship between cache partitions and time spans is adjusted according to experimental conditions. The optimal mapping relationship is selected, with the time span of the cache partition as the time interval, and the time span between each cache partition is guaranteed to increase continuously.

[0017] Step 2: Extract time information from the out-of-order data, determine the cache partition corresponding to the current data based on the mapping relationship between cache partition and time span, and obtain the mapping relationship between time information and cache address write pointer, and implement the reordering of out-of-order data in the cache; In this step, the cache address is written to the pointer. Calculate using the following formula: (3) in, This is the cache partition number; This represents the maximum number of cacheable units within a single cache partition. This represents the amount of data already stored in the cache partition.

[0018] like Figure 2 The diagram shows the mapping relationship between time information and cache read / write addresses according to an embodiment of the present invention. Out-of-order time data is written into the cache in the order of arrival, but the addresses to be written may be discontinuous according to the mapping relationship of time information.

[0019] Out-of-time data is reordered on a timeline constructed using the time span of cache partition mapping as the time interval, such as... Figure 3 The diagram illustrates the mapping relationship between cache partitions and cache write addresses according to an embodiment of the present invention. Within each cache partition, data is stored in the order of arrival, without needing to be sorted, i.e., out of order for a short period; however, the data between cache partitions is sequential over a long period.

[0020] In addition, after mapping the time information to the last cache partition, the mapping relationship between the time information and the cache partition is updated to keep the span of the cache partitions continuous on the time axis, and the time information is remapped starting from the first cache partition.

[0021] Step 3: Construct a global time counter based on the system clock, lock the global time corresponding to the trigger signal, and obtain the time range for trigger reading based on the delay, offset, and trigger window information of the system-transmitted trigger signal; In this step, the specific calculation formula is as follows: (4) (5) in, This is the lower limit of the time range for triggering the readout; The upper limit of the time range for triggering the read; The global time corresponding to the trigger signal; The delay time for triggering the signal; The offset time of the trigger signal; This refers to the trigger window time information for the trigger signal; The constructed global time counter is a cyclic counter, which locks the current global time each time a trigger signal is triggered. When calculating the current trigger read time range, because the global time counter has a fixed number of bits, such as a 12-bit counter, it counts to 2... 12 -1 then loops to 0, so in formulas (4) and (5), the carry relationship during the loop counting needs to be added to the calculation process.

[0022] Step 4: Based on the mapping relationship between cache partitions and time spans, reverse the determination of the cache partition range corresponding to the time range that triggers the read, read the data in each cache partition, compare the time information in the data with the time range that triggers the read, filter out all the data that meets the time range, and complete the trigger read process. In this step, the comparison formula is as follows: (6) in, This refers to the time information in the data; the time range used to trigger readouts increases incrementally on the time axis, and two adjacent trigger readout time ranges will not overlap. The first trigger readout time range... Time range until the second trigger read The cache partitions between them will not satisfy any of the triggers, so there is no need for read processing, and they can be directly written to overwrite. When new data is written, simply refresh the cache address write pointer to reduce the processing speed of triggering reads.

[0023] Based on the above method, this embodiment of the invention also provides a trigger-reading device for time-out-of-order data, the device comprising: The cache partition setting module is used to select the total depth of the hardware integrated cache, divide the cache unit into multiple cache partitions, allocate a corresponding cache depth to each cache partition, and then map each cache partition to the corresponding time span on the time axis. The time-out-of-order data reordering module is used to extract time information from time-out-of-order data, determine the cache partition corresponding to the current data according to the mapping relationship between cache partition and time span, and obtain the mapping relationship between time information and cache address write pointer, and realize the reordering of time-out-of-order data in the cache. The trigger readout time range determination module is used to construct a global time counter based on the system clock, lock the global time corresponding to the trigger signal, and obtain the trigger readout time range based on the delay, offset, and trigger window information of the system-transmitted trigger signal. The data filtering module is used to reverse the mapping relationship between cache partitions and time spans to determine the cache partition range corresponding to the time range that triggers the read, read the data in each cache partition, compare the time information in the data with the time range that triggers the read, filter out all data that meets the time range, and complete the trigger read process.

[0024] The specific implementation process of each module in the above device is described in the method embodiment.

[0025] This invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the method.

[0026] To more clearly demonstrate the technical solution and effects provided by the present invention, the method provided by the embodiments of the present invention will be described in detail below with reference to specific embodiments. In this example, the following conditions are met: the analog signal is generated according to a Poisson distribution with a generation rate of 30 MHz and an analog signal pulse width of 3 μs. The trigger signal for triggering readout also follows a Poisson distribution with a generation rate of 1 MHz and a trigger signal delay of 10 μs. The write rate of the buffer is 120 MHz, the read rate is 160 MHz, and 8 channels generate data together.

[0027] The method of this invention is based on the mapping of time information to address information, which can quickly realize the triggered reading of the above-mentioned time-out-of-order data, such as... Figure 4 The diagram shown illustrates the reordering process of time-disordered data in an example of this invention. Figure 5 The diagram illustrates the triggered reading process of out-of-order time data in an example of this invention, including the following steps: Step S1: Based on the experimental background requirements, simulate and obtain the appropriate total cache depth according to formulas (7) and (8). Scope of cache partition storage time information The number of cache partitions N and the maximum number of cacheable units within a single cache partition. .

[0028] in: (7) (8) in, Speed ​​of writing out-of-order data to the cache; For cache read data rate; The total time span that the cache can cover; The delay time for triggering the signal; The processing time required to trigger the matching process depends on the read / write speed of the cache that the hardware platform can provide.

[0029] In the current instance, the total cache depth is set to 4096, divided into 16 cache partitions. Each partition has a time span of 900 ns and a cache depth of 256. The time span between cache partitions is used as the time interval, ensuring that the time span between cache partitions increases continuously. A total of 14.4 μs of data can be cached. After this time interval, the data will be written back to the first partition.

[0030] Step S2: Extract time information from the out-of-order data, such as a time of 2 μs. Compare the time information with the time span of the cache partition to obtain the mapping between time and cache partition, and determine that the current data corresponds to the third cache partition.

[0031] Using the obtained cache partition number, the cache depth allocated to each cache partition, and the amount of data already stored in the cache partition, the mapping relationship between the time information in the data and the cache write address is obtained, that is, the current write address is 512 + the amount of data already stored.

[0032] Out-of-time data is written to the cache according to the above method, obtaining write address information. Data within each partition is stored out of time and does not require reordering, meaning it is out of order for a short period. Data between cache partitions is sequential in time, meaning it is ordered over a long period. Reordering is then performed on a timeline constructed using the time span mapped from the cache partitions as time intervals.

[0033] Step S3: Construct a global time counter based on the system clock. When the trigger signal for each readout arrives, lock the corresponding global time T1. Based on the system's transmitted trigger signal delay, offset, trigger window, and other information, obtain the time range for triggering the readout, i.e., the time range T1 to T2 corresponding to the valid data.

[0034] Step S4: Based on the time range of valid data and the time mapping relationship corresponding to the cache partition, such as T1 being 1.5 μs and T2 being 2.7 μs, read the data in the second and third cache partitions one by one, and compare the time information in the data with the time range of the trigger read to filter out all data that meet the time range and complete the trigger read process.

[0035] In summary, the method described in this invention utilizes the mapping of time information in the data to the cache write address, enabling real-time reordering over a long time range without consuming additional hardware resources. When triggering a read, the same mapping of time range to the cache read address is used to read and compare data within the cache partition, eliminating the need to repeatedly search through out-of-order data, thus reducing the trigger read time and hardware resource consumption.

[0036] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to those skilled in the art.

[0037] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A method for triggering the reading of time-out-of-order data, characterized in that, The method includes: Step 1: Select the total depth of the hardware integrated cache, divide the cache unit into multiple cache partitions, allocate a corresponding cache depth to each cache partition, and then map each cache partition to the corresponding time span on the time axis. Step 2: Extract time information from the out-of-order data, determine the cache partition corresponding to the current data based on the mapping relationship between cache partition and time span, and obtain the mapping relationship between time information and cache address write pointer, and implement the reordering of out-of-order data in the cache; Step 3: Construct a global time counter based on the system clock, lock the global time corresponding to the trigger signal, and obtain the time range for trigger reading based on the delay, offset, and trigger window information of the system-transmitted trigger signal; Step 4: Based on the mapping relationship between cache partitions and time spans, reverse the process to determine the cache partition range corresponding to the time range that triggers the read. Read the data in each cache partition, compare the time information in the data with the time range that triggers the read, filter out all the data that meets the time range, and complete the trigger read process.

2. The method for triggering and reading out-of-order time data according to claim 1, characterized in that, In step 1, the selection of the total cache depth is based on a comprehensive calculation of the rate and distribution of the simulated signal generation in the current experimental context, the delay time of the trigger signal for triggering readout, the rate and distribution of the trigger signal, and the read / write rate conditions of the cache; then, the minimum cache size required is determined in conjunction with the hardware implementation platform.

3. The method for triggering and reading out-of-order time data according to claim 1, characterized in that, In step 1, the product of the number of cache partitions in the cache unit and the cache depth within each cache partition is less than or equal to the total cache depth, as shown in equation (1): （1） in, This represents the total cache depth. The range for storing time information in the cache partition; The maximum number of units that can be cached within a single cache partition is calculated based on the analog signal generation rate and distribution. The maximum amount of data that can be generated within a given time frame; The total time span that the cache can cover is represented as: （2） in The delay time for the trigger signal; The processing time required to trigger the matching process depends on the read / write speed of the cache that the hardware platform can provide. The mapping relationship between cache partitions and time spans is adjusted according to experimental conditions. The optimal mapping relationship is selected, with the time span of the cache partition as the time interval, and the time span between each cache partition is guaranteed to increase continuously.

4. The method for triggering and reading out-of-order time data according to claim 1, characterized in that, In step 2, the cache address write pointer Calculate using the following formula: （3） in, This is the cache partition number; This represents the maximum number of cacheable units within a single cache partition. This represents the amount of data already stored in the cache partition.

5. The method for triggering and reading out-of-order time data according to claim 1, characterized in that, In step 2, the time-out-of-order data is reordered in the cache, specifically as follows: Out-of-time data is reordered on a timeline constructed using the time span of cache partition mapping as the time interval; Within each cache partition, data is stored in the order of arrival, without the need for sorting, meaning it is out of order for a short period of time; however, the data between cache partitions is sequential over a long period of time.

6. The method for triggering and reading out-of-order time data according to claim 1, characterized in that, In step 2, After mapping the time information to the last cache partition, the mapping relationship between the time information and the cache partition is updated to keep the span of the cache partitions continuous on the time axis, and the time information is remapped starting from the first cache partition.

7. The method for triggering and reading out-of-order time data according to claim 1, characterized in that, In step 3, the specific calculation formula is as follows: （4） （5） in, This is the lower limit of the time range for triggering the readout; The upper limit of the time range for triggering the read; The global time corresponding to the trigger signal; The delay time for triggering the signal; The offset time of the trigger signal; This refers to the trigger window time information for the trigger signal; The constructed global time counter is a cyclic counter, which locks the current global time each time a trigger signal is triggered. When calculating the current trigger read time range, since the global time counter has a fixed number of bits, the carry relationship during the loop count needs to be added to the calculation process in formulas (4) and (5).

8. The method for triggering and reading out-of-order time data according to claim 7, characterized in that, In step 4, the comparison formula is as follows: （6） in, This refers to the time information in the data; the time range used to trigger readouts increases incrementally on the time axis, and two adjacent trigger readout time ranges will not overlap. The first trigger readout time range... Time range until the second trigger read The cache partitions between them will not satisfy any of the triggers, so there is no need for read processing, and they can be directly written to overwrite. When new data is written, simply refresh the cache address write pointer to reduce the processing speed of triggering reads.

9. A device for triggering and reading out-of-order time data, characterized in that, The device includes: The cache partition setting module is used to select the total depth of the hardware integrated cache, divide the cache unit into multiple cache partitions, allocate a corresponding cache depth to each cache partition, and then map each cache partition to the corresponding time span on the time axis. The time-out-of-order data reordering module is used to extract time information from time-out-of-order data, determine the cache partition corresponding to the current data according to the mapping relationship between cache partition and time span, and obtain the mapping relationship between time information and cache address write pointer, and realize the reordering of time-out-of-order data in the cache. The trigger readout time range determination module is used to construct a global time counter based on the system clock, lock the global time corresponding to the trigger signal, and obtain the trigger readout time range based on the delay, offset, and trigger window information of the system-transmitted trigger signal. The data filtering module is used to reverse the mapping relationship between cache partitions and time spans to determine the cache partition range corresponding to the time range that triggers the read, read the data in each cache partition, compare the time information in the data with the time range that triggers the read, filter out all data that meets the time range, and complete the trigger read process.

10. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 8.

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