Advanced extensible interface bus anti-deadlock method and electronic equipment

Abstract

The invention provides an advanced extensible interface bus deadlock prevention method and electronic equipment. One write address channel cache is introduced into a write address channel; the method comprises the following steps: simultaneously receiving a first command sent by a write address channel and first data sent by a write data channel; when a first command is received, the received first command is sent to the slave device, meanwhile, the received first command is stored in the write address channel cache, and meanwhile, the write address channel is subjected to back pressure; sending the received first data to the slave device; and when the WLAST signal is at a high level, relieving the back pressure of the write address channel, and repeating the steps of sending the received first command to the slave device, storing the received first command in the write address channel cache and back-pressing the write address channel when the first command is received and the subsequent steps. According to the method, deadlock prevention can be achieved through one write address channel cache, and cavitation bubbles cannot be generated.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an advanced scalable interface bus anti-deadlock method and electronic device. Background Technology

[0002] In the implementation of the AXI (Advanced eXtensible Interface) bus, a write operation deadlock prevention mechanism, namely the Single Active Slave (SAS) mechanism, was introduced.

[0003] Existing write operation deadlock prevention mechanisms introduce caches for the write address channel (AW) and the write data channel (W), and implement them through a restriction policy (i.e., the write data channel (W) can only be sent after the write address channel (AW) has been completed).

[0004] like Figure 1 As shown, the write address channel (AW) introduces two caches (such as...). Figure 1 In the AW channel cache 1 and AW channel cache 2), the write data channel (W) introduces one cache (such as... Figure 1 (W channel cache in the middle).

[0005] For write operations, the write address channel (AW) buffers two first commands. If the first command is AW data, one AW data is buffered in AW channel buffer 1, and the other in AW channel buffer 2. Similarly, the first data in the write data channel (W), if it's W data, is buffered in the W channel buffer. The corresponding AW data is sent after arriving at the AW channel buffer, causing backpressure on the write data channel (W). During a write operation, when the master device sends data through the write data channel (W), the WLAST signal is low, and it is pulled high during the transmission of the last data packet. This indicates that the current data transmission is the last data packet of the current write transaction. New AW data is only sent after the WLAST signal of the write data channel (W) goes high. This causes cavitation during transmission in the write data channel, such as... Figure 2 As shown. Summary of the Invention

[0006] To address one of the aforementioned technical deficiencies, this application provides an advanced scalable interface bus anti-deadlock method and electronic device.

[0007] The first aspect of this application provides a deadlock prevention method for an Advanced Scalable Interface Bus (ASPA), wherein the write address channel of the ASPA introduces a write address channel cache. The method includes: Simultaneously receive the first command sent by the master device through the write address channel and the first data sent by the master device through the write data channel; When a first command is received, the received first command is sent to the slave device. At the same time, the received first command is stored in the write address channel buffer, and the write address channel is pressured back. Send the first received data to the slave device; When the WLAST signal is high, the reverse pressure of the write address channel is released, and the process of sending the received first command to the slave device and storing the received first command in the write address channel buffer is repeated. At the same time, the write address channel is reverse-pressurized, and subsequent steps are repeated.

[0008] Optionally, the write data channel of the Advanced Extensible Interface Bus introduces one flag bit; The initial value of the flag is the first value; When a first command is received, update the flag to the second value; The first received data is sent to the slave device, including: When the flag is at the second value, the received first data is sent to the slave device; When the WLAST signal is high, the reverse voltage of the write address channel is released, including: When the WLAST signal is high, update the flag bit to the first value; When the flag is at its first value, the back pressure on the write address channel is released.

[0009] Optionally, this method is implemented through the first-level selection logic of the high-level extensible interface bus matrix; The advanced scalable interface bus matrix includes: multi-level selection logic; The first-level selection logic is connected to the master device; The final selection logic is connected to the slave device; The first-level selection logic also includes deadlock prevention logic; the number of levels in the multi-level selection logic is determined according to the floorplan.

[0010] Optionally, the higher-level selection logic outputs a selection signal to the lower-level selection logic.

[0011] Optionally, the selection logic in the register also includes a timing logic.

[0012] Optionally, the received first command is sent to the slave device, including: The first received command is sent to the slave device through the lower-level selection logic; The first received data is sent to the slave device, including: The first received data is sent to the slave device through the lower-level selection logic.

[0013] Optionally, the first-level selection logic is connected to the main device through the main execution module; The final-level selection logic connects to the slave device through the execution module; The main execution module is used to monitor the main device and take over the main device when it malfunctions. The execution module is used to monitor the slave device and take over the slave device when it malfunctions.

[0014] Optionally, the execution module includes: a write data buffer, a read data buffer, a write command first-in-first-out queue, a slave state machine, and a slave synchronization module; Among them, the write data buffer, read data buffer, and write command first-in-first-out queue are connected to the advanced extensible interface bus matrix, and the write data buffer, read data buffer, and write command first-in-first-out queue are also connected to the slave state machine. Establish a path between the synchronization module and the slave state machine; The state machine also establishes a path with the advanced scalable interface bus matrix, and at the same time, it establishes a path with the slave device. The slave state machine is used to receive write command response data and / or read command response data from the slave device; wherein the write command response data includes at least: a first identifier ID of the responding write command; and the read command response data includes at least: a second ID of the responding read command and the data read length corresponding to the read command. The write data buffer is used to cache write command response data and handle the transmission of write response channels; The read data buffer is used to cache the third ID of the read command transmitted through the read address channel and the target read length corresponding to the read command, cache the read command response data, and process the transmission of the read data channel. The write command first-in-first-out queue is used to store the fourth ID of the write command transmitted through the write address channel; The synchronization module is used to synchronize the slave device's slave takeover enable signal when the slave device malfunctions. The state machine is also used to enable slave device takeover based on read data buffer and / or write data buffer, and write command first-in-first-out queue after synchronizing to the slave takeover enable signal; and to stop slave device takeover after the slave takeover enable signal is released and the stop condition is met.

[0015] Optionally, the main execution module includes: a main state machine, a main synchronization module, and an interception module; Among them, the main synchronization module and the interception module establish a communication path; The master state machine establishes a communication channel with the interception module, and at the same time, the interception module establishes a communication channel with the master device; The master state machine also establishes a path with the advanced scalable interface bus matrix, and at the same time, the master state machine establishes a path with the master device; The master synchronization module is used to synchronize the master takeover enable signal of the master device when the master device is malfunctioning. The master state machine stores the data transmission length of the first data sent through the write data channel. After synchronizing with the master takeover enable signal, it starts the takeover of the master device based on the data transmission length. After the master takeover enable signal is released and the stop condition is met, it stops the takeover of the master device. The interception module is used to intercept the first data sent by the write data channel after the master device takes over, before the address channel handshake is completed.

[0016] A second aspect of this application provides an electronic device including an advanced scalable interface bus matrix; The Advanced Extensible Interface Bus (AEMB) matrix implements the AEMB anti-deadlock method as described in the first aspect above.

[0017] This application provides a deadlock prevention method and electronic device for an Advanced Scalable Interface (ASPI) bus. The ASPI bus incorporates a write address channel buffer in its write address channel. The method includes: simultaneously receiving a first command sent by a master device via the write address channel and first data sent by the master device via the write data channel; upon receiving a first command, sending the received first command to a slave device and storing the received first command in the write address channel buffer, while simultaneously applying back pressure to the write address channel; sending the received first data to the slave device; and when the WLAST signal is high, releasing the back pressure on the write address channel and repeating the steps of sending the received first command to the slave device, storing the received first command in the write address channel buffer, and applying back pressure to the write address channel, as well as subsequent steps. The method provided in this application achieves deadlock prevention through a single write address channel buffer, avoiding cavitation. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram illustrating the principle of an existing advanced scalable interface bus for preventing deadlock. Figure 2 A schematic diagram illustrating the principle of deadlock prevention for another existing advanced scalable interface bus; Figure 3 A schematic diagram illustrating the principle of the first advanced scalable interface bus anti-deadlock method provided in the embodiments of this application; Figure 4 A flowchart illustrating an advanced scalable interface bus anti-deadlock method provided in this application embodiment; Figure 5 A schematic diagram illustrating the principle of the second advanced scalable interface bus anti-deadlock method provided in this application embodiment; Figure 6 A schematic diagram illustrating the principle of the third advanced extensible interface bus anti-deadlock method provided in the embodiments of this application; Figure 7 A schematic diagram illustrating the principle of the fourth advanced scalable interface bus anti-deadlock method provided in the embodiments of this application; Figure 8 A schematic diagram of the structure of the first type of advanced scalable interface bus matrix provided in the embodiments of this application; Figure 9 This is a schematic diagram of the structure of a second type of advanced scalable interface bus matrix provided in an embodiment of this application; Figure 10 A schematic diagram of the structure of the third type of advanced scalable interface bus matrix provided in the embodiments of this application; Figure 11 A schematic diagram of the structure of the fourth type of advanced scalable interface bus matrix provided in the embodiments of this application; Figure 12 This is a schematic diagram of the structure of a first type of main execution module provided in an embodiment of this application; Figure 13 This is a schematic diagram of the structure of a second type of main execution module provided in an embodiment of this application; Figure 14 This is a schematic diagram of the structure of a third type of main execution module provided in an embodiment of this application; Figure 15 This is a schematic diagram of the structure of a first execution module provided in an embodiment of this application; Figure 16 This is a schematic diagram of the structure of a second execution module provided in an embodiment of this application; Figure 17 This is a schematic diagram of the third type of execution module provided in the embodiments of this application. Detailed Implementation

[0019] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0020] In developing this application, the inventors discovered that existing write operation deadlock prevention mechanisms introduce buffers for the write address channel (AW) and the write data channel (W), implemented through a restriction strategy (i.e., the write data channel (W) can only be sent after the write address channel (AW) has finished sending). For write operations, the write address channel (AW) buffers two first commands. If the first command is AW data, one AW data is buffered in AW channel buffer 1, and the other AW data is buffered in AW channel buffer 2. The first data of the write data channel (W), if the first data is W data, is buffered in the W channel buffer. Sending the corresponding AW data after it arrives in the AW channel buffer causes backpressure on the write data channel (W). Furthermore, new AW data is only sent after the WLAST signal is high, which causes cavitation during the transmission of the write data channel.

[0021] To address the aforementioned problems, this application provides an Advanced Scalable Interface Bus (ASPA) anti-deadlock method and electronic device. The ASPA's write address channel incorporates a write address channel buffer. The method includes: simultaneously receiving a first command sent by a master device via the write address channel and first data sent by the master device via the write data channel; upon receiving a first command, sending the received first command to a slave device and storing the received first command in the write address channel buffer, while simultaneously applying back pressure to the write address channel; sending the received first data to the slave device; and when the WLAST signal is high, releasing the back pressure on the write address channel, repeating the steps of sending the received first command to the slave device, storing the received first command in the write address channel buffer, and applying back pressure to the write address channel, and subsequent steps. The method provided in this application achieves anti-deadlock through a single write address channel buffer, preventing cavitation.

[0022] This embodiment provides a deadlock prevention method for the Advanced Extensible Interface (AXI) bus, wherein the write address channel (AW) of the AXI bus introduces a write address channel cache (such as an AW channel cache), such as... Figure 3 As shown.

[0023] based on Figure 3 The implementation process of the Advanced Extensible Interface (AXI) bus deadlock prevention method provided in this embodiment is as follows: Figure 4 As shown: 401, simultaneously receives the first command sent by the master device through the write address channel and the first data sent by the master device through the write data channel.

[0024] In step 401, the first data will be continuously received. The first command will also be continuously received even when there is no backpressure on the write address channel (AW).

[0025] 402. When a first command is received, the received first command is sent to the slave device. At the same time, the received first command is stored in the write address channel buffer, and the write address channel is pressured back.

[0026] If the write address channel cache is empty, the first received command is directly stored in the write address channel cache. If the write address channel cache is not empty, the write address channel cache is first cleared, and then the first received command is stored in the write address channel cache.

[0027] 403, send the received first data to the slave device.

[0028] 404. When the WLAST signal is high, release the reverse pressure of the write address channel and repeat the process of sending the received first command to the slave device when a first command is received, storing the received first command in the write address channel buffer, and simultaneously reversing the write address channel and subsequent steps (i.e., steps 402 to 404) until all data has been received.

[0029] According to the AXI protocol specification, the WLAST signal is part of the write data channel (W) and is sent along with the data (i.e., the first data). That is, during a write operation, when the master device sends data (i.e., the first data) through the write data channel (W), the WLAST signal is pulled high (becomes a high level) during the transmission of the last data packet. This indicates that the current data (i.e., the first data) transmission is the last data packet of the current write transaction. As part of the write data channel (W), the transmission of the WLAST signal is synchronized with the data (i.e., the first data), ensuring that the end of data (i.e., the first data) transmission can be identified in a timely manner at the final stage of data transmission, avoiding data loss or misprocessing.

[0030] Therefore, in step 404, when the WLAST signal is high, it indicates that the first data corresponding to the first command in the write address channel buffer has been sent. Thus, the back pressure of the write address channel (AW) can be released so as to receive the first data corresponding to the next first command. That is, the steps of sending the received first command to the slave device and storing the received first command in the write address channel buffer, and back pressure on the write address channel (AW) and subsequent steps (i.e., steps 402 to 404) are repeated.

[0031] It should be noted that the above description is only in the order of steps 401, 402, 403, and 404. In specific implementation, this embodiment and subsequent embodiments do not limit the execution order of steps 401, 402, 403, and 404.

[0032] For example, the master device writes to the address channel (AW, such as...) Figure 3 The master device AW channel and write data channel (W, such as...) Figure 3 The master device (W channel) simultaneously sends data. For example, the master device sends AW0 and AW1 sequentially at different times through the write address channel (AW), and the master device sends W01, W02, W03, W04, W11, and W12 sequentially at different times through the write data channel (W).

[0033] Since AW0 and AW1 are not sent at the same time, they will not be received at the same time either. Similarly, W01, W02, W03, W04, W11, and W12 are not sent at the same time, and therefore will not be received at the same time either.

[0034] like Figure 5 As shown, at time t0, the first command sent by the master device through the write address channel (AW) is simultaneously received in step 401 (e.g., ...). Figure 5 The first data (such as AW0 in the middle) and the master device sent through the write data channel (W) are... Figure 5 (W01 in the middle), and as Figure 5 As shown, the WLAST signal of the write data channel (W) is low at time t0. When AW0 is received at time t0 (i.e., a first command is received), the received first command (such as...) will be sent to the data channel (W) via step 402. Figure 5 The AW0 in the middle is sent to the slave device, and at the same time, the first command received (such as...) is sent to the slave device. Figure 5 AW0 in the address channel cache (e.g.) is stored in the write address channel cache. Figure 3 In the AW channel cache), at the same time, the reverse pressure write address channel (AW, such as...) is also in the cache. Figure 3 The master device AW channel in the middle). At the same time, the first data received (such as) is processed through step 403. Figure 5 The W01 in the middle is sent to the slave device.

[0035] At time t1, the first data sent by the master device through the write data channel (W) is still received via step 401 (e.g., ...). Figure 5 As shown in W02), and as Figure 5 As shown, at time t1, the WLAST signal of the write data channel (W) is low. This is because at this time, the write address channel (AW, as shown...) is also low. Figure 3 The master device's AW channel is back-pressurized, therefore the first command sent by the master device through the write address channel (AW) will not be received in step 401, and the write address channel buffer (such as...) Figure 3 AW0 is still stored in the AW channel buffer. Meanwhile, at time t1, the received first data (such as...) will be processed through step 403. Figure 5 The W02 shown is sent to the slave device.

[0036] At time t2, the first data sent by the master device through the write data channel (W) is still received via step 401 (e.g., ...). Figure 5 As shown in W03), and as Figure 5 As shown, at time t2, the WLAST signal of the write data channel (W) is low. This is because at this time, the write address channel (AW, as shown...) is also low. Figure 3 The master device's AW channel is back-pressurized, therefore the first command sent by the master device through the write address channel (AW) will not be received in step 401, and the write address channel buffer (such as...) Figure 3 AW0 is still stored in the AW channel buffer. Meanwhile, at time t2, the received first data (such as...) will be processed through step 403. Figure 5 The W03 shown is sent to the slave device.

[0037] At time t3, the first data sent by the master device through the write data channel (W) is still received via step 401 (e.g., ...). Figure 5 As shown in W04), but as Figure 5 As shown, at time t3, the WLAST signal of the write data channel (W) is high, thus the reverse voltage of the write address channel (AW) is released in step 404. Since the reverse voltage of the write address channel (AW) is released, at time t3, in step 401, the first command sent by the master device through the write address channel (AW) will also be received (e.g., ...). Figure 3 (AW1 in the middle), and at the same time, clear the write address channel cache (such as AW1 in the middle). Figure 3 (in the AW channel cache), and store AW1 in the write address channel cache (such as Figure 3 In the AW channel cache), at the same time, the reverse pressure write address channel (AW, such as...) is also in the cache. Figure 3 The master device AW channel). At the same time, at time t3, the first command received (such as...) will be transmitted through step 402. Figure 5 The AW1 in the middle is sent to the slave device, and the first data received (such as AW1 in the middle) is sent to the slave device through step 403. Figure 5 The W04 shown is sent to the slave device.

[0038] At time t4, the first data sent by the master device through the write data channel (W) is still received via step 401 (e.g., ...). Figure 5 As shown in W11), and as Figure 5 As shown, at time t4, the WLAST signal of the write data channel (W) is low. This is because at this time, the write address channel (AW, as shown...) is also low. Figure 3 The master device's AW channel is back-pressurized, therefore the first command sent by the master device through the write address channel (AW) will not be received in step 401, and the write address channel buffer (such as...) Figure 3 AW1 is still stored in the AW channel buffer. Meanwhile, at time t4, the received first data (such as...) will be processed through step 403. Figure 5 The W11 shown is sent to the slave device.

[0039] At time t5, the first data sent by the master device through the write data channel (W) is still received via step 401 (e.g., ...). Figure 5 As shown in W12), and as Figure 5 As shown, at time t5, the WLAST signal of the write data channel (W) is low. This is because at this time, the write address channel (AW, as shown...) is also low. Figure 3 The master device's AW channel is back-pressurized, therefore the first command sent by the master device through the write address channel (AW) will not be received in step 401, and the write address channel buffer (such as...) Figure 3 AW1 is still stored in the AW channel buffer. Meanwhile, at time t5, the received first data (such as...) will be processed through step 403. Figure 5 The W12 shown is sent to the slave device.

[0040] … This process is repeated until all write data sent by the master device has been received.

[0041] Taking one master device and three slave devices as an example, an exemplary schematic diagram of the advanced scalable interface bus anti-deadlock method provided in this embodiment is shown below. Figure 6 As shown.

[0042] Additionally, in practical implementations, the write data channel (W) of the tier scalable interface bus can also introduce a flag bit, such as... Figure 7 As shown. The flag bit occupies 1 bit. The initial value of the flag bit is the first value, such as 0.

[0043] This flag indicates whether the write address channel (AW) has received data (i.e., the first command).

[0044] In this case, step 401 will still simultaneously receive the first command sent by the master device through the write address channel (AW) and the first data sent by the master device through the write data channel (W). However, when a first command is received, the flag bit will be updated to a second value, such as 1. That is, when the flag bit is 0, it means that the write address channel (AW) has not received data (i.e., the first command), and when the flag bit is 1, it means that the write address channel (AW) has received data (i.e., the first command).

[0045] In step 402, when a first command is received, the received first command is sent to the slave device. At the same time, the received first command is stored in the write address channel buffer, and the write address channel (AW) is reverse-pressured.

[0046] The process of sending the received first data to the slave device in step 403 is as follows: when the flag bit is the second value, the received first data is sent to the slave device. That is, the first data is only sent to the slave device after the write address channel (AW) receives the data (i.e., the first command).

[0047] In step 404, when the WLAST signal is high, the process of releasing the reverse pressure of the write address channel (AW) is as follows: when the WLAST signal is high, the flag bit is updated to the first value, and when the flag bit is the first value, the reverse pressure of the write address channel (AW) is released. That is, when the WLAST signal of the write data channel (W) is high, it indicates that the first data corresponding to the current first command has been received. Upon receiving more first data, it should correspond to a new first command, therefore the flag bit is updated to the first value, thus stopping the transmission of first data to the slave device. Then, when the flag bit is the first value, the reverse pressure of the write address channel (AW) is released so that when step 401 is executed again, the first command sent by the master device through the write address channel (AW) will be received again. This process is repeated. When a first command is received, the received first command is sent to the slave device, and simultaneously, the received first command is stored in the write address channel buffer (e.g., ...). Figure 3 In the AW channel buffer, at the same time, the reverse pressure write address channel (AW) step and subsequent steps (i.e., steps 402 to 404) are performed until all data is received.

[0048] If the first command is received again, the flag will be updated to the second value, and then the second value received subsequently will be sent to the slave device after the flag is updated to the second value.

[0049] Similarly, for the implementation scheme of introducing one write address channel cache (such as AW channel cache) for the write address channel (AW) and one flag bit for the write data channel (W), the above description is only based on the order of steps 401, 402, 403 and 404. In specific implementation, this embodiment and subsequent embodiments do not limit the execution order of steps 401, 402, 403 and 404.

[0050] Still with Figure 5 For example, the master device writes to the address channel (AW, such as...) Figure 3 The master device AW channel and write data channel (W, such as...) Figure 3 The master device (W channel) simultaneously transmits data. For example, the master device transmits AW0 and AW1 sequentially at different times through the write address channel (AW), and transmits W01, W02, W03, W04, W11, and W12 sequentially at different times through the write data channel (W). The initial value of the flag bit is 0.

[0051] At time t0, in step 401, the first command sent by the master device through the write address channel (AW) is simultaneously received (e.g., ...). Figure 5 The first data (such as AW0 in the middle) and the master device sent through the write data channel (W) are... Figure 5 (W01 in the middle), and as Figure 5 As shown, at time t0, the WLAST signal of the write data channel (W) is low. When AW0 is received at time t0 (i.e., a first command is received), the flag bit is updated to 1 (i.e., the second value), and the received first command (such as...) is updated in step 402. Figure 5 The AW0 in the middle is sent to the slave device, and at the same time, the first command received (such as...) is sent to the slave device. Figure 5 AW0 in the address channel cache (e.g.) is stored in the write address channel cache. Figure 3 In the AW channel cache), at the same time, the reverse pressure write address channel (AW, such as...) is also in the cache. Figure 3 The master device AW channel in the middle). At the same time, the first data received (such as) is processed through step 403. Figure 5 The W01 in the middle is sent to the slave device.

[0052] At time t1, the first data sent by the master device through the write data channel (W) is still received via step 401 (e.g., ...). Figure 5 As shown in W02), and as Figure 5 As shown, at time t1, the WLAST signal of the write data channel (W) is low. This is because at this time, the write address channel (AW, as shown...) is also low. Figure 3 The master device's AW channel is back-pressurized, therefore the first command sent by the master device through the write address channel (AW) will not be received in step 401, and the write address channel buffer (such as...) Figure 3 AW0 is still stored in the AW channel buffer. Meanwhile, the flag bit is 1 (i.e., the second value), so at time t1, the received first data (such as...) will be processed through step 403. Figure 5 The W02 shown is sent to the slave device.

[0053] At time t2, the first data sent by the master device through the write data channel (W) is still received via step 401 (e.g., ...). Figure 5 As shown in W03), and as Figure 5 As shown, at time t2, the WLAST signal of the write data channel (W) is low. This is because at this time, the write address channel (AW, as shown...) is also low. Figure 3 The master device's AW channel is back-pressurized, therefore the first command sent by the master device through the write address channel (AW) will not be received in step 401, and the write address channel buffer (such as...) Figure 3 AW0 is still stored in the AW channel buffer. Meanwhile, the flag is set to 1 (i.e., the second value), and at time t2, the received first data (such as...) will be processed through step 403. Figure 5 The W03 shown is sent to the slave device.

[0054] At time t3, the first data sent by the master device through the write data channel (W) is still received via step 401 (e.g., ...). Figure 5 As shown in W04), but as Figure 5 As shown, at time t3, the WLAST signal of the write data channel (W) is high, therefore the flag bit is updated to 0 in step 404, and when the flag bit is 0, the reverse pressure of the write address channel (AW) is released. Since the reverse pressure of the write address channel (AW) is released, at time t3, in step 401, the first command sent by the master device through the write address channel (AW) will also be received (such as...). Figure 3 (AW1 in the middle), and at the same time, clear the write address channel cache (such as AW1 in the middle). Figure 3 (in the AW channel cache), and store AW1 in the write address channel cache (such as Figure 3 In the AW channel cache), at the same time, the reverse pressure write address channel (AW, such as...) is also in the cache. Figure 3 The master device AW channel). When AW1 is received at time t3 (i.e., a first command is received), the flag bit will be updated to 1 (i.e., the second value). At the same time, at time t3, the received first command (such as...) will be updated through step 402. Figure 5 The AW1 in the middle is sent to the slave device, and the first data received (such as AW1 in the middle) is sent to the slave device through step 403. Figure 5 The W04 shown is sent to the slave device.

[0055] At time t4, the first data sent by the master device through the write data channel (W) is still received via step 401 (e.g., ...). Figure 5 As shown in W11), and as Figure 5 As shown, at time t4, the WLAST signal of the write data channel (W) is low. This is because at this time, the write address channel (AW, as shown...) is also low. Figure 3 The master device's AW channel is back-pressurized, therefore the first command sent by the master device through the write address channel (AW) will not be received in step 401, and the write address channel buffer (such as...) Figure 3 AW1 is still stored in the AW channel buffer. Meanwhile, the flag is set to 1 (i.e., the second value), and at time t4, the received first data (such as...) will be processed through step 403. Figure 5 The W11 shown is sent to the slave device.

[0056] At time t5, the first data sent by the master device through the write data channel (W) is still received via step 401 (e.g., ...). Figure 5 As shown in W12), and as Figure 5 As shown, at time t5, the WLAST signal of the write data channel (W) is low. This is because at this time, the write address channel (AW, as shown...) is also low. Figure 3The master device's AW channel is back-pressurized, therefore the first command sent by the master device through the write address channel (AW) will not be received in step 401, and the write address channel buffer (such as...) Figure 3 AW1 is still stored in the AW channel buffer. Meanwhile, the flag is set to 1 (i.e., the second value), and at time t5, the received first data (such as...) will be processed through step 403. Figure 5 The W12 shown is sent to the slave device.

[0057] … This process is repeated until all write data sent by the master device has been received.

[0058] In this way, by writing to the address channel cache (such as...) Figure 3 The AW channel cache in the middle represents the first command corresponding to the first data. The flag bit indicates that the first command has been received. Thus, the write operation can be completed with a cache and 1 bit to prevent deadlock.

[0059] In addition, in specific implementation, the Advanced Extensible Interface (AXI) bus anti-deadlock method provided in this embodiment is implemented through the first-level selection logic of the Advanced Extensible Interface (AXI) bus matrix.

[0060] The Advanced Extensible Interface (AXI) bus matrix includes multi-level selection logic.

[0061] The number of levels in the multi-level selection logic can be determined based on the floorplan. In other words, the number of levels and the branching of each level of selection logic are entirely determined by the backend physical implementation of the floorplan. This embodiment does not limit the number of levels or the branching of each level of selection logic. This embodiment also does not limit the method for determining the floorplan or the content of the floorplan.

[0062] The first-level selection logic is connected to the master device, and the last-level selection logic is connected to the slave device.

[0063] The first-level selection logic includes deadlock prevention logic to prevent deadlocks. In addition, it includes decoding logic for address decoding.

[0064] In practical implementation, within the multi-level selection logic, only the first-level selection logic includes deadlock prevention and decoding logic; subsequent selection logics do not. In other words, only the initial selection logic within the Advanced Extensible Interface (AXI) bus matrix contains deadlock prevention and decoding logic; subsequent selection logics do not.

[0065] In addition, the Advanced Extensible Interface (AXI) bus matrix may not contain logical registers.

[0066] In addition, the higher-level selection logic outputs a selection signal to the lower-level selection logic. That is to say, the higher-level selection logic is cascaded, and the selection signal output by the first-level selection logic will be output along with each cascaded logic.

[0067] In addition, in the specific implementation, each level of selection logic can also include timing logic, so that timing logic can be added in the middle of the selection signal output.

[0068] Taking one master device and six slave devices as an example, an exemplary implementation structure of an Advanced Extensible Interface (AXI) bus matrix is ​​as follows: Figure 9 As shown.

[0069] In a practical implementation, the decoding logic can be the address decoding logic.

[0070] Deadlock prevention logic can be multiple sets of CDAS (Cyclic Dependency Avoidance Schemes) deadlock prevention logic and / or SAS (Single Active Slave) logic (i.e., write operation deadlock prevention logic).

[0071] The SAS (Single Active Slave) logic (i.e., write operation deadlock prevention logic) is implemented using the Advanced Extensible Interface (AXI) bus deadlock prevention method provided in this embodiment. In other words, the AXI bus deadlock prevention method provided in this embodiment is implemented through the first-level selection logic of the AXI bus matrix, such as... Figure 10 As shown, Figure 10 Other channels include the read address channel (AR).

[0072] For example, the first-level selection logic of the Advanced Scalable Interface Bus Matrix simultaneously receives the first command sent by the master device through the write address channel (AW) and the first data sent by the master device through the write data channel (W) in step 401.

[0073] When a first command is received via 402, it is sent to the slave device. Simultaneously, the received first command is stored in the write address channel buffer, and the write address channel (AW) is backpressured. When sending the received first command to the slave device, if the slave device is a slave device that directly outputs through the first-level selection logic (e.g., ...), ... Figure 9 If the slave device is not a slave device that is directly output through the first-level selection logic (such as slave device 0), then the first command received will be sent to slave device 0; if the slave device is not a slave device that is directly output through the first-level selection logic (such as slave device 0), then the first command received will be sent to slave device 0; Figure 9If the slave device is 1, 2, 3, 4, or 5, then the first command received is sent to the slave device through the lower-level selection logic (if the slave device is slave device 2, then the first command received is sent to slave device 2 through the second-level selection logic).

[0074] The received first data is sent to the slave device in step 403. When sending the received first data to the slave device, if the slave device is a slave device that directly outputs through the first-level selection logic (e.g., ...), ... Figure 9 If the slave device is not a slave device that is directly output through the first-level selection logic (such as slave device 0), then the received first data will be sent to slave device 0; if the slave device is not a slave device that is directly output through the first-level selection logic (such as slave device 0), then the received first data will be sent to slave device 0; Figure 9 If the slave device is 1, 2, 3, 4, or 5, then the first data received is sent to the slave device through the lower-level selection logic (if the slave device is slave device 5, then the first data received is sent to slave device 5 through the second-level selection logic and the third-level selection logic).

[0075] Furthermore, in practical implementation, during the connection process between the Advanced Extensible Interface (AXI) bus matrix provided in this embodiment and the master and slave devices, if one device malfunctions (e.g., freezes), the AXI bus will be unable to respond, causing it to be hampered and hang. To prevent this, when the first-level selection logic is connected to the master device, it can be connected through the master execution module; when the last-level selection logic is connected to the slave device, it can be connected through the slave execution module, as shown below. Figure 11 As shown.

[0076] The main execution module is used to monitor the main device and take over the main device when it malfunctions.

[0077] The execution module is used to monitor the slave device and take over the slave device when it malfunctions.

[0078] 1. Main Execution Module The main execution module is connected between the master device and the Advanced Extensible Interface (AXI) bus matrix to monitor the master device and take over the master device in case of failure.

[0079] like Figure 12 As shown, the main execution module includes: a main state machine (such as...) Figure 12 In the FSM), the master synchronization module (such as Figure 12 Sync in the middle), interception module (such as Figure 12 (mst_wintercept in the middle).

[0080] Among them, the main synchronization module and the interception module establish a path.

[0081] The master state machine establishes a communication channel with the interception module, and at the same time, the interception module establishes a communication channel with the master device.

[0082] The master state machine also establishes a path with the advanced scalable interface bus matrix, and at the same time, the master state machine establishes a path with the master device.

[0083] 1) Master Synchronization Module The master synchronization module is used to synchronize the master takeover enable signal of the master device when the master device is malfunctioning.

[0084] In other words, when the master device is functioning normally, the master synchronization module will not receive the master takeover enable signal, such as... Figure 12 As shown, at this time, the master state machine only performs data pass-through and does not perform any processing.

[0085] If the master device is functioning normally, when the master device needs to read data, it initiates a read command (including the read address, the length of the data to be read, etc.). This read command enters the master state machine (e.g., ...). Figure 12 In the FSM), at the same time, the master state machine (such as FSM) Figure 12 The read command is transmitted transparently through the FSM (Front State Machine) and sent to the slave device via the read address channel (AR). The read data (read by the slave device based on the read command) and response information (response information from the slave device executing the read command) returned by the read data channel (R) also enter the master state machine (e.g., ...). Figure 12 In the FSM), at the same time, the master state machine (such as FSM) Figure 12 The FSM in the middle transmits it to the master device.

[0086] If the master device is functioning normally, when the master device needs to write data, it initiates a write command (including the address to be written, the length of the data to be written, etc.). This write command enters the master state machine (e.g., ...). Figure 12 In the FSM), at the same time, the master state machine (such as FSM) Figure 12 The write command is transmitted transparently to the master state machine (FSM) and sent to the slave device via the write address channel (AW); in addition, the written data will also enter the master state machine (e.g., FSM). Figure 12 In the FSM), at the same time, the master state machine (such as FSM) Figure 12 The write command is transparently transmitted through the FSM (Followed by the master state machine) and transmitted to the slave device via the write data channel (W). The response information returned by the write response channel (B) (which is the response information of the slave device executing the write command) will also enter the master state machine (e.g., ...). Figure 12 In the FSM), at the same time, the master state machine (such as FSM) Figure 12 The FSM in the middle transmits it to the master device.

[0087] If the main device malfunctions (e.g., the main device freezes), a main takeover enable signal will be sent. Figure 13 In the AXI_ISO_EN signal, the master synchronization module receives the master takeover enable signal (i.e., AXI_ISO_EN) and synchronizes it to the master state machine. Figure 13 The synchronization of the master control enable signal between the master synchronization module and the master state machine is shown.

[0088] 2) Master state machine The master state machine stores the data transmission length of the first data sent through the write data channel. After synchronizing with the master takeover enable signal, it initiates master device takeover based on the data transmission length. Master device takeover stops after the master takeover enable signal is released and the stop condition is met.

[0089] The stopping condition is that the transmission processing within the current module is completed.

[0090] For example, when the master equipment is functioning normally, the master synchronization module will not receive the master takeover enable signal, such as Figure 12 As shown, at this time, the main state machine only performs data pass-through. In this case, when passing through a read command, no processing is performed except for pass-through. However, when passing through a write command, in addition to pass-through, the data transmission length of the first data sent through the write data channel (W) is also stored.

[0091] It should be noted that the write command ID is not recorded here. This is because AXI 4 and later protocols have the following requirements for write data: the transmission of write data channels (W) must be strictly in address order, i.e., the write data channel (W) must maintain order. In other words, write data must be transmitted in address order; data from a later write command cannot arrive at the slave device before the write command itself. Based on this requirement, it is not necessary to record that the first data sent by the write data channel (W) corresponds to the current write command. Therefore, the write command corresponding to the data can be determined without recording the write command ID.

[0092] When the master state machine synchronizes to the master takeover enable signal, it indicates that the master device has malfunctioned and can no longer send commands and / or data. At this time, the master state machine will initiate master takeover based on the data transmission length, taking over the response to the Advanced Extensible Interface (AXI) bus matrix. During this period, the master device can perform repair operations such as restarting. Once the master device returns to normal and the transmission processing within the current module is complete, it will stop sending the master takeover enable signal. At this point, the master synchronization module will no longer receive the master takeover enable signal (i.e., from...). Figure 13 The image shows the restoration to... Figure 12As shown), the master state machine cannot synchronize with the master takeover enable signal, and thus the master state machine receives the release of the master takeover enable signal. After the master takeover enable signal is released and the transmission processing within the current module is completed, the master state machine stops taking over the master device and resumes the transparent transmission of data from the master device. In this case, when transparently transmitting a read command, no processing is performed except for the transparent transmission. However, when transparently transmitting a write command, in addition to the transparent transmission, the data transmission length of the first data sent through the write data channel (W) is also stored.

[0093] After the master state machine takes over the master device, for read commands, the master device mainly receives the read data returned by the read data channel (R). Therefore, the master state machine can continue to receive the read data returned by the read data channel (R). For write commands, the master device needs to continue sending write data and does not need to maintain the transmission of the write response channel (B). Therefore, the ready signal of the write response channel (B) can be continuously pulled high. For the write data, the master state machine is used to obtain the target transmission length after synchronizing with the master takeover enable signal. If the data transmission length is different from the target transmission length, the data continues to be transmitted through the write data channel (W). For example, the master state machine obtains the length of the write data in the current write command, which is the target transmission length. According to the requirements of AXI 4 and subsequent protocols, the data transmission length of the first data sent through the write data channel (W) is the actual data length sent to the slave device by the current write command. If the data transmission length is the same as the target transmission length, it means that the write data corresponding to the write command has been sent. The master state machine does not need to continue sending and only needs to receive the response information returned by the write response channel (B). If the data transmission length is different from the target transmission length (because the transmission ends when the data is sent to the target transmission length, this situation must be that the data transmission length is less than the target transmission length), it means that the data has not been completely transmitted. In this case, the master state machine will continue to transmit data through the write data channel (W).

[0094] 3) Interception module (such as...) Figure 12 (mst_wintercept) The interception module is used to intercept the first data sent by the write data channel after the master device takes over, before the address channel handshake is completed.

[0095] This is because the AXI protocol supports out-of-order delivery, under which commands and data are not transmitted sequentially; data may be transmitted before commands. In such cases, the interception module will intercept the first data sent by the write data channel (W) before the address channel handshake is completed, such as by pulling wready low. Figure 13 As shown.

[0096] In actual execution, when the master device is functioning normally, the main execution module transparently transmits information sent by the master device (such as commands, data, etc.) and / or information received by the master device (such as data, responses, etc.). When the master device malfunctions, the main execution module takes over the master device, transmitting information (such as commands, data, etc.) and / or receiving information (such as data, responses, etc.) on behalf of the master device, maintaining the interaction between the master device and the Advanced Extensible Interface (AXI) bus matrix, and preventing the AXI bus from being affected and crashing due to the master device malfunction.

[0097] In addition, the main execution module can also be configured through configuration files, configuration interfaces, etc., such as Figure 14 The cfg_interface shown.

[0098] Furthermore, the process of the main execution module taking over and protecting the main device can be as follows: 501, stores the data transmission length of the first data sent through the write data channel (W).

[0099] For example, the master state machine stores the data transmission length of the first data sent through the write data channel (W).

[0100] 502, after synchronizing with the master takeover enable signal when the master device malfunctions, the master device takeover is initiated based on the data transmission length.

[0101] When the master device takes over based on the data transmission length, it can intercept the first data sent by the write data channel (W) before the address channel handshake is completed. At the same time, it can obtain the target transmission length. If the data transmission length is different from the target transmission length, it can continue to transmit data through the write data channel (W).

[0102] If the master state machine synchronizes with the master device's takeover enable signal when the master device malfunctions via the master synchronization module, the master state machine initiates takeover of the master device based on the data transmission length. Specifically, this includes: the interception module intercepting the first data sent via the write data channel (W) before the address channel handshake is completed; simultaneously, the master state machine obtains the target transmission length; if the data transmission length differs from the target transmission length, data transmission continues through the write data channel (W).

[0103] 503. After the main control enable signal is released and the stop condition is met, the main equipment control is stopped.

[0104] If the master state machine determines through the master synchronization module that the master takeover enable signal has been released and the stop condition is met, the master state machine will stop the takeover of the master device.

[0105] After receiving the master takeover enable signal, the main execution module disconnects the path between the malfunctioning master device and the Advanced Extensible Interface (AXI) bus matrix on the one hand, and maintains the transmission between the master device and the AXI bus matrix on the other hand. Thus, after the master device malfunctions, the operation of the AXI bus is not affected, thereby allowing time for the recovery of the malfunctioning master device.

[0106] In addition, since the main execution module stores the data transmission length of the first data sent by the write data channel (W) when the master device is normal, the main execution module also has a monitoring function. It can monitor the transmission status between the master device and the Advanced Extensible Interface (AXI) bus matrix throughout the process. If a transmission abnormality is detected based on the data transmission length (such as the data transmission length not changing for a long time), an interrupt can be issued to provide an early warning.

[0107] 2. From the execution module The execution module is attached between the slave device and the Advanced Extensible Interface (AXI) bus matrix to monitor the slave device and take over the slave device in case of failure.

[0108] like Figure 15 As shown, the execution module includes: a write data buffer (such as...) Figure 15 bid_buf in the middle), read data buffer (such as...) Figure 15 (rid_buf in the context of writing commands to a first-in-first-out queue, such as...) Figure 15 wr_fifo in the state machine (e.g., wr_fifo) Figure 15 In the FSM), from the synchronization module (such as ...) Figure 15 (Sync in the middle).

[0109] Among them, the write data buffer, read data buffer, and write command first-in-first-out queue are connected to the Advanced Extensible Interface (AXI) bus matrix, and the write data buffer, read data buffer, and write command first-in-first-out queue are also connected to the slave state machine.

[0110] Establish a path between the synchronization module and the slave state machine.

[0111] The state machine also establishes a path with the Advanced Extensible Interface (AXI) bus matrix, and simultaneously establishes a path with the slave device.

[0112] 1) From the synchronization module The synchronization module is used to synchronize the slave device's slave takeover enable signal when the slave device malfunctions.

[0113] In other words, when the device is functioning normally, the synchronization module will not receive a slave takeover enable signal, such as... Figure 15 As shown, at this time, the state machine only transmits data without performing any processing.

[0114] If the device is functioning correctly, for a read request, the read command transmitted via the read address channel (AR) (including the read address, the length of the data to be read, etc.) enters the slave state machine (e.g., ...). Figure 15 In the FSM), at the same time, from the state machine (such as Figure 15 The FSM in the system transmits the read command to the slave device. After reading the data and receiving the response information based on the read command, the slave device sends the read data and response information to the slave state machine (e.g., FSM). Figure 15 In the FSM), from the state machine (such as ...) Figure 15 The FSM in the data is transmitted to the master device via the read data channel (R).

[0115] If the device is functioning normally, for write requests, the write command transmitted via the write address channel (AW) (i.e., the first command, which includes the address to be written, the length of the data to be written, etc.) enters the slave state machine (e.g., ...). Figure 15 In the FSM), at the same time, from the state machine (such as Figure 15 The write command is transparently transmitted to the slave device via the FSM (Folded Streaming Machine). The data being written, transmitted via the write data channel (W), also enters the slave state machine (e.g., FSM). Figure 15 In the FSM), at the same time, from the state machine (such as Figure 15 The FSM in the process transmits the written data transparently to the slave device. The slave device writes the data based on the write command, receives a response, and then sends the response to the slave state machine (e.g., FSM). Figure 15 In the FSM), from the state machine (such as ...) Figure 15 The FSM in the process is transmitted to the master device via the write response channel (B).

[0116] If a device malfunctions (such as becoming stuck), a slave controller enable signal will be sent, such as... Figure 16 In the AXI_ISO_EN signal, the synchronization module receives the slave takeover enable signal (i.e., AXI_ISO_EN) and synchronizes it to the slave state machine so that the slave state machine can take over the slave device.

[0117] 2) Write data buffer The write data buffer is used to cache write command response data and handle the transmission of write response channels.

[0118] The write command response data includes at least the first ID of the write command in the response.

[0119] It should be noted that the response data here is not response information.

[0120] The response message is what the AXI protocol requires the slave device to send back to the master device after executing a write command. In the AXI protocol, after executing a write command, the slave device sends a response message to the master device via the write response channel (B), which is carried by the BRESP[1:0] signals. The AXI protocol defines four response types: OKAY: This indicates that the access was successful.

[0121] EXOKAY: Indicates successful exclusive access.

[0122] SLVERR: Indicates a device error.

[0123] DECERR: Indicates an interconnect decoding error (usually caused by interconnect components).

[0124] The response data is generated by the execution module and includes the first ID of the write command in the response. The response data does not need to be fed back to the master device; it is only used as auxiliary information after the execution module takes over the slave device, assisting the slave module in its takeover process.

[0125] For example, when the device is functioning normally, the slave synchronization module will not receive the slave takeover enable signal, such as... Figure 15 As shown, at this time, the slave state machine only performs data pass-through. If the slave device executes a write command (such as write command 1, whose ID is ID1) and then receives the response data (such as response data 1), the write data buffer will cache the first ID of the response write command (such as cache ID1), and at the same time, the slave state machine will transmit the response data 1 to the master device through the write response channel (B).

[0126] In addition, when a device malfunctions, the write data buffer will take over the transmission of the write response channel from the slave device.

[0127] 3) Read data buffer The read data buffer is used to cache the third ID of the read command transmitted through the read address channel and the target read length corresponding to the read command, cache the read command response data, and process the transmission of the read data channel.

[0128] The read command response data includes at least: the second ID of the responding read command and the data read length corresponding to the read command.

[0129] It should be noted that the response data here is not the same as the response information.

[0130] The response message is what the AXI protocol requires the slave device to send back to the master device after executing a read command. In the AXI protocol, after executing a read command, the slave device sends a response message to the master device via the read data channel (R). This response message is carried by the RRESP[1:0] signal and is returned synchronously with the read data. The AXI protocol defines four response types: OKAY: This indicates that the access was successful (default response).

[0131] EXOKAY: Indicates successful exclusive access (e.g., atomic operation).

[0132] SLVERR: Indicates a device error (such as an illegal address or misaligned access).

[0133] DECERR: Address decoding error (no target slave device).

[0134] The response data is generated by the execution module. It includes the second ID of the read command and the data length corresponding to that read command. This response data does not need to be sent back to the master device; it is only used as auxiliary information after the execution module takes over the slave device, assisting in the takeover process.

[0135] For example, when the device is functioning normally, the slave synchronization module will not receive the slave takeover enable signal, such as... Figure 15 As shown, at this point, the state machine only performs data pass-through. If the read address channel (AR) transmits a read command (such as read command 2, whose ID is ID2, and read command 2 includes read address 2, read data length 2, etc.), then the read data buffer will cache the third ID (i.e., cache ID2) of the read command transmitted by the address channel (AR). Simultaneously, the state machine (such as...) Figure 15 The FSM in the read state machine (FSM) transmits read command 2 to the slave device. After the slave device reads data based on read command 2 and receives the response information, the read data buffer caches the third ID (e.g., ID2) of the read command transmitted through the read address channel (AR) and the target read length (e.g., length 2) corresponding to the read command, and caches the read command response data (e.g., the second ID of the responding read command and the data read length corresponding to the read command). At the same time, the slave state machine sends the read data and response information to the slave state machine (e.g., ...). Figure 15 In the FSM), from the state machine (such as ...) Figure 15 The FSM in the data is transmitted to the master device via the read data channel (R).

[0136] Additionally, in the event of a device malfunction, the read data buffer will take over the transmission of the read data channel (R) from the slave device.

[0137] 4) Write commands for the first-in, first-out queue. The write command first-in-first-out queue is used to store the fourth ID of the write command (i.e., the first command) transmitted through the write address channel.

[0138] For example, when the device is functioning normally, the slave synchronization module will not receive the slave takeover enable signal, such as... Figure 15 As shown, at this time, the state machine only performs data pass-through. If the write address channel (AW) transmits a write command (such as write command 1, whose ID is ID1, and write command 1 includes the address to be written 1, the length of the data to be written 1, etc.), then the write command first-in-first-out queue will store the fourth ID of the write command transmitted by the write address channel (AW) (i.e., cache ID1).

[0139] In other words, AXI bus-related information will be processed as follows: (1) Read transaction The ID (as the third ID) and the length to be read (as the target read length) of each read command transmitted via the read address channel (AR) are stored in the read data buffer.

[0140] The ID of the read command (as the second ID) and the length read (as the data read length) involved in executing each read command from the device are also stored in the read data buffer.

[0141] In this way, by using the read data buffer, we can know which read commands the slave device received through the third ID, and the target read length can indicate how much data each read command requires to be read. Similarly, by using the second ID, we can know which read commands the slave device executed, and by using the data read length, we can determine how much data each executed read command actually read.

[0142] (2) Write the transaction The ID of each write command transmitted via the write address channel (AW) (as the fourth ID) is stored in the write command first-in-first-out queue.

[0143] The ID of each write command involved in executing a write command from the device (as the first ID) is stored in the write data buffer.

[0144] Thus, the fourth ID of the write command FIFO queue indicates which write commands the slave device has received. The first ID of the write data buffer indicates which write commands the slave device has executed.

[0145] Furthermore, the ID of the write command transmitted through the write address channel (AW) (i.e., the fourth ID) is implemented using a first-in, first-out (FIFO) queue, while other data is stored using a buffer. This is because AXI 4 and subsequent protocols have the following requirements for write data: the transmission of write data through the write data channel (W) must be strictly in address order, i.e., the write data channel (W) must maintain order. Since FIFO also maintains order, the ID of the write command transmitted through the write address channel (AW) (i.e., the fourth ID) is stored using a first-in, first-out queue. Other channels support out-of-order mechanisms, under which commands and data are not transmitted in sequence, and therefore are stored using buffers.

[0146] 5) From the state machine The state machine is used to receive write command response data and / or read command response data from the slave device.

[0147] The write command response data includes at least the first ID of the write command in the response.

[0148] The read command response data includes at least: the second ID of the read command and the data length to be read for the corresponding read command.

[0149] For example, when the device is functioning normally, the slave synchronization module will not receive the slave takeover enable signal, such as... Figure 15 As shown, at this time, the state machine only performs data pass-through. In this case, when the slave device returns the read data after executing the read command, the slave state machine will obtain the ID of the read command corresponding to the read data (i.e., the second ID) and the length of the read data (i.e., the data read length) while passing through the read data. Subsequently, the second ID and the data read length will be stored in the read data buffer.

[0150] When the slave device sends back a response after executing a write command, the slave state machine will obtain the ID of the write command corresponding to the response (i.e., the first ID) while transmitting the response information. Subsequently, the first ID will be stored in the write data buffer.

[0151] When the slave state machine synchronizes to the slave takeover enable signal, it indicates that the slave device has malfunctioned and can no longer receive commands and / or data, as well as feedback data and / or response information. At this time, the slave state machine, based on the read data buffer and / or write data buffer, and the write command FIFO queue, initiates takeover of the slave device, continuing to respond to the AXI bus in place of the slave device. During this period, the slave device can perform repair operations such as restarting. Once the slave device returns to normal and the transmission processing within the current module is completed, it will stop sending the slave takeover enable signal. At this point, the slave synchronization module will no longer receive the slave takeover enable signal (i.e., from the slave device). Figure 16 The image shows the restoration to... Figure 15As shown in the diagram, the slave state machine will also be unable to synchronize with the slave takeover enable signal, and the slave state machine will receive the release of the slave takeover enable signal. After the slave takeover enable signal is released and the stop condition is met, the slave state machine will stop taking over the slave device and resume the transparent transmission of data from the slave device.

[0152] The stopping condition is that the transmission processing within the current module is completed.

[0153] In other words, the state machine is also used to initiate slave device takeover based on the read data buffer and / or write data buffer, and the write command FIFO queue, after synchronizing with the slave takeover enable signal. After the slave takeover enable signal is released, the takeover does not immediately terminate; instead, it terminates after the transmission processing within the current module is completed.

[0154] To avoid being unable to exit takeover for an extended period, after the takeover enable signal is released, the device will no longer accept handshake signals for the address channel, and will only process the data channel. Once the transmission processing within the current module is complete, the takeover of the slave device will cease.

[0155] (1) Read transaction After the slave device is taken over from the state machine, the read data buffer will take over the slave device to process read commands transmitted through the read address channel (AR). That is, the read data buffer receives read commands transmitted through the read address channel (AR).

[0156] The slave state machine takes over from the slave device and responds to read commands. That is, after synchronizing with the slave takeover enable signal (i.e., after the slave state machine takes over the slave device), it retrieves all the second IDs, third IDs, data read lengths, and target read lengths from the read data buffer. If a second takeover ID exists, it generates a second response message for that second takeover ID. Here, the second takeover ID is the third ID, but not the second ID. Alternatively, the second takeover ID is the second ID, but its corresponding data read length is different from the target read length.

[0157] The read data buffer stores the IDs of all read commands (i.e., the third ID) transmitted by the read address channel (AR) and the lengths of the data to be read by each read command (i.e., the target read length). It also stores the IDs of all read commands that the slave device has executed (i.e., the second ID, which can be obtained from the read command response data) and the lengths of the data that the slave device has read based on each read command (i.e., the data read length, which can be obtained from the read command response data). If the slave device executes normally, it will execute the read commands transmitted by the read address channel (AR) (at this time, the ID of this read command will be stored as the third ID in the read data buffer when transmitted from the read address channel, and will be stored as the second ID in the read data buffer after the read command is executed). And when executing, it will read according to the target read length of the read command (at this time, the length of the data that this read command needs to read will be stored as the target read length in the read data buffer, and the actual length of the data read after the read command is executed will be stored as the data read length in the read data buffer). Therefore, normally, the third ID and the second ID are the same (i.e., each read command is executed), and the data read length and the target read length are also the same (i.e., each read command reads as required). When the slave device is abnormal, the slave state machine can know which read commands have been executed by the slave device and which have not been executed by comparing the second ID and the third ID. For the executed read commands, the slave state machine can know which read commands have been normally executed by the slave device and which have not been executed by comparing the data read length and the target read length. Therefore, after the slave state machine takes over the slave device, it obtains all the second IDs (such as ID3, ID4, ID5), third IDs (such as ID3, ID4), data read lengths (such as the data read length corresponding to ID3 is 3, the data read length corresponding to ID4 is 4, and the data read length corresponding to ID5 is 5), and target read lengths (such as the target read length corresponding to ID3 is 3, the target read length corresponding to ID4 is 4) in the read data buffer. Among them, the data read length 3 = the target read length 3, and the data read length 4 < the target read length 4 corresponding to ID3. Because ID5 is only the second ID and not the third ID, therefore, although the read command corresponding to ID5 is received by the slave device, the slave device has not executed it. Also because it has not been executed, there is no data read length for it. At this time, ID5 is determined as the second takeover ID (i.e., the ID of the read command that needs to be processed by the slave state machine after taking over). Because ID4 is both the second ID and the third ID, but the data read length 4 < the target read length 4, it means that although the read command corresponding to ID4 is executed by the slave device, it has not been executed completely (i.e., the amount of data read does not reach the amount of data indicated by this read command). At this time, ID4 is determined as the second takeover ID (i.e., the ID of the read command that needs to be processed by the slave state machine after taking over).Since ID3 is both the second and third ID, and the data read length 3 = the target read length 3, it means that the read command corresponding to ID3 has been executed by the slave device and has been completed (i.e., the amount of data read has reached the amount of data indicated by the read command). At this time, ID3 is not determined as the second takeover ID, and the slave state machine does not process ID3.

[0158] For the second takeover ID (such as ID4, ID5), the state machine generates the second response information 4 for the read command corresponding to ID4 and the second response information 5 for the read command corresponding to ID5.

[0159] The read data buffer is used to return the second response information through the read data channel (R), that is, the read data buffer returns the second response information 4 and the second response information 5 through the read data channel (R).

[0160] Through the above process, the state machine completes the takeover of read transactions from the slave device.

[0161] (2) Write the transaction After the state machine takes over the slave device, for write commands transmitted through the write address channel (AW), the write data buffer will take over the transmission of the write data buffer from the slave device, that is, the write data buffer receives write commands transmitted through the write address channel (AW).

[0162] The slave state machine takes over from the slave device and responds to write commands. That is, after synchronizing with the slave takeover enable signal (i.e., after the slave state machine takes over the slave device), it retrieves all first IDs (which can be obtained from the write command response data) in the write data buffer and all fourth IDs in the write command FIFO queue. If a first takeover ID exists, it generates a first response message for that first takeover ID. The first takeover ID is the fourth ID, but not the first ID.

[0163] The write command FIFO queue stores the IDs (i.e., the fourth ID) of all write commands transmitted via the write address channel (AW). The write data buffer stores the IDs (i.e., the first ID) of all write commands executed by the slave device. If the slave device executes normally, it will execute the write commands transmitted via the write address channel (AW). (At this time, the ID of the write command, which was stored as the fourth ID in the write command FIFO queue when it was transmitted from the write address channel (AW), and then stored as the fourth ID in the write data buffer after the write command is executed.) Therefore, normally the fourth ID and the first ID are the same (i.e., every write command is executed). It should be noted here that the execution module does not record the data writing status of each write command. This is because, according to the ordering requirements of AXI 4 and subsequent protocols, the transmission of write data channels (W) must be strictly in address order. That is to say, the data writing of the next write command will only be executed after all the data of the previous write command has been written. If the currently executed write command changes, it means that the previous write command has not been completed. If the currently executed write command does not change, it means that it has not been completed. Therefore, there is no need to record the execution status of the write commands.

[0164] When a slave device malfunctions, the slave state machine can determine which write commands have been executed and which have not by comparing the fourth ID with the first ID. It can also determine whether the last write command was successfully executed. Therefore, after taking over the slave device, the slave state machine retrieves all the fourth IDs (e.g., ID6, ID7, ID8) from the write command FIFO queue and all the first IDs (e.g., ID6, ID7) from the write data buffer. Based on ID6 and ID7 in the write data buffer, it knows that the write commands corresponding to ID6 and ID7 have been processed. ID8 is the first takeover ID. At this point, the slave state machine takes over the slave device to respond to the write command corresponding to ID8, generating the first response information 8 for ID8, thus completing the response information for any unresponsive write commands.

[0165] The write data buffer is used to return the first response information through the write response channel (B), that is, the write data buffer returns the first response information 8 through the write response channel (B).

[0166] Through the above process, the state machine completes the takeover of write transactions from the slave device.

[0167] In practice, when the slave device is functioning normally, the execution module transparently transmits information (such as data and responses) sent by the slave device to the AXI bus and information (such as commands and data) received by the slave device from the AXI bus. When the slave device malfunctions, the execution module takes over, sending information (such as data and responses) to the AXI bus and / or receiving information (such as commands and data) from the AXI bus on behalf of the slave device, maintaining interaction between the slave device and the AXI bus and preventing the AXI bus from being affected and crashing due to the slave device malfunction.

[0168] In the specific implementation, when the execution module processes write transactions and read transactions, it processes them in the order that the priority of write transactions is greater than that of read transactions. For example, for read data channels (R) and write data channels (W), only one channel is processed at a time (write data channel (W) is processed first). The other channel will only be processed after the transmission response of the current channel is completed.

[0169] In addition, the execution module can be configured in other ways, such as through configuration files, configuration interfaces, etc. Figure 17 The cfg_interface shown.

[0170] Furthermore, the process of the execution module taking over the protection of the slave device can be as follows: 601, caches the third ID of the read command transmitted via the read address channel (AR) and the target read length corresponding to that read command. Stores the fourth ID of the write command transmitted via the write address channel (AW).

[0171] For example, the read data buffer caches the third ID of the read command transmitted via the read address channel (AR) and the target read length corresponding to that read command. The write command first-in-first-out queue stores the fourth ID of the write command transmitted via the write address channel (AW).

[0172] 602, Receive write command response data and / or read command response data from the slave device.

[0173] The write command response data includes at least the first ID of the responding write command. The read command response data includes at least the second ID of the responding read command and the data length to be read for that read command.

[0174] For example, a write data buffer receives and stores write command response data from the device and / or a read data buffer receives and stores read command response data.

[0175] 603, after synchronizing to the slave takeover enable signal when the slave device malfunctions, the slave device takeover is enabled based on the third ID, target read length, read command response data and / or the fourth ID, write command response data.

[0176] If the slave state machine synchronizes with the slave device's takeover enable signal (in case of a slave device malfunction) via the synchronization module, the slave state machine initiates takeover of the slave device based on the third ID, target read length, read command response data and / or the fourth ID, and write command response data. Specifically, this includes: retrieving all first IDs from the write command response data. If a first takeover ID exists, a first response message for that first takeover ID is generated. The first response message is returned via the write response channel (B). Here, the first takeover ID is the fourth ID, but not the first ID.

[0177] And / or, obtain all second IDs and corresponding target read lengths from the read command response data in the state machine. If a second takeover ID exists, generate second response information for that second takeover ID. Return the second response information through the read data channel (R). Here, the second takeover ID is a third ID, but not a second ID. Alternatively, the second takeover ID is a second ID, but its corresponding data read length is different from the target read length.

[0178] 604. Stop taking over the device after the takeover enable signal is released and the stop condition is met.

[0179] The stopping condition is that the transmission processing within the current module is completed.

[0180] If the state machine determines through the synchronization module that the takeover enable signal has been released and the transmission processing within the current module is completed, the state machine stops taking over the device.

[0181] After receiving the takeover enable signal from the execution module, it disconnects the path between the faulty slave device and the Advanced Extensible Interface (AXI) bus matrix on the one hand, and maintains the transmission between the slave device and the AXI bus matrix on the other hand. Thus, after the slave device fails, the operation of the AXI bus is not affected, thereby allowing time for the faulty slave device to recover.

[0182] In addition, since the execution module caches the ID of the read command transmitted through the read address channel (AR) and the target read length corresponding to the read command, the read command response data, the transmission of the read data channel (R), the write command response data, and the ID of the write command transmitted through the write address channel (AW) when the slave device is normal, the execution module also has a monitoring function. It can monitor the transmission status between the slave device and the Advanced Extensible Interface (AXI) bus matrix throughout the process. If a transmission abnormality is detected based on the cached and stored data, an interrupt can be issued to provide an early warning.

[0183] The master execution module can take over the master device after a failure (such as a freeze), ensuring the normal operation of the AXI bus during the master device reset process. Similarly, the slave execution module can take over the slave device after a failure (such as a freeze), ensuring the normal operation of the AXI bus during the slave device reset process. The master and slave execution modules together implement AXI bus isolation, monitoring already-handshaked transmissions before the master and / or slave devices reset. Upon reset, they act as proxies for the master and / or slave devices to respond to these transmissions and process subsequent transmissions, preventing bus hangs.

[0184] It should be noted that the data in each channel flows in one direction only. For example, the read address channel (AR) flows from the master device to the slave device, the read data channel (R) flows from the slave device to the master device, the write address channel (AW) flows from the master device to the slave device, the write data channel (W) flows from the master device to the slave device, and the write response channel (B) flows from the slave device to the master device. Figure 1 , Figure 3 , Figures 6 to 11 The arrows in the connecting lines are all unidirectional, flowing from the master device to the slave device. This is an example of one or more channels flowing from the master device to the slave device. Figures 12 to 17 It does not restrict channels, so some channels flow from the master device to the slave device, and some channels flow from the slave device to the master device. Figures 12 to 17 The arrows in the text are double-headed.

[0185] The Advanced Extensible Interface (AXI) bus deadlock prevention method provided in this embodiment can implement SAS (Single Active Slave) logic (i.e., write operation deadlock prevention logic).

[0186] The Advanced Extensible Interface (AXI) bus deadlock prevention method provided in this embodiment can deliver a faster transmission channel with less logic overhead.

[0187] The Advanced Scalable Interface (AXI) bus anti-deadlock method provided in this embodiment ensures that the first data (i.e., the first data) of the write address channel (AW) and the write data channel (W) are sent simultaneously without back pressure, while meeting the SAS write operation anti-deadlock mechanism.

[0188] This embodiment provides a deadlock prevention method for an Advanced Scalable Interface (ASPI) bus. The ASPI bus's write address channel incorporates a write address channel buffer. The method includes: simultaneously receiving a first command sent by the master device via the write address channel and first data sent by the master device via the write data channel; upon receiving a first command, sending the received first command to the slave device and storing the received first command in the write address channel buffer, while simultaneously applying back pressure to the write address channel; sending the received first data to the slave device; when the WLAST signal is high, releasing the back pressure on the write address channel, and repeating the steps of sending the received first command to the slave device, storing the received first command in the write address channel buffer, and applying back pressure to the write address channel, and subsequent steps. This method achieves deadlock prevention through a single write address channel buffer and avoids cavitation.

[0189] Based on the same inventive concept of the Advanced Scalable Interface Bus (ASPA) anti-deadlock method, this embodiment provides an electronic device that includes an ASPA matrix.

[0190] Among them, the advanced scalable interface bus matrix can be as follows: Figure 10 As shown, this advanced scalable interface bus matrix performs... Figure 4 The advanced scalable interface bus deadlock prevention method is shown.

[0191] Specifically, the write address channel of the Advanced Extensible Interface Bus introduces a write address channel cache.

[0192] The advanced scalable interface bus deadlock prevention method includes: Simultaneously receive the first command sent by the master device through the write address channel and the first data sent by the master device through the write data channel.

[0193] When a first command is received, the received first command is sent to the slave device. At the same time, the received first command is stored in the write address channel buffer, and the write address channel is pressured back.

[0194] The first received data is sent to the slave device.

[0195] When the WLAST signal is high, the reverse pressure of the write address channel is released, and the process of sending the received first command to the slave device and storing the received first command in the write address channel buffer is repeated. At the same time, the write address channel is reverse-pressurized, and subsequent steps are repeated.

[0196] The write data channel of the Advanced Scalable Interface Bus introduces one flag bit.

[0197] The initial value of the flag is the first value.

[0198] When a first command is received, the flag is updated to the second value.

[0199] The first received data is sent to the slave device, including: When the flag is at the second value, the received first data is sent to the slave device.

[0200] When the WLAST signal is high, the reverse voltage of the write address channel is released, including: When the WLAST signal is high, update the flag bit to the first value.

[0201] When the flag is at its first value, the back pressure on the write address channel is released.

[0202] This method is implemented through the first-level selection logic of the high-level extensible interface bus matrix.

[0203] The advanced scalable interface bus matrix includes multi-level selection logic.

[0204] The first-level selection logic is connected to the master device.

[0205] The final selection logic is connected to the slave device.

[0206] The first-level selection logic also includes deadlock prevention logic. The number of levels in the multi-level selection logic is determined according to the floorplan.

[0207] Among them, the upper-level selection logic outputs a selection signal to the lower-level selection logic.

[0208] The selection logic in the register also includes a timing logic.

[0209] The first command received is sent to the slave device, including: The first command received is sent to the slave device through the lower-level selection logic.

[0210] The first received data is sent to the slave device, including: The first received data is sent to the slave device through the lower-level selection logic.

[0211] The first-level selection logic is connected to the main device through the main execution module.

[0212] The final selection logic is connected to the slave device through the execution module.

[0213] The main execution module is used to monitor the main device and take over the main device when it malfunctions.

[0214] The execution module is used to monitor the slave device and take over the slave device when it malfunctions.

[0215] The execution module includes: a write data buffer, a read data buffer, a write command first-in-first-out queue, a slave state machine, and a slave synchronization module.

[0216] Among them, the write data buffer, read data buffer, and write command first-in-first-out queue are connected to the advanced extensible interface bus matrix, and the write data buffer, read data buffer, and write command first-in-first-out queue are also connected to the slave state machine.

[0217] Establish a path between the synchronization module and the slave state machine.

[0218] The state machine also establishes a path with the advanced scalable interface bus matrix, and at the same time, it establishes a path with the slave device.

[0219] The slave state machine is used to receive write command response data and / or read command response data from the slave device. The write command response data includes at least: a first identifier ID of the responding write command. The read command response data includes at least: a second ID of the responding read command and the data length corresponding to that read command.

[0220] The write data buffer is used to cache write command response data and handle the transmission of write response channels.

[0221] The read data buffer is used to cache the third ID of the read command transmitted through the read address channel and the target read length corresponding to the read command, cache the read command response data, and process the transmission of the read data channel.

[0222] The write command first-in-first-out queue is used to store the fourth ID of the write command transmitted through the write address channel.

[0223] The synchronization module is used to synchronize the slave device's slave takeover enable signal when the slave device malfunctions.

[0224] The state machine is also used to initiate slave device takeover based on the read data buffer and / or write data buffer, and the write command FIFO queue, after synchronizing to the slave takeover enable signal. Slave device takeover is stopped after the slave takeover enable signal is released and the stop condition is met.

[0225] The main execution module includes: the main state machine, the main synchronization module, and the interception module.

[0226] Among them, the main synchronization module and the interception module establish a path.

[0227] The master state machine establishes a communication channel with the interception module, and at the same time, the interception module establishes a communication channel with the master device.

[0228] The master state machine also establishes a path with the advanced scalable interface bus matrix, and at the same time, the master state machine establishes a path with the master device.

[0229] The master synchronization module is used to synchronize the master takeover enable signal of the master device when the master device is malfunctioning.

[0230] The master state machine stores the data transmission length of the first data sent through the write data channel. After synchronizing with the master takeover enable signal, it initiates master device takeover based on the data transmission length. Master device takeover stops after the master takeover enable signal is released and the stop condition is met.

[0231] The interception module is used to intercept the first data sent by the write data channel after the master device takes over, before the address channel handshake is completed.

[0232] The electronic device provided in this embodiment can prevent deadlock by having its computer program executed by a processor and cached through a write address channel, thus avoiding cavitation.

[0233] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0234] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0235] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0236] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0237] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0238] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0239] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for preventing deadlock on an advanced scalable interface bus, characterized in that, The write address channel of the Advanced Extensible Interface Bus introduces a write address channel cache; The method includes: Simultaneously receive the first command sent by the master device through the write address channel and the first data sent by the master device through the write data channel; When a first command is received, the received first command is sent to the slave device. At the same time, the received first command is stored in the write address channel buffer, and the write address channel is pressured back. Send the first received data to the slave device; When the WLAST signal is high, the reverse pressure of the write address channel is released, and the steps of sending the received first command to the slave device and storing the received first command in the write address channel buffer, as well as the reverse pressure of the write address channel and subsequent steps, are repeated.

2. The method according to claim 1, characterized in that, The write data channel of the Advanced Extensible Interface Bus introduces one flag bit; The initial value of the flag bit is a first value; When a first command is received, update the flag to the second value; Sending the received first data to the slave device includes: When the flag is at the second value, the received first data is sent to the slave device; The step of releasing the reverse pressure of the write address channel when the WLAST signal is high includes: When the WLAST signal is high, update the flag bit to the first value; When the flag is at its first value, the back pressure on the write address channel is released.

3. The method according to claim 1, characterized in that, The method is implemented through the first-level selection logic of the advanced extensible interface bus matrix; The advanced scalable interface bus matrix includes: multi-level selection logic; The first-level selection logic is connected to the master device; The final selection logic is connected to the slave device; The first-level selection logic also includes deadlock prevention logic; the number of levels in the multi-level selection logic is determined according to the floorplan.

4. The method according to claim 3, characterized in that, The higher-level selection logic outputs a selection signal to the lower-level selection logic.

5. The method according to claim 3, characterized in that, The selection logic in the register also includes a timing logic.

6. The advanced scalable interface bus matrix according to claim 1, characterized in that, Sending the received first command to the slave device includes: The first received command is sent to the slave device through the lower-level selection logic; Sending the received first data to the slave device includes: The first received data is sent to the slave device through the lower-level selection logic.

7. The advanced scalable interface bus matrix according to claim 3, characterized in that, The first-level selection logic is connected to the main device through the main execution module; The final-level selection logic is connected to the slave device via the execution module; The main execution module is used to monitor the main device and take over the main device when it malfunctions. The slave execution module is used to monitor the slave device and take over the slave device when it malfunctions.

8. The advanced scalable interface bus matrix according to claim 7, characterized in that, The execution module includes: a write data buffer, a read data buffer, a write command first-in-first-out queue, a slave state machine, and a slave synchronization module; Among them, the write data buffer, read data buffer, and write command first-in-first-out queue are connected to the advanced extensible interface bus matrix, and the write data buffer, read data buffer, and write command first-in-first-out queue are also connected to the slave state machine. Establish a path between the synchronization module and the slave state machine; The state machine also establishes a path with the advanced scalable interface bus matrix, and at the same time, it establishes a path with the slave device. The slave state machine is used to receive write command response data and / or read command response data from the slave device; wherein, the write command response data includes at least: a first identifier ID of the responding write command; the read command response data includes at least: a second ID of the responding read command and the data read length corresponding to the read command; The write data buffer is used to cache write command response data and handle the transmission of write response channels; The read data buffer is used to cache the third ID of the read command transmitted through the read address channel and the target read length corresponding to the read command, cache the read command response data, and process the transmission of the read data channel. The write command first-in-first-out queue is used to store the fourth ID of the write command transmitted through the write address channel; The slave synchronization module is used to synchronize the slave takeover enable signal of the slave device when the slave device is abnormal; The slave state machine is further configured to, after synchronizing to the slave takeover enable signal, enable the takeover of the slave device based on the read data buffer and / or write data buffer and the write command first-in-first-out queue; and stop the takeover of the slave device after the slave takeover enable signal is released and the stop condition is met.

9. The advanced scalable interface bus matrix according to claim 7, characterized in that, The main execution module includes: a main state machine, a main synchronization module, and an interception module; Among them, the main synchronization module and the interception module establish a communication path; The master state machine establishes a communication channel with the interception module, and at the same time, the interception module establishes a communication channel with the master device; The master state machine also establishes a path with the advanced scalable interface bus matrix, and at the same time, the master state machine establishes a path with the master device; The main synchronization module is used to synchronize the main takeover enable signal of the main device when the main device is abnormal. The master state machine is used to store the data transmission length of the first data sent through the write data channel. After synchronizing with the master takeover enable signal, it starts the takeover of the master device based on the data transmission length. After the master takeover enable signal is released and the stop condition is met, it stops the takeover of the master device. The interception module is used to intercept the first data sent by the write data channel before the address channel handshake is completed after the master device takes over.

10. An electronic device, characterized in that, Includes an advanced scalable interface bus matrix; The Advanced Scalable Interface Bus (ASME) matrix implements the ASME anti-deadlock method as described in any one of claims 1-9.

Images