Block RAM process mapping method

Abstract

The invention discloses a Block RAM (Random Access Memory) process mapping method. In the target FPGA design, obtaining a target memory to be processed and current attribute information; if the non-standard memory template register transfer level design is determined, obtaining current random access memory layout netlist information, a current read-write port and a current layout netlist; and querying the current layout netlist through a layout netlist traversal search method to obtain target memory query description information, matching the target memory query description information with a memory splitting processing method library, and obtaining a target standard splitting processing memory according to a matched memory splitting processing mode so as to realize Block RAM process mapping. The problems that the workload is large due to RTL rewriting and the product performance is poor due to mapping to non-special physical storage resources are solved, and accurate process mapping of the split memory is improved.

Description

Technical Field

[0001] This invention relates to the field of FPGA data processing technology, and in particular to a Block RAM process mapping method. Background Technology

[0002] In the design of FPGAs (Field Programmable Gate Arrays) and application-specific integrated circuits (ASICs), data is typically stored in memory for efficient data reading and writing. Memory can be implemented using URAM, BRAM, LUTRAM, and FFRAM resources within the FPGA. When user design requirements are met and resources are sufficient, dedicated physical memory resources, such as URAM or BRAM, should be prioritized. Dedicated physical memory resources offer larger capacities and higher integration, which facilitates final placement and routing and improves the performance of the final product.

[0003] In the process of developing this invention, the inventors discovered the following shortcomings in the prior art: When the memory usage logic in a user's design is complex, such as when the number of read / write ports is unequal, or when memory is read and written bit-by-bit, resulting in a large number of read / write ports, the synthesizer typically cannot synthesize dedicated physical storage resources and instead uses non-dedicated physical storage resources (such as LUTRAM or FFRAM) as a substitute. If the memory itself is also large, this can lead to the consumption of a large amount of LUTRAM or FFRAM resources, and in some scenarios, synthesis may even be impossible. Even if LUTRAM or FFRAM is eventually synthesized, insufficient resources may prevent the final process mapping from being completed.

[0004] In existing technologies, the design is typically rewritten using the standard memory template RTL by rewriting the RTL (Register Transfer Level). This results in a large workload and is inconvenient in some cases. Another approach is to map memory to non-dedicated physical storage resources by splitting the original design across multiple FPGA resources. However, this increases the overall resource cost, and the interconnection between FPGAs affects the final performance of the product. Summary of the Invention

[0005] This invention provides a Block RAM process mapping method to achieve accurate Block RAM process mapping of the split memory.

[0006] According to one aspect of the present invention, a Block RAM process mapping method is provided, comprising:

[0007] In the target FPGA design, obtain the target memory to be processed, and the current attribute information corresponding to the target memory;

[0008] Based on the current attribute information, if it is determined that the target memory is a non-standard memory template register transfer level design, then the current random access memory layout netlist information, current read / write port and current layout netlist corresponding to the target memory are obtained;

[0009] Based on the current random access memory layout netlist information and the current read / write port, the current layout netlist is queried using a preset layout netlist traversal search method to obtain the target memory query description information.

[0010] The target memory query description information is matched with a pre-built memory splitting processing method library, and the target memory is processed according to the matched memory splitting processing method to obtain the target standard splitting processed memory, so as to realize the Block RAM process mapping of the target FPGA design according to the target standard splitting processed memory.

[0011] According to another aspect of the present invention, a Block RAM process mapping apparatus is provided, comprising:

[0012] The current attribute information acquisition module is used to acquire the target memory to be processed and the current attribute information corresponding to the target memory in the target FPGA design.

[0013] The current random access memory layout netlist information, current read / write port and current layout netlist acquisition module is used to acquire the current random access memory layout netlist information, current read / write port and current layout netlist corresponding to the target memory if it is determined that the target memory is a non-standard memory template register transfer level design based on the current attribute information.

[0014] The target memory query description information determination module is used to query the current layout netlist based on the current random access memory layout netlist information and the current read / write port, and obtain the target memory query description information by using a preset layout netlist traversal search method.

[0015] The target standard split processing memory determination module is used to match the target memory query description information with a pre-built memory split processing method library, and process the target memory according to the matched memory split processing method to obtain the target standard split processing memory, so as to realize the Block RAM process mapping of the target FPGA design according to the target standard split processing memory.

[0016] According to another aspect of the present invention, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the Block RAM process mapping method according to any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the Block RAM process mapping method according to any embodiment of the present invention.

[0018] The technical solution of this invention involves obtaining the target memory to be processed and the current attribute information corresponding to the target memory in the target FPGA design; based on the current attribute information, if it is determined that the target memory is a non-standard memory template register transfer level design, then obtaining the current random access memory layout netlist information, current read / write port, and current layout netlist corresponding to the target memory; based on the current random access memory layout netlist information and current read / write port, querying the current layout netlist using a preset layout netlist traversal search method to obtain target memory query description information; matching the target memory query description information with a pre-built memory splitting processing method library, and processing the target memory according to the matched memory splitting processing method to obtain the target standard splitting processed memory, thereby realizing the Block RAM process mapping of the target FPGA design based on the target standard splitting processed memory. It solves the problems of high workload caused by rewriting RTL and poor product performance caused by mapping to non-dedicated physical storage resources. It improves the efficiency, accuracy and success rate of Block RAM process mapping using split memory, thereby improving product performance and reducing workload.

[0019] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart of the Block RAM process mapping method provided in Embodiment 1 of the present invention;

[0022] Figure 2 This is a schematic diagram of a Block RAM process mapping device according to Embodiment 2 of the present invention;

[0023] Figure 3 This is a schematic diagram of the structure of an electronic device provided according to Embodiment 3 of the present invention. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "target," "current," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] It is worth noting that the information collected in the technical solution of this application is information and data authorized by the user or fully authorized by all parties, and the collection, storage, use, processing, transmission, provision, disclosure and application of the relevant data all comply with the relevant laws, regulations and standards of the relevant countries and regions, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entry points for users to choose to authorize or refuse; if the user chooses to refuse, the process will proceed to the expert decision-making process.

[0027] Example 1

[0028] Figure 1 The flowchart of a Block RAM process mapping method provided in Embodiment 1 of the present invention is applicable to the case where memory in an FPGA is split into smaller parts to perform process mapping on the Block RAM of the target FPGA design based on the split memory. This method can be executed by a Block RAM process mapping device, which can be implemented in hardware and / or software.

[0029] Correspondingly, such as Figure 1 As shown, the method includes:

[0030] S110. In the target FPGA design, obtain the target memory to be processed and the current attribute information corresponding to the target memory.

[0031] The current attribute information includes: the current number of ports, the current port data bit width, the current address signal, the trigger information connected to the current address, the current write port information, and the current write port clock signal information.

[0032] The current number of ports includes the current number of read ports and the current number of write ports.

[0033] In this embodiment, the process mapping of the Block RAM of the target FPGA design is performed based on the target memory to be processed. However, since the target memory to be processed can be a standard memory template register-transfer level design or a non-standard memory template register-transfer level design, directly performing process mapping on the memory of a non-standard memory template register-transfer level design may lead to poor product performance and a large workload. Therefore, processing is required before performing the process mapping operation on the Block RAM of the target FPGA design. The Block RAM is a computing unit chip module in the target FPGA, and the processed memory needs to undergo process mapping on the Block RAM.

[0034] S120. Based on the current attribute information, if it is determined that the target memory is a non-standard memory template register transfer level design, then obtain the current random access memory layout netlist information, current read / write port and current layout netlist corresponding to the target memory.

[0035] Optionally, the step of obtaining the current random access memory layout netlist information, current read / write ports, and current layout netlist corresponding to the target memory based on the current attribute information, if the target memory is determined to be a non-standard memory template register-transfer level design, includes: inputting the current attribute information into a pre-set standard memory usage logic template library for matching; if the matching is successful, the target memory is determined to be a standard memory template register-transfer level design, and the Block RAM process mapping of the target FPGA design is completed according to the standard memory template register-transfer level design; if the matching is unsuccessful, the target memory is determined to be a non-standard memory template register-transfer level design, and the current random access memory layout netlist information corresponding to the target memory is obtained, along with the current read / write ports and current layout netlist corresponding to the current random access memory layout netlist information.

[0036] In this embodiment, because the user-designed memory usage logic may be complex, including inconsistent read / write ports or a large number of read / write ports due to bit-based memory read / write, the synthesizer usually cannot synthesize dedicated memory resources. Therefore, the current attribute information needs to be input into the standard memory usage logic template library for matching. If a match is found, the target memory can be determined to be a standard memory template register-transfer level design, and the Block RAM process mapping of the target FPGA design can be directly completed based on the standard memory template register-transfer level design. Otherwise, it means that no standard memory usage logic template was hit, and therefore it is determined to be a non-standard memory template register-transfer level design. The current random access memory layout netlist information, current read / write ports, and current layout netlist corresponding to the target memory are obtained.

[0037] For a specific example of inconsistent read and write ports, assume that the current number of read ports and the current number of write ports corresponding to the current number of ports are obtained; if the current number of read ports is 1 and the current number of write ports is 1, then the target memory is determined to be a standard memory template register-transfer level design, and the Block RAM process mapping of the target FPGA design is completed according to the standard memory template register-transfer level design; if the current number of read ports is not 1 and the current number of write ports is not 1, then the target memory is determined to be a non-standard memory template register-transfer level design, and the current random access memory layout netlist information, current read ports, and current layout netlist corresponding to the target memory are obtained.

[0038] In this embodiment, it is necessary to first determine whether the current number of read ports and the current number of write ports are both 1. If so, it means that the target memory is a standard memory template register transfer level design, and the Block RAM process mapping can be completed directly according to the standard memory template register transfer level design.

[0039] However, if there is at least one current read port count that is not 1, or a current write port count that is not 1, it indicates that the target memory is a non-standard memory template register transfer level design. Therefore, it is necessary to obtain the current random access memory layout netlist information, current read / write ports, and current layout netlist corresponding to the target memory.

[0040] S130. Based on the current random access memory layout netlist information and the current read / write port, the current layout netlist is queried using a preset layout netlist traversal search method to obtain the target memory query description information.

[0041] In this embodiment, it can be assumed that the current random access memory layout netlist information is ramnet. The corresponding initial value and one or more current read / write ports can be obtained based on ramnet. The layout netlist traversal search method can be a method of updating the netlist by finding the driver device (next device) of the layout netlist (which can be denoted as net).

[0042] Optionally, the step of querying the current layout netlist based on the current random access memory layout netlist information and the current read / write port using a preset layout netlist traversal search method to obtain the target memory query description information includes: establishing a current read / write port status array corresponding to the current read / write port based on the current random access memory layout netlist information and the current port data bit width; wherein, the current read / write port status array is used to store the layout netlist corresponding to each bit of data in the data port; the initial value of the current read / write port status array is the current layout netlist directly connected to the data port corresponding to the current read / write port; and querying the current layout netlist in the current read / write port status array using the layout netlist traversal search method to obtain the target memory query description information.

[0043] In this embodiment, on the ramnet, a current read / write port status array corresponding to the current read / write port can be established based on the current port data bit width. This array can be set to... Specifically, The initial value is the data port corresponding to the current read / write port (set to...). The currently connected netlist of the current layout. For storage The net in the final output corresponds to each bit of data in the net.

[0044] Specifically, the step of querying the current layout netlist in the current read / write port status array using the layout netlist traversal search method to obtain the target memory query description information includes: querying the current layout netlist in the current read / write port status array using a preset layout netlist traversal search method; if the query determines a target driver device corresponding to the current layout netlist and a new layout netlist corresponding to the output of the target driver device, then updating each bit of data in the data port corresponding to the new layout netlist; and determining the target memory query description information based on the current address signal, the trigger information connected to the current address, the current write port information, and the current write port clock signal information. If the current search conditions meet the preset joint stop traversal conditions, and if they do, the flag in the current read / write port status array is updated to the completed state, and the target memory query description information is obtained based on the new layout netlist. The joint stop traversal conditions include at least one of the following: the current layout netlist reaches the module boundary of the target memory, the current layout netlist is connected to a non-dedicated physical storage resource, and the current layout netlist is connected to the write port of the target memory. If the conditions are not met, the operation of searching the current layout netlist in the current read / write port status array by means of the preset layout netlist traversal search method is returned.

[0045] In this embodiment, the current read / write port status array is first searched by traversing the layout netlist. The current net is searched. If the search finds a target driver device (which can be set to an instance) corresponding to the current net, and a new net corresponding to the instance output, then the net corresponding to the new net is updated. Each bit of data in the file.

[0046] Furthermore, based on the current address signal, the trigger information connected to the current address, the current write port information, and the current write port clock signal information, it is determined whether the current search condition meets the preset joint stop traversal condition. Specifically, it is necessary to determine whether the current net search has reached the module boundary of the target memory. If so, the joint stop traversal condition is met, and the flag bit of the current read / write port status array can be updated to the completed state (specifically, it can be set...). If the flag is true, the target memory query description information is obtained based on the new net. Otherwise, the operation of searching the current layout netlist in the current read / write port status array by traversing the preset layout netlist needs to be continued.

[0047] Furthermore, it is necessary to determine whether the current layout netlist is connected to a non-dedicated physical storage resource (such as LUTRAM or FFRAM) based on the current address signal and the trigger information connected to the current address. If so, the joint stop traversal condition is met, and the flag of the current read / write port status array can be updated to the completed state (specifically, it can be set...). If the flag is true, the target memory query description information is obtained based on the new net. Otherwise, the operation of searching the current layout netlist in the current read / write port status array by traversing the preset layout netlist needs to be continued.

[0048] Correspondingly, it is also necessary to determine whether the current layout netlist is connected to the write port of the target memory based on the current write port information and the current write port clock signal information. If so, the joint stop traversal condition is met, and the flag of the current read / write port status array can be updated to the completed state (specifically, it can be set to...). If the flag is true, the target memory query description information is obtained based on the new net. Otherwise, the operation of searching the current layout netlist in the current read / write port status array by traversing the preset layout netlist needs to be continued.

[0049] The advantage of this setting is that it can accurately perform the lookup and processing operations of the current layout netlist, and can stop traversal and obtain a new layout netlist when the joint stopping traversal condition is met. This can reduce the workload and improve the efficiency and accuracy of determining the memory query description information.

[0050] S140. Match the target memory query description information with the pre-built memory splitting processing method library, and process the target memory according to the matched memory splitting processing method to obtain the target standard splitting processed memory, so as to realize the Block RAM process mapping of the target FPGA design according to the target standard splitting processed memory.

[0051] The memory partitioning method library can be a database that stores various partitioning methods. The memory partitioning method library is built using historical data, and the specific operation is as follows.

[0052] Optionally, before obtaining the target memory to be processed and the current attribute information corresponding to the target memory in the target FPGA design, the method further includes: obtaining each historical memory and the historical attribute information corresponding to each historical memory; obtaining the historical memory query description information and historical memory splitting processing method corresponding to each historical attribute information; and jointly storing the historical attribute information, historical memory identification layout netlist and historical memory splitting processing method corresponding to each historical memory to obtain the constructed memory splitting processing method library.

[0053] In this embodiment, it is necessary to acquire multiple historical memories on each FPGA, as well as corresponding historical attribute information. By identifying each historical attribute, the historical memory query description information and the historical memory splitting processing method corresponding to each historical memory query description information are determined.

[0054] Furthermore, the aforementioned data can be combined for storage to obtain a completed memory partitioning method library. Specifically, for this library, corresponding memory partitioning methods can be matched based on randomly obtained memory query description information.

[0055] Optionally, the memory partitioning processing method library includes a bit-by-bit read-write partitioning method, a partial bit selection write partitioning method, a read port data loopback write port partitioning processing method, and a write port enable signal mutual exclusion partitioning method; the step of matching the target memory query description information with the pre-built memory partitioning processing method library, and processing the target memory according to the matched memory partitioning method to obtain the target standard partitioned memory includes: matching the target memory query description information with the memory partitioning processing method library; if no match is found, no partitioning processing is performed on the target memory; if a bit-by-bit read-write partitioning method is matched, the target memory is partitioned bit by bit to obtain the target standard partitioned memory; wherein, the target standard The split processing memory includes multiple target standard split processing sub-memories, each processing 1 bit of data. If a partial bit selection write splitting method is matched, the target memory is split according to the specified partial bit to obtain the target standard split processing memory. The number of target standard split processing sub-memories contained in the target standard split processing memory is consistent with the number of bits in the specified partial bit. If a read port data loopback write port splitting processing method is matched, one read port corresponding to the target memory is removed, and the enable bit of the write port is modified to obtain the target standard split processing memory. If a write port enable signal mutual exclusion splitting method is matched, one write port corresponding to the target memory is removed to obtain the target standard split processing memory.

[0056] The bit-by-bit read / write splitting method targets a memory query description where the number of read and write ports is consistent. Each read or write port can process 1 bit of data, and the number of ports matches the port data width of the memory. This splitting method requires copying n copies (n being the port data width) of the ramnet and splitting the memory bit by bit. Each split sub-memory can process 1 bit of data.

[0057] Specifically, each sub-memory needs to have read and write ports created, and the address, clock, and enable signals must be set to match the original read and write ports. The write port of each sub-memory connects to the data port of the target memory, and the new net connects to the data port of the write port. Furthermore, the nets of the read ports of multiple sub-memories need to be concatenated, and the original target memory and its associated read and write port information must be deleted.

[0058] The partial bit selection write splitting method targets specific bits of memory for write operations. It requires splitting the memory according to the specified bits, and each split sub-memory can process 1 bit of data.

[0059] The read port data loop and write port splitting method can be used for cases with two read ports and one write port. That is, data entering from one read port of memory flows to the write port and then to another read port, causing a data loop. This can be solved by removing one read port and readjusting the enable bit of the write port.

[0060] The write port enable signal mutual exclusion splitting method can be used for cases where there are two write ports for memory and the enable signals of the two write ports are mutually exclusive. This can be solved by deleting one of the write ports with mutually exclusive signals.

[0061] In this embodiment, the target memory query description information needs to be matched with the memory splitting processing method library first. If they cannot be matched, the target memory will not be split and the original memory will be used for design processing. Furthermore, the target memory can be parsed and the parsed results can be added to the memory splitting processing method library to realize the update processing operation of the memory splitting processing method library.

[0062] Furthermore, assuming matching is possible, it is necessary to determine which specific splitting method is matched and to perform the memory splitting operation according to the corresponding method.

[0063] Specifically, if a bit-by-bit read / write splitting method is matched, the target memory is split bit by bit to obtain multiple target standard splitting sub-memories, each processing 1 bit of data. For example, assuming there are 5 bits of data, the original target memory needs to be split into 5 target standard splitting sub-memories. Each sub-memory requires the creation of corresponding read and write ports, and the address signals, clock signals, and various enable signals are set to be consistent with the original read and write ports. The write port of each sub-memory is connected to the data port of the target memory, and a new net is connected to the data port of the write port. Furthermore, the nets of the read ports of multiple sub-memories need to be concatenated, and the original target memory and related read / write port information are deleted.

[0064] Furthermore, if a partial bit selection write splitting method is matched, the target memory is split according to the specified partial bits, resulting in a target standard split-processed memory where the number of sub-memories matches the number of bits in the specified partial bits. If a read port data loopback write port splitting method is matched, one read port corresponding to the target memory is removed, and the enable bit of the write port is modified to obtain the target standard split-processed memory. Conversely, if a write port enable signal mutual exclusion splitting method is matched, one write port corresponding to the target memory's mutual exclusion enable signal needs to be removed to obtain the target standard split-processed memory.

[0065] The technical solution of this invention involves obtaining the target memory to be processed and the current attribute information corresponding to the target memory in the target FPGA design; based on the current attribute information, if it is determined that the target memory is a non-standard memory template register transfer level design, then obtaining the current random access memory layout netlist information, current read / write port, and current layout netlist corresponding to the target memory; based on the current random access memory layout netlist information and current read / write port, querying the current layout netlist using a preset layout netlist traversal search method to obtain target memory query description information; matching the target memory query description information with a pre-built memory splitting processing method library, and processing the target memory according to the matched memory splitting processing method to obtain the target standard splitting processed memory, thereby realizing the Block RAM process mapping of the target FPGA design based on the target standard splitting processed memory. It solves the problems of high workload caused by rewriting RTL and poor product performance caused by mapping to non-dedicated physical storage resources. It improves the efficiency, accuracy and success rate of Block RAM process mapping using split memory, thereby improving product performance and reducing workload.

[0066] Example 2

[0067] Figure 2 This is a schematic diagram of a Block RAM process mapping apparatus provided in Embodiment 2 of the present invention. The Block RAM process mapping apparatus provided in this embodiment can be implemented by software and / or hardware, and can be configured in a terminal device or server to implement a Block RAM process mapping method according to an embodiment of the present invention. Figure 2As shown, the device includes: a current attribute information acquisition module 210, a current random access memory layout netlist information, current read / write port and current layout netlist acquisition module 220, a target memory query description information determination module 230 and a target standard split processing memory determination module 240.

[0068] The current attribute information acquisition module 210 is used to acquire the target memory to be processed and the current attribute information corresponding to the target memory in the target FPGA design.

[0069] The current random access memory layout netlist information, current read / write port and current layout netlist acquisition module 220 is used to acquire the current random access memory layout netlist information, current read / write port and current layout netlist corresponding to the target memory if it is determined that the target memory is a non-standard memory template register transfer level design based on the current attribute information.

[0070] The target memory query description information determination module 230 is used to query the current layout netlist based on the current random access memory layout netlist information and the current read / write port, and obtain the target memory query description information by means of a preset layout netlist traversal search method.

[0071] The target standard split processing memory determination module 240 is used to match the target memory query description information with a pre-built memory split processing method library, and process the target memory according to the matched memory split processing method to obtain the target standard split processing memory, so as to realize the Block RAM process mapping of the target FPGA design according to the target standard split processing memory.

[0072] The technical solution of this invention involves obtaining the target memory to be processed and the current attribute information corresponding to the target memory in the target FPGA design; based on the current attribute information, if it is determined that the target memory is a non-standard memory template register transfer level design, then obtaining the current random access memory layout netlist information, current read / write port, and current layout netlist corresponding to the target memory; based on the current random access memory layout netlist information and current read / write port, querying the current layout netlist using a preset layout netlist traversal search method to obtain target memory query description information; matching the target memory query description information with a pre-built memory splitting processing method library, and processing the target memory according to the matched memory splitting processing method to obtain the target standard splitting processed memory, thereby realizing the Block RAM process mapping of the target FPGA design based on the target standard splitting processed memory. It solves the problems of high workload caused by rewriting RTL and poor product performance caused by mapping to non-dedicated physical storage resources. It improves the efficiency, accuracy and success rate of Block RAM process mapping using split memory, thereby improving product performance and reducing workload.

[0073] Based on the above embodiments, the current attribute information includes: the current number of ports, the current port data bit width, the current address signal, the trigger information connected to the current address, the current write port information, and the current write port clock signal information.

[0074] Based on the above embodiments, the current random access memory layout netlist information, current read / write port, and current layout netlist acquisition module 220 can be specifically used to: input the current attribute information into a pre-set standard memory usage logic template library for matching; if the matching is successful, the target memory is determined to be a standard memory template register-transfer level design, and the Block RAM process mapping of the target FPGA design is completed according to the standard memory template register-transfer level design; if the matching is unsuccessful, the target memory is determined to be a non-standard memory template register-transfer level design, and the current random access memory layout netlist information corresponding to the target memory is obtained, and the current read / write port and current layout netlist corresponding to the current random access memory layout netlist information are obtained.

[0075] Based on the above embodiments, the current random access memory layout netlist information, current read / write port, and current layout netlist acquisition module 220 can also be specifically used to: establish a current read / write port status array corresponding to the current read / write port based on the current random access memory layout netlist information and the current port data bit width; wherein, the current read / write port status array is used to store the layout netlist corresponding to each bit of data in the data port; the initial value of the current read / write port status array is the current layout netlist directly connected to the data port corresponding to the current read / write port; in the current read / write port status array, the current layout netlist is queried through the layout netlist traversal search method to obtain the target memory query description information.

[0076] Based on the above embodiments, the target memory query description information determination module 230 can be specifically used to: query the current layout netlist in the current read / write port status array using a preset layout netlist traversal search method; if the query determines a target driver device corresponding to the current layout netlist and a new layout netlist corresponding to the output of the target driver device, then update each bit of data in the data port corresponding to the new layout netlist; and determine whether the current search conditions are satisfied based on the current address signal, the trigger information connected to the current address, the current write port information, and the current write port clock signal information. If a set joint stopping traversal condition is met, the flag in the current read / write port status array is updated to the completed state, and the target memory query description information is obtained based on the new layout netlist. The joint stopping traversal condition includes at least one of the following: the current layout netlist reaches the module boundary of the target memory; the current layout netlist is connected to a non-dedicated physical storage resource; and the current layout netlist is connected to the write port of the target memory. If the condition is not met, the process returns to performing the search operation of the current layout netlist in the current read / write port status array using the preset layout netlist traversal search method.

[0077] Based on the above embodiments, the memory splitting processing method library includes a bit-by-bit read-write splitting method, a partial bit selection write splitting method, a read port data loopback write port splitting processing method, and a write port enable signal mutual exclusion splitting method.

[0078] Based on the above embodiments, the target standard splitting processing memory determination module 240 can be specifically used to: match the target memory query description information with the memory splitting processing method library; if no match is found, no splitting processing is performed on the target memory; if a bit-by-bit read / write splitting method is matched, the target memory is split bit by bit to obtain the target standard splitting processing memory; wherein, the target standard splitting processing memory includes multiple target standard splitting processing sub-memories, each target standard splitting processing sub-memory processes 1 bit of data; if a partial match is found... If the bit selection write splitting method is used, the target memory is split according to the specified part of the bits to obtain the target standard split processed memory; wherein the number of target standard split processed sub-memories contained in the target standard split processed memory is consistent with the number of bits in the specified part of the bits; if the read port data loopback write port splitting processing method is matched, one read port corresponding to the target memory is removed and the enable bit of the write port is modified to obtain the target standard split processed memory; if the write port enable signal mutual exclusion splitting method is matched, one write port corresponding to the target memory is removed to obtain the target standard split processed memory.

[0079] Based on the above embodiments, a memory splitting processing method library construction module is also included, which can be specifically used to: before obtaining the target memory to be processed and the current attribute information corresponding to the target memory in the target FPGA design, the module further includes: obtaining each historical memory and the historical attribute information corresponding to each historical memory; obtaining historical memory query description information and historical memory splitting processing methods corresponding to each historical attribute information; and jointly storing the historical attribute information, historical memory identification layout netlist and historical memory splitting processing methods corresponding to each historical memory to obtain the constructed memory splitting processing method library.

[0080] The Block RAM process mapping apparatus provided in this embodiment of the invention can execute the Block RAM process mapping method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method execution.

[0081] Example 3

[0082] Figure 3A schematic diagram of an electronic device 10, which can be used to implement Embodiment 3 of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0083] like Figure 3 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0084] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0085] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as BlockRAM process mapping methods.

[0086] In some embodiments, the Block RAM process mapping method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the Block RAM process mapping method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to execute the Block RAM process mapping method by any other suitable means (e.g., by means of firmware).

[0087] The method includes: in the target FPGA design, acquiring the target memory to be processed and the current attribute information corresponding to the target memory; based on the current attribute information, if it is determined that the target memory is a non-standard memory template register transfer level design, acquiring the current random access memory layout netlist information, current read / write port, and current layout netlist corresponding to the target memory; based on the current random access memory layout netlist information and current read / write port, querying the current layout netlist using a preset layout netlist traversal search method to obtain target memory query description information; matching the target memory query description information with a pre-built memory splitting processing method library, and processing the target memory according to the matched memory splitting processing method to obtain the target standard splitting processed memory, so as to realize the Block RAM process mapping of the target FPGA design based on the target standard splitting processed memory.

[0088] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0089] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0090] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0091] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0092] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0093] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0094] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0095] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

[0096] Example 4

[0097] Embodiment 4 of the present invention also provides a computer-readable storage medium, wherein the computer-readable instructions, when executed by a computer processor, are used to perform a Block RAM process mapping method. The method includes: in a target FPGA design, obtaining a target memory to be processed and current attribute information corresponding to the target memory; based on the current attribute information, if it is determined that the target memory is a non-standard memory template register-transfer level design, obtaining the current random access memory layout netlist information, the current read / write port, and the current layout netlist corresponding to the target memory; based on the current random access memory layout netlist information and the current read / write port, querying the current layout netlist using a preset layout netlist traversal search method to obtain target memory query description information; matching the target memory query description information with a pre-built memory splitting processing method library, and processing the target memory according to the matched memory splitting processing method to obtain a target standard splitting processed memory, thereby realizing the Block RAM process mapping of the target FPGA design based on the target standard splitting processed memory.

[0098] Of course, the computer-executable instructions provided in the embodiments of the present invention are not limited to the method operations described above, but can also perform related operations in the Block RAM process mapping provided in any embodiment of the present invention.

[0099] Based on the above description of the implementation methods, those skilled in the art can clearly understand that the present invention can be implemented using software and necessary general-purpose hardware, and of course, it can also be implemented using hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0100] It is worth noting that in the above-described Block RAM process mapping embodiments, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the scope of protection of the present invention.

[0101] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A Block RAM process mapping method, characterized in that, include: In the target FPGA design, obtain the target memory to be processed, and the current attribute information corresponding to the target memory; Based on the current attribute information, if it is determined that the target memory is a non-standard memory template register transfer level design, then the current random access memory layout netlist information, current read / write port and current layout netlist corresponding to the target memory are obtained; Based on the current random access memory layout netlist information and the current read / write port, the current layout netlist is queried using a preset layout netlist traversal search method to obtain the target memory query description information. The target memory query description information is matched with a pre-built memory splitting processing method library, and the target memory is processed according to the matched memory splitting processing method to obtain the target standard splitting processed memory, so as to realize the Block RAM process mapping of the target FPGA design according to the target standard splitting processed memory.

2. The method according to claim 1, characterized in that, The current attribute information includes: the current number of ports, the current port data bit width, the current address signal, the trigger information connected to the current address, the current write port information, and the current write port clock signal information.

3. The method according to claim 2, characterized in that, Based on the current attribute information, if it is determined that the target memory is a non-standard memory template register-transfer level design, then the current random access memory layout netlist information, current read / write ports, and current layout netlist corresponding to the target memory are obtained, including: The current attribute information is input into the pre-set standard memory logic template library for matching. If the matching is successful, the target memory is determined to be a standard memory template register transfer level design, and the Block RAM process mapping of the target FPGA design is completed according to the standard memory template register transfer level design. If the match fails, the target memory is determined to be a non-standard memory template register transfer level design, and the current random access memory layout netlist information corresponding to the target memory is obtained, along with the current read / write port and current layout netlist corresponding to the current random access memory layout netlist information.

4. The method according to claim 3, characterized in that, The step involves querying the current random access memory layout netlist information and the current read / write port using a preset layout netlist traversal search method to obtain target memory query description information, including: Based on the current random access memory layout netlist information and the current port data bit width, establish a current read / write port status array corresponding to the current read / write port; The current read / write port status array is used to store the layout netlist corresponding to each bit of data in the data port; the initial value of the current read / write port status array is the current layout netlist directly connected to the data port corresponding to the current read / write port. In the current read / write port status array, the current layout netlist is queried using the layout netlist traversal search method to obtain the target memory query description information.

5. The method according to claim 4, characterized in that, The step involves querying the current layout netlist in the current read / write port status array using the layout netlist traversal search method to obtain the target memory query description information, including: The current layout netlist in the current read / write port status array is queried using a preset layout netlist traversal search method. If the query determines the target driver device corresponding to the current layout netlist and the new layout netlist corresponding to the output of the target driver device, then each bit of data in the data port corresponding to the new layout netlist is updated. Based on the current address signal, the trigger information connected to the current address, the current write port information, and the current write port clock signal information, determine whether the current search condition meets the preset joint stop traversal condition. If it does, update the flag bit of the current read / write port status array to the completed state, and obtain the target memory query description information based on the new layout netlist. The joint stopping traversal condition includes at least one of the following: the current layout netlist reaches the module boundary of the target memory, the current layout netlist is connected to a non-dedicated physical storage resource, and the current layout netlist is connected to the write port of the target memory. If the conditions are not met, the operation of searching the current layout netlist in the current read / write port status array by traversing the preset layout netlist is returned.

6. The method according to claim 5, characterized in that, The memory splitting processing method library includes a bit-by-bit read-write splitting method, a partial bit selection write splitting method, a read port data loopback write port splitting processing method, and a write port enable signal mutual exclusion splitting method. The step of matching the target memory query description information with a pre-built memory splitting processing method library, and processing the target memory according to the matched memory splitting method to obtain the target standard splitting processed memory, includes: The target memory query description information is matched with the memory splitting processing method library. If no match is found, the target memory is not split. If the bit-by-bit read-write splitting method is matched, the target memory is split into bits to obtain the target standard splitting processed memory; wherein, the target standard splitting processed memory includes multiple target standard splitting processed sub-memories, and each target standard splitting processed sub-memory processes 1 bit of data; If a partial bit selection method is chosen, the target memory is split according to the specified partial bit to obtain the target standard split memory; wherein, the number of target standard split sub-memories contained in the target standard split memory is the same as the number of bits of the specified partial bit. If the read port data loopback write port splitting processing method is matched, then remove one read port corresponding to the target memory and modify the enable bit of the write port to obtain the target standard split processing memory. If the write port enable signal mutual exclusion splitting method is matched, then one write port corresponding to the target memory is removed to obtain the target standard splitting processing memory.

7. The method according to claim 6, characterized in that, Before obtaining the target memory to be processed and the current attribute information corresponding to the target memory in the target FPGA design, the method further includes: Obtain each historical memory and the historical attribute information corresponding to each historical memory; Obtain historical memory query description information and historical memory splitting processing methods corresponding to each historical attribute information; By jointly storing the historical attribute information, the historical memory identification layout netlist, and the historical memory splitting processing method corresponding to each historical memory, a complete memory splitting processing method library is obtained.

8. A Block RAM process mapping apparatus, characterized in that, include: The current attribute information acquisition module is used to acquire the target memory to be processed and the current attribute information corresponding to the target memory in the target FPGA design. The current random access memory layout netlist information, current read / write port and current layout netlist acquisition module is used to acquire the current random access memory layout netlist information, current read / write port and current layout netlist corresponding to the target memory if it is determined that the target memory is a non-standard memory template register transfer level design based on the current attribute information. The target memory query description information determination module is used to query the current layout netlist based on the current random access memory layout netlist information and the current read / write port, and obtain the target memory query description information by using a preset layout netlist traversal search method. The target standard split processing memory determination module is used to match the target memory query description information with a pre-built memory split processing method library, and process the target memory according to the matched memory split processing method to obtain the target standard split processing memory, so as to realize the Block RAM process mapping of the target FPGA design according to the target standard split processing memory.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements a Block RAM process mapping method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute a BlockRAM process mapping method as described in any one of claims 1-7.

Images