Supercomputing node and quantum node interaction method oriented to heterogeneous measurement and control board card

Abstract

The embodiment of the invention discloses a supercomputing node and quantum node interaction method oriented to a heterogeneous measurement and control board card. A specific embodiment of the method comprises the following steps: performing request monitoring on a supercomputing node through a daemon process corresponding to a heterogeneous measurement and control board card; receiving an instruction request initiated by the supercomputing node, and performing request analysis and adaptation on the instruction request; transmitting the adapted instruction request to a heterogeneous measurement and control board card through a daemon process and a PCIe bus; carrying out request processing on the adapted instruction request through an FPGA unit and a digital-to-analog converter which are included in the heterogeneous measurement and control board card; controlling quantum nodes to operate according to the analog signal, and generating a control result; performing analog-to-digital conversion on the control result through an analog-to-digital converter; and transmitting the digital signal to a supercomputing node. According to the embodiment, the problem of distributed collaboration between the supercomputing node corresponding to the computer and the quantum node corresponding to the quantum computer in a distributed computing system under a classic heterogeneous fusion computing system is solved.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the fields of quantum computing and communications, specifically to an interaction method between supercomputing nodes and quantum nodes for heterogeneous measurement and control boards. Background Technology

[0002] There have been preliminary explorations of architectures that integrate supercomputing nodes based on classical computers and quantum nodes based on quantum computers. For example, the existing architecture of "supercomputing node-host computer-quantum node" is loosely coupled, meaning that the supercomputing node, host computer, and quantum node are independent of each other. The communication links and control logic in distributed scenarios have not been optimized, resulting in "low communication efficiency between supercomputing nodes and quantum nodes, making it difficult to efficiently cope with the task requirements of multi-node, distributed computing". Summary of the Invention

[0003] The summary portion of this disclosure is intended to provide a brief overview of the concepts, which will be described in detail in the detailed description portion. This summary portion is not intended to identify key or essential features of the claimed technical solutions, nor is it intended to limit the scope of the claimed technical solutions.

[0004] Some embodiments of this disclosure propose an interaction method for supercomputing nodes and quantum nodes for heterogeneous measurement and control boards to solve the technical problems mentioned in the background section above.

[0005] In a first aspect, some embodiments of this disclosure provide an interaction method between a supercomputing node and a quantum node for a heterogeneous measurement and control board. The method includes: listening to requests from the supercomputing node through a daemon process corresponding to the heterogeneous measurement and control board; receiving the instruction request initiated by the supercomputing node in response to the daemon process listening to the instruction request; parsing and adapting the instruction request to obtain an adapted instruction request; transmitting the adapted instruction request to the heterogeneous measurement and control board through the daemon process and the PCIe bus; processing the adapted instruction request through the FPGA unit and digital-to-analog converter included in the heterogeneous measurement and control board to obtain an analog signal; controlling the operation of the quantum node based on the analog signal and generating control results, wherein the analog signal and control results are monitored using an oscilloscope; converting the control results from analog to digital using an analog-to-digital converter to obtain a digital signal; and transmitting the digital signal to the supercomputing node based on the FPGA unit and the corresponding daemon process included in the heterogeneous measurement and control board.

[0006] Secondly, some embodiments of this disclosure provide an interaction device for supercomputing nodes and quantum nodes on heterogeneous measurement and control boards. The device includes: a request listening unit configured to listen for requests to the supercomputing node through a daemon process corresponding to the heterogeneous measurement and control board; a receiving unit configured to receive the instruction request initiated by the supercomputing node in response to the daemon process listening for the instruction request initiated by the supercomputing node, and to parse and adapt the instruction request to obtain an adapted instruction request; and a first transmission unit configured to transmit the adapted instruction request to the heterogeneous measurement and control board through the daemon process and the PCIe bus. The request processing unit is configured to process instruction requests using the FPGA unit and digital-to-analog converter included in the heterogeneous measurement and control board to obtain analog signals; the control unit is configured to control the operation of the quantum node based on the analog signals and generate control results, wherein the analog signals and control results are monitored by an oscilloscope; the analog-to-digital conversion unit is configured to convert the control results into digital signals using an analog-to-digital converter; and the second transmission unit is configured to transmit the digital signals to the supercomputing node based on the FPGA unit and corresponding daemon process included in the heterogeneous measurement and control board.

[0007] Thirdly, some embodiments of this disclosure provide an electronic device, including: one or more processors; and a storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any implementation of the first aspect above.

[0008] Fourthly, some embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method described in any of the implementations of the first aspect above.

[0009] The above-described embodiments of this disclosure have the following beneficial effects: they realize the interaction between supercomputing nodes and quantum nodes, especially making up for the shortcomings of the board in terms of distributed instruction adaptation, quantum signal waveforms and state monitoring, and effectively solving the distributed collaboration problem between the supercomputing node corresponding to the computer and the quantum node corresponding to the quantum computer in the distributed computing system under the classical heterogeneous fusion computing system. Attached Figure Description

[0010] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and elements are not necessarily drawn to scale.

[0011] Figure 1This is a flowchart of some embodiments of the interaction method between supercomputing nodes and quantum nodes for heterogeneous measurement and control boards according to the present disclosure; Figure 2 This is a schematic diagram of the structure of some embodiments of the interaction device for supercomputing nodes and quantum nodes oriented towards heterogeneous measurement and control boards according to the present disclosure; Figure 3 This is a schematic diagram of the structure of an electronic device suitable for implementing some embodiments of the present disclosure. Detailed Implementation

[0012] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0013] It should also be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0014] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0015] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0016] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0017] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0018] refer to Figure 1 The diagram illustrates flow 100 of some embodiments of an interaction method for supercomputing nodes and quantum nodes oriented towards heterogeneous measurement and control boards according to the present disclosure. This interaction method for supercomputing nodes and quantum nodes oriented towards heterogeneous measurement and control boards includes the following steps: Step 101: Listen for requests to the supercomputing node through the daemon process corresponding to the heterogeneous measurement and control board.

[0019] In some embodiments, the execution entity (e.g., a computing device) of the interaction method between supercomputing nodes and quantum nodes facing heterogeneous measurement and control boards can listen for requests to the supercomputing nodes through the daemon process corresponding to the heterogeneous measurement and control boards.

[0020] The heterogeneous measurement and control board is positioned between the supercomputing node and the quantum node. The supercomputing node is a distributed node corresponding to a classical computer. The quantum node is a distributed node corresponding to a quantum computer. The daemon process can be a process used for interaction between the supercomputing node and the quantum node.

[0021] In practice, heterogeneous measurement and control boards can continuously listen for requests from supercomputing nodes, which can effectively solve the problems of passive waiting and response delays associated with traditional architecture boards.

[0022] It should be noted that the aforementioned computing devices can be either hardware or software. When the computing device is hardware, it can be implemented as a distributed cluster consisting of multiple servers or terminal devices, or as a single server or a single terminal device. When the computing device is software, it can be installed on the hardware devices listed above. It can be implemented as, for example, multiple software programs or software modules used to provide distributed services, or as a single software program or software module. No specific limitations are made here.

[0023] Optionally, the daemon configures communication through the following steps: Step S1: Determine communication configuration information.

[0024] The communication configuration information is used for network environment initialization when the corresponding daemon process of the heterogeneous measurement and control board starts. This information includes buffer parameters, communication address parameters, and interaction port parameters. The corresponding code for the communication configuration information can be seen below: typedef struct { #define BUFFER_SIZE 1024 #define IP "192.168.1.10" #define PORT 5001 }; The communication configuration information is defined using a structure format. "BUFFER_SIZE" corresponds to the buffer parameter; for example, "1024" is a possible value. Expanding the buffer parameter to 1024 bytes allows for the concurrent transmission of instructions and batch status data from multiple nodes, thus preventing data congestion. "IP" corresponds to the communication address parameter; for example, "192.168.1.10" is a possible value. The communication address can use a routable network address within the local network, supporting communication between supercomputing nodes and quantum nodes deployed across devices, thus overcoming the limitations of single-device interaction. "PORT" corresponds to the interaction port parameter; for example, "5001" is a possible value. Setting a dedicated interaction port parameter ensures conflict-free communication between multiple daemons in the distributed architecture, guaranteeing the uniqueness of the distributed link. In particular, the buffer parameter, communication address parameter, and interaction port parameter are directly invoked when the daemon process starts, thereby initializing the network environment corresponding to the daemon process. For example, the fixed length of the data transmission and reception buffer can be set through the buffer parameter (BUFFER_SIZE), and the communication address parameter (IP) and interaction port parameter (PORT) and socket address can be bound to provide a basic network configuration foundation for subsequent network interaction, thereby solving the basic problems of "insufficient data transmission capacity, limited cross-device communication, and port conflicts" in distributed scenarios.

[0025] Step S2: Initialize the network interaction handle according to the communication configuration information to obtain the network interaction handle corresponding to the daemon process.

[0026] The handle configuration information corresponding to the network interaction handle includes: a first socket, a second socket group, a quantum node communication address group, and auxiliary parameters. The first socket is the socket corresponding to the supercomputing node that supports multiple concurrent connections. The second socket is the socket corresponding to the quantum node. The quantum node communication address is the network address corresponding to the quantum node. The auxiliary parameters are used for multi-node socket binding and socket connection management. The code corresponding to the handle configuration information can be shown below: int server_fd; int node_sockets[8]; struct sockaddr_in node_addrs[8]; int addrlen = sizeof(struct sockaddr_in); Among them, “server_fd” corresponds to the first socket, which is the receiving entry point for distributed instructions from multiple supercomputing nodes, thereby supporting concurrent connections of multiple supercomputing nodes. “node_sockets[8]” corresponds to the second socket group, which supports parallel interaction of 8 quantum nodes to meet the needs of distributed scale. “node_addrs[8]” corresponds to the quantum node communication address group, which is used to store the network address corresponding to each quantum node, so that subsequent instructions can be accurately distributed to the corresponding quantum node. “addrlen” corresponds to the auxiliary parameter, which is used for multi-node socket binding and socket connection management.

[0027] In practice, firstly, the communication address parameter (IP) and interaction port parameter (PORT) in step S1 are the core parameters for the creation and binding of the first socket (server_fd). When initializing the first socket (server_fd), it is necessary to bind the first socket (server_fd) to the network address corresponding to the communication address parameter (IP) and the port corresponding to the interaction port parameter (PORT) to ensure that the supercomputing node can find the instruction receiving entry point corresponding to the daemon process through the communication address parameter (IP) and interaction port parameter (PORT). Secondly, the quantum node communication address group (node_addrs[8]) stores the network address corresponding to each quantum node. The network address corresponding to the quantum node needs to be consistent with the communication address parameter (IP) and interaction port parameter (PORT) to establish a valid connection between the quantum node communication address group (node_addrs[8]) and the quantum node, and avoid communication failure due to network address or port mismatch. In addition, although the buffer parameter (BUFFER_SIZE) in step S1 does not directly participate in the initialization of the network interaction handle, it will provide a preset standard for the buffer capacity corresponding to the data transmitted through the network interaction handle in the future. In this way, connection management and precise instruction distribution are achieved for a hybrid distributed network consisting of multiple quantum nodes and multiple supercomputing nodes, thereby solving the problem of "multi-node identity confusion and instruction distribution chaos" at the physical link layer.

[0028] Optionally, the daemon process is configured with distributed collaboration configuration information, which includes: board node identifier, cross-node synchronization identifier, and task distribution identifier. The board node identifier is associated with the second socket in the second socket group; the cross-node synchronization identifier is updated based on the request response corresponding to the synchronization status request; and the task distribution identifier is bound to the quantum node task corresponding to the second socket in the second socket group. The code corresponding to the distributed collaboration configuration information can be shown below: int local_node_id; int cross_node_sync_flag; int task_distribution_flag; Among them, "local_node_id" corresponds to the board node identifier. "cross_node_sync_flag" corresponds to the cross-node synchronization flag. The cross-node synchronization flag can be represented by 0 or 1. When the cross-node synchronization flag is 0, it indicates that cross-node synchronization has not occurred. When the cross-node synchronization flag is 1, it indicates that cross-node synchronization has occurred. "task_distribution_flag" corresponds to the task distribution flag. The task distribution flag can be represented by 0 or 1. When the task distribution flag is 1, it indicates that cross-node task distribution has occurred. When the task distribution flag is 0, it indicates that cross-node task distribution has not occurred.

[0029] In practice, firstly, the board node identifier (local_node_id) is bound to the quantum node task corresponding to the quantum node communication address in the quantum node communication address group (node_addrs[8]). For example, if the IP address of the quantum node corresponding to the quantum node communication address ends with "10", then the corresponding board node identifier is 10. When the supercomputing node issues an instruction request, the daemon process can match the quantum node communication address (target address) in the quantum node communication address group (node_addrs[8]) according to the board node identifier (local_node_id), and then send the instruction accurately to the corresponding quantum node through the second socket group (node_sockets[8]) corresponding to the target address. Next, the task distribution flag (task_distribution_flag) is bound to the instruction sending action corresponding to the second socket group (node_sockets[8]). That is, when a task is sent to the corresponding quantum node through a certain second socket, the task distribution flag is immediately updated to 1 to avoid duplicate task issuance. The task distribution flag is 0 by default, indicating that no task has been issued.

[0030] Optionally, in a distributed scenario where multiple quantum nodes operate collaboratively, the daemon process sends synchronization status requests to multiple quantum nodes corresponding to the quantum node communication address group. The synchronization status request is used to determine whether multiple quantum nodes are ready. Specifically, when the request response to the synchronization status request indicates that multiple quantum nodes are ready, the cross-node synchronization identifier is updated to a first identifier value. When the request response to the synchronization status request indicates that there is an unread quantum node among the multiple quantum nodes, the cross-node synchronization identifier is updated to a second identifier value.

[0031] In practice, the cross-node synchronization flag (cross_node_sync_flag) can be represented by 0 or 1. The update of the cross-node synchronization flag (cross_node_sync_flag) depends on the quantum node communication address group (node_addrs[8]). That is, before performing multi-node collaborative operation, the daemon process will send a synchronization status query request to all quantum nodes through the quantum node communication address group (node_addrs[8]), and update the cross-node synchronization flag (cross_node_sync_flag) according to the query results returned by all quantum nodes. Specifically, when the query result indicates that all quantum nodes are renewed, the cross-node synchronization flag is 1. When the query result indicates that there are quantum nodes that are not renewed, the cross-node synchronization flag is 0. In this way, multi-node identity recognition, time synchronization and task distribution management are realized from the logical level.

[0032] Optionally, the daemon process is configured with data caching and interaction configuration information, which includes: a buffer, cross-node synchronization signals, and verification parameters. The buffer length is controlled by buffer parameters. The cross-node synchronization signals are used for synchronization confirmation across nodes in a distributed scenario. The verification parameters are used to determine whether data loss or truncation occurs during data reception by the quantum node. Data retransmission is triggered when data loss or truncation occurs. The code corresponding to the data caching and interaction configuration information can be shown below: char buffer[BUFFER_SIZE]; char sync_ack[6]; ssize_t valread; Among them, “buffer[BUFFER_SIZE]” corresponds to the buffer. “BUFFER_SIZE” represents the buffer parameter, which controls the buffer length of the corresponding buffer. By setting the buffer (buffer[BUFFER_SIZE]), the distributed instructions containing the target node ID (quantum node), multi-node batch state data, and full-link data can be temporarily stored. “sync_ack[6]” corresponds to the cross-node synchronization signal. By setting the cross-node synchronization signal (sync_ack[6]), the reliability of distributed collaboration can be guaranteed. “valread” corresponds to the verification parameter. The verification parameter (valread) is used to record the data length of the received data and verify the integrity of multi-node data transmission to avoid data loss or data truncation problems.

[0033] In practice, the buffer length corresponding to the buffer is controlled by the buffer parameter (BUFFER_SIZE) to ensure that the multi-node instructions and status data transmitted concurrently through the second socket group (node_sockets[8]) are not truncated due to insufficient buffer (cache) capacity. The cross-node synchronization signal (sync_ack[6]) stores confirmation signals such as "SYNC_OK" and "SYNC_ERR", and is sent back to the node that initiated the synchronization request through the second socket group (node_sockets[8]) to form a "request-confirmation" closed loop. The verification parameter (valread) records the actual length of the data received through the second socket group (node_sockets[8]), which needs to be compared with the buffer parameter (BUFFER_SIZE). If the actual length is less than the buffer parameter (BUFFER_SIZE), it is determined that there is data, packet loss or data truncation, thereby triggering data retransmission. In this way, the temporary storage, verification and confirmation of distributed instructions and status data are realized, solving the problem of "multi-node data congestion and unreliable transmission".

[0034] Optionally, the daemon process is configured with quantum node parameter information, which includes: a multi-node qubit parameter cache, a single-qubit waveform parameter carrier, and the total number of qubits in the distributed network. The multi-node qubit parameter cache stores the quantum waveform parameters corresponding to multiple quantum nodes in the distributed scenario, the single-qubit waveform parameter carrier stores the quantum waveform parameters corresponding to a single quantum node, and the total number of qubits in the distributed network is the total number of qubits corresponding to multiple quantum nodes in the distributed scenario. The code corresponding to the quantum node parameter information can be shown below: typedef struct{ double** multi_node_qubit; double* wave_arry; int total_qubit_count; }GuardianContext; Among them, "multi_node_qubit" corresponds to the multi-node qubit parameter cache, used to store the quantum waveform parameters corresponding to the quantum nodes in multiple quantum nodes. "wave_arry" corresponds to the single-qubit waveform parameter carrier, which is used to carry the waveform parameters of the qubit corresponding to a single quantum node, in order to adapt to the precise operational requirements of quantum hardware. "total_qubit_count" corresponds to the total number of qubits in the distributed network, which represents the total number of qubits corresponding to multiple quantum nodes in the distributed scenario, providing data basis for global scheduling on the supercomputing node side. "GuardianContext" corresponds to the quantum node parameter information.

[0035] In practice, the first dimension of the multi-node qubit parameter cache (multi_node_qubit) is preset to 8, so as to match the number of second sockets corresponding to the second socket group (node_sockets[8]). Each dimension of the multi-node qubit parameter cache (multi_node_qubit) corresponds to the quantum waveform parameters of a quantum node. When it is necessary to update the quantum waveform parameters of a certain quantum node (i), the quantum waveform parameters corresponding to the i-th quantum node can be found directly through multi_node_qubit[i], and then sent to the quantum node through node_sockets[i]. The single-qubit waveform parameter carrier (wave_arry) stores the quantum waveform parameters (e.g., amplitude, frequency, etc.) corresponding to a single quantum node. It is adapted through the buffer parameter (BUFFER_SIZE) to ensure that it can be completely stored in the buffer (buffer[BUFFER_SIZE]) and transmitted through the second socket group (node_sockets[8]). The total number of qubits in the distributed network (total_qubit_count) needs to be counted based on the local node ID to distinguish each quantum node. After the count is completed, it is fed back to the supercomputing node according to the second socket group (node_sockets[8]), so as to provide data support for the supercomputing node to perform sharding tasks based on the total number of qubits in the distributed network (total_qubit_count). This achieves full-link connectivity of communication configuration and quantum communication management. By combining communication configuration information, distributed collaborative configuration information, data caching and interaction configuration information, and quantum node parameter information, a comprehensive construction is achieved from communication standard definition, physical communication link construction, communication identity recognition, timing synchronization, communication guarantee based on caching mechanism, quantum node side communication and parameter management.

[0036] Step 102: In response to the daemon listening to the instruction request initiated by the supercomputing node, the daemon receives the instruction request initiated by the supercomputing node, and performs request parsing and adaptation on the instruction request to obtain the adapted instruction request.

[0037] In some embodiments, the aforementioned execution entity may respond to the daemon process listening for the instruction request initiated by the supercomputing node, receive the instruction request initiated by the supercomputing node, and parse and adapt the instruction request to obtain the adapted instruction request.

[0038] The instruction request can be a control request initiated by a supercomputing node and directed at a quantum node. After adaptation, the instruction request can represent operational instructions recognizable by both the quantum node and the heterogeneous measurement and control board.

[0039] In practice, supercomputing nodes can initiate command requests through the process corresponding to MPI (Message Passing Interface). After the daemon process listens for the command request, it will parse and adapt the command request to obtain the adapted command request.

[0040] In some optional implementations of certain embodiments, the execution entity performs request parsing and adaptation on the instruction request to obtain an adapted instruction request, including: Step S1: The command request is parsed and adapted by the request parsing and adaptation module corresponding to the daemon process to obtain the adapted command request.

[0041] The request parsing and adaptation module is configured with a request parsing and adaptation structure, which includes: first instruction information, second instruction information, instruction type identifier, and parsing result identifier. The first instruction information stores the instruction request initiated by the supercomputing node. The second instruction information stores the adapted instruction request. The storage length of the first and second instruction information is controlled by the buffer parameters included in the communication configuration information. The instruction type identifier indicates the instruction type of the adapted instruction request. The parsing result identifier indicates whether the instruction request was parsed successfully. Setting the instruction type identifier distinguishes different instruction operations. The parsing result identifier can be represented by 0 or 1. When the parsing result identifier is 1, it indicates that the instruction request was parsed successfully; when the parsing result identifier is 0, it indicates that the instruction request failed to be parsed. By setting the request parsing and adaptation structure, the "translation" of instruction requests received by the daemon process and sent by the supercomputing node can be achieved, and the instruction requests can be parsed into an instruction format recognizable by heterogeneous measurement and control boards, facilitating accurate instruction distribution across multiple nodes in a distributed architecture. Specifically, the code corresponding to the request parsing and adaptation structure can be shown below: typedef struct { char classic_instruction

[1024] ; char adapted_instruction

[1024] ; int instruction_type; int parse_result; InstructionParseAdapt; Among them, "classic_instruction

[1024] " corresponds to the first instruction information. "char adapted_instruction

[1024] " corresponds to the second instruction information. "instruction_type" corresponds to the instruction type identifier. "parse_result" corresponds to the parsing result identifier. "InstructionParseAdapt" corresponds to the parsing and adaptation structure. "1024" in "classic_instruction

[1024] " and "adapted_instruction

[1024] " corresponds to the buffer parameter, which ensures the received instruction request.

[0042] In practice, the corresponding request can be parsed according to the instruction type of the instruction request to obtain the adapted instruction request. In the specific instruction parsing process, the core relies on the local board representation (local_node_id) to match the "target_node_id" in the instruction request to determine the node identity of the target node. And through the second socket group (node_sockets[8]) to determine whether the target node is online (node_sockets[i]!=-1 means the connection is normal), the node is determined to be valid only when both judgment conditions are met. On this basis, when "SYNC" (synchronization instruction) is parsed, the cross-node synchronization flag (cross_node_sync_flag) is directly modified to 0 to initialize the flag state of the cross-node synchronization flag and prepare for subsequent timing verification. This solves the problem of "chaotic instruction distribution among multiple supercomputing nodes", ensures that the instruction request can accurately reach the target quantum node, and provides a logical trigger point for cross-node synchronization operation.

[0043] Step 103: Transmit the adapted command request to the heterogeneous measurement and control board through the daemon process and PCIe bus.

[0044] In some embodiments, the aforementioned execution entity can transmit the adapted instruction request to the heterogeneous measurement and control board through the daemon process and the PCIe bus.

[0045] In practice, the daemon process transmits the adapted command requests to the heterogeneous measurement and control board via the PCIe bus.

[0046] Step 104: The adapted command request is processed by the FPGA unit and digital-to-analog converter included in the heterogeneous measurement and control board to obtain the analog signal.

[0047] In some embodiments, the aforementioned execution entity can process the adapted instruction request through the FPGA (Field Programmable Gate Array) unit and digital-to-analog converter (DAC) included in the heterogeneous measurement and control board to obtain an analog signal.

[0048] The digital-to-analog converter is used to convert the adapted digital signal into the corresponding analog signal.

[0049] Optionally, the adapted instruction is processed by the quantum instruction waveform mapping module to obtain an analog signal. The quantum instruction waveform mapping module is configured with a corresponding quantum instruction waveform mapping structure, which includes: the adapted instruction, waveform data, waveform data length, and mapping result identifier. A portion of the code corresponding to the quantum instruction waveform mapping structure is shown below: typedef struct { char adapted_instruction

[1024] ; double waveform

[1024] ; int waveform_length; int map_result; } QuantumInstructionWaveformMap; Among them, “adapted_instruction

[1024] ” corresponds to the adapted instruction. “waveform

[1024] ” corresponds to the waveform data. “waveform_length” corresponds to the waveform length. “map_result” corresponds to the mapping result identifier. “QuantumInstructionWaveformMap” corresponds to the quantum instruction waveform mapping structure.

[0050] In practice, the code corresponding to the process of converting the adapted instructions into analog signals is shown below: int map_instruction_to_waveform(QuantumInstructionWaveformMap *qiwm){ if (strstr(qiwm->adapted_instruction, "ADAPT_CONFIG")) { for (int i = 0; i<100; i++) { qiwm->waveform[i] = sin(i *0.1); } qiwm->waveform_length = 100; qiwm->map_result = 0; } else { qiwm->map_result = -1; } return qiwm->map_result; }

[0051] The `map_instruction_to_waveform()` function is the core function of the quantum instruction waveform mapping module. It receives the adapted instruction, identifies "ADAPT_CONFIG" type instructions through string matching, and generates relevant waveform data stored in `waveform

[1024] `. When the mapping match is successful, the mapping result identifier (`map_result`) is updated to 1; otherwise, it is updated to 0. Simultaneously, the waveform length corresponding to the waveform data is recorded using `waveform_length`. This achieves the conversion from instruction to hardware-executable waveform.

[0052] In addition, in the synchronous verification of waveforms of multiple quantum nodes, the second socket group (node_sockets[8]) is used to filter online quantum nodes (node_sockets[i]!=-1 means the connection is normal). On this basis, the cross-node synchronization flag (cross_node_sync_flag) is used to determine whether the online quantum nodes are synchronized (cross-node synchronization flag (cross_node_sync_flag=1), and the verification loop is only exited when all online quantum nodes are ready). Waveform data (analog signal) is sent to multiple online quantum nodes through the second socket group (node_sockets[8]) to achieve parallel control of 8 quantum nodes and avoid the efficiency bottleneck of traditional node-by-node distribution. By designing the request parsing and adaptation module and the quantum instruction waveform mapping module, the limitation of single node is broken, the corresponding structure of the connection guardian is implemented, the instruction distribution on the supercomputing node side and the closed loop of synchronous operation on the quantum node side are realized, thus providing support for distributed scenarios.

[0053] Step 105: Control the operation of the quantum node according to the analog signal and generate the control result.

[0054] In some embodiments, the aforementioned execution entity can control the operation of the quantum node and generate control results based on analog signals.

[0055] The analog signals and control results are monitored using an oscilloscope.

[0056] In practice, the aforementioned executing entity can send analog signals to the quantum node to control the quantum node to execute the instructions corresponding to the analog signals and obtain the control result.

[0057] Step 106: The control result is converted from analog to digital using an analog-to-digital converter to obtain a digital signal.

[0058] In some embodiments, the aforementioned execution entity can use an analog-to-digital converter (ADC) to convert the control result into a digital signal.

[0059] In practice, since the control result is generated by the quantum node after executing the adapted instructions, it is in analog signal format. Therefore, it needs to be converted into a digital signal by an analog-to-digital converter.

[0060] Step 107: Based on the FPGA units and corresponding daemons included in the heterogeneous measurement and control board, transmit the digital signals to the supercomputing node.

[0061] In some embodiments, the aforementioned execution entity may transmit digital signals to the supercomputing node based on the FPGA unit and corresponding daemon process included in the heterogeneous measurement and control board.

[0062] The above-described embodiments of this disclosure have the following beneficial effects: they realize the interaction between supercomputing nodes and quantum nodes, especially making up for the shortcomings of the board in terms of distributed instruction adaptation, quantum signal waveforms and state monitoring, and effectively solving the distributed collaboration problem between the supercomputing node corresponding to the computer and the quantum node corresponding to the quantum computer in the distributed computing system under the classical heterogeneous fusion computing system.

[0063] Further reference Figure 2 As an implementation of the methods shown in the above figures, this disclosure provides some embodiments of an interaction device for supercomputing nodes and quantum nodes oriented towards heterogeneous measurement and control boards. These device embodiments are similar to... Figure 1 Corresponding to the method embodiments shown, this interaction device for supercomputing nodes and quantum nodes oriented towards heterogeneous measurement and control boards can be specifically applied to various electronic devices.

[0064] like Figure 2 As shown, some embodiments of the interaction device 200 for supercomputing nodes and quantum nodes with heterogeneous measurement and control boards include: a request listening unit 201, a receiving unit 202, a first transmission unit 203, a request processing unit 204, a control unit 205, an analog-to-digital conversion unit 206, and a second transmission unit 207. The request listening unit 201 is configured to listen for requests to the supercomputing node through a daemon process corresponding to the heterogeneous measurement and control board; the receiving unit 202 is configured to receive the instruction request initiated by the supercomputing node in response to the daemon process listening for an instruction request initiated by the supercomputing node, and to parse and adapt the instruction request to obtain an adapted instruction request; the first transmission unit 203 is configured to listen for requests to the supercomputing node through a .... The process and PCIe bus are used to transmit the adapted instruction request to the heterogeneous measurement and control board; the request processing unit 204 is configured to process the instruction request through the FPGA unit and digital-to-analog converter included in the heterogeneous measurement and control board to obtain an analog signal; the control unit 205 is configured to control the operation of the quantum node according to the analog signal and generate control results, wherein the analog signal and control results are monitored by an oscilloscope; the analog-to-digital conversion unit 206 is configured to convert the control result into an analog signal through the analog-to-digital converter to obtain a digital signal; the second transmission unit 207 is configured to transmit the digital signal to the supercomputing node according to the FPGA unit and corresponding daemon included in the heterogeneous measurement and control board.

[0065] It is understandable that the units and references described in the interaction device 200 for supercomputing nodes and quantum nodes oriented towards heterogeneous measurement and control boards... Figure 1 The steps in the described method correspond accordingly. Therefore, the operations, features, and beneficial effects described above for the method are also applicable to the interaction device 200 for supercomputing nodes and quantum nodes oriented towards heterogeneous measurement and control boards, and the units contained therein, and will not be repeated here.

[0066] The following is for reference. Figure 3 It shows a schematic diagram of the structure of an electronic device (e.g., a computing device) 300 suitable for implementing some embodiments of the present disclosure. Figure 3 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments of this disclosure.

[0067] like Figure 3As shown, the electronic device 300 may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 301, which can perform various appropriate actions and processes according to a program stored in a read-only memory 302 or a program loaded from a storage device 308 into a random access memory 303. The random access memory 303 also stores various programs and data required for the operation of the electronic device 300. The processing unit 301, the read-only memory 302, and the random access memory 303 are interconnected via a bus 304. An input / output interface 305 is also connected to the bus 304.

[0068] Typically, the following devices can be connected to the input / output interface 303: input devices 306 including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 307 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 308 including, for example, magnetic tape, hard disk, etc.; and communication devices 309. Communication device 309 allows electronic device 300 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 3 An electronic device 300 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively. Figure 3 Each box shown can represent a device or multiple devices as needed.

[0069] In particular, according to some embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, some embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 309, or installed from a storage device 308, or installed from a read-only memory 302. When the computer program is executed by the processing device 301, it performs the functions defined in the methods of some embodiments of this disclosure.

[0070] It should be noted that, in some embodiments of this disclosure, the computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In some embodiments of this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In some embodiments of this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0071] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol), and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0072] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently without being assembled into the electronic device. The aforementioned computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to: listen for requests from the supercomputing node through the daemon process corresponding to the heterogeneous measurement and control board; in response to the daemon process listening for an instruction request initiated by the supercomputing node, receive the instruction request initiated by the supercomputing node, and parse and adapt the instruction request to obtain an adapted instruction request; transmit the adapted instruction request to the heterogeneous measurement and control board through the daemon process and the PCIe bus; process the adapted instruction request through the FPGA unit and digital-to-analog converter included in the heterogeneous measurement and control board to obtain an analog signal; control the operation of the quantum node according to the analog signal and generate control results, wherein the analog signal and control results are monitored by an oscilloscope; convert the control results to digital signals through an analog-to-digital converter to obtain digital signals; and transmit the digital signals to the supercomputing node according to the FPGA unit and the corresponding daemon process included in the heterogeneous measurement and control board.

[0073] Computer program code for performing operations of some embodiments of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0074] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0075] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0076] The above description is merely a selection of preferred embodiments of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this disclosure.

Claims

1. A method for interaction between supercomputing nodes and quantum nodes for heterogeneous measurement and control boards, characterized in that, include: The supercomputing node is monitored by the daemon process corresponding to the heterogeneous measurement and control board. In response to the daemon listening to the instruction request initiated by the supercomputing node, the daemon receives the instruction request initiated by the supercomputing node, and performs request parsing and adaptation on the instruction request to obtain the adapted instruction request. The adapted command requests are transmitted to the heterogeneous measurement and control board through the daemon process and PCIe bus; The FPGA unit and digital-to-analog converter included in the heterogeneous measurement and control board are used to process the adapted command requests and obtain analog signals. The operation of the quantum node is controlled by analog signals, and control results are generated. The analog signals and control results are monitored by an oscilloscope. The control result is converted from analog to digital by an analog-to-digital converter to obtain a digital signal; Based on the FPGA units and corresponding daemons included in the heterogeneous measurement and control board, digital signals are transmitted to the supercomputing node.

2. The interaction method between supercomputing nodes and quantum nodes for heterogeneous measurement and control boards according to claim 1, characterized in that, The daemon process configures communication through the following steps: Determine the communication configuration information, which is used for network environment initialization when the corresponding daemon process of the heterogeneous measurement and control board starts. The communication configuration information includes: buffer parameters, communication address parameters, and interaction port parameters. The network interaction handle is initialized based on the communication configuration information to obtain the network interaction handle corresponding to the daemon process. The handle configuration information corresponding to the network interaction handle includes: a first socket, a second socket group, a quantum node communication address group, and auxiliary parameters. The first socket is the socket corresponding to the supercomputing node that supports multiple concurrent connections. The second socket is the socket corresponding to the quantum node. The quantum node communication address is the network address corresponding to the quantum node. The auxiliary parameters are used for multi-node socket binding and socket connection management.

3. The interaction method between supercomputing nodes and quantum nodes for heterogeneous measurement and control boards according to claim 2, characterized in that, The daemon process is configured with distributed collaborative configuration information, which includes: board node identifier, cross-node synchronization identifier, and task distribution identifier. The board node identifier is associated with the second socket in the second socket group. The cross-node synchronization identifier is updated according to the request response corresponding to the synchronization status request. The task distribution identifier is bound to the quantum node task corresponding to the second socket in the second socket group.

4. The interaction method between supercomputing nodes and quantum nodes for heterogeneous measurement and control boards according to claim 3, characterized in that, In a distributed scenario where multiple quantum nodes operate collaboratively, the daemon sends synchronization status requests to multiple quantum nodes corresponding to the quantum node communication address group. The synchronization status request is used to determine whether multiple quantum nodes are ready. Specifically, when the request response to the synchronization status request indicates that multiple quantum nodes are ready, the cross-node synchronization flag is updated to the first flag value. When the request response to the synchronization status request indicates that there are unready quantum nodes among the multiple quantum nodes, the cross-node synchronization flag is updated to the second flag value.

5. The interaction method between supercomputing nodes and quantum nodes for heterogeneous measurement and control boards according to claim 4, characterized in that, The daemon process is configured with data caching and interaction configuration information, which includes: buffer, cross-node synchronization signal and verification parameters. The buffer length is controlled by the buffer parameter. The cross-node synchronization signal is used to confirm synchronization across nodes in a distributed scenario. The verification parameter is used to determine whether there is data loss or data truncation during the quantum node's data reception process. When data loss or data truncation occurs, data retransmission is triggered.

6. The interaction method between supercomputing nodes and quantum nodes for heterogeneous measurement and control boards according to claim 5, characterized in that, The daemon process is configured with quantum node parameter information, which includes: multi-node quantum bit parameter cache, single quantum bit waveform parameter carrier, and the total number of quantum bits in the distributed network. The multi-node quantum bit parameter cache is used to store the quantum waveform parameters corresponding to multiple quantum nodes in the distributed scenario, the single quantum bit waveform parameter carrier is used to store the quantum waveform parameters corresponding to a single quantum node, and the total number of quantum bits in the distributed network is the total number of quantum bits corresponding to multiple quantum nodes in the distributed scenario.

7. The interaction method between supercomputing nodes and quantum nodes for heterogeneous measurement and control boards according to claim 6, characterized in that, The process of parsing and adapting the instruction request to obtain the adapted instruction request includes: The request parsing and adaptation module corresponding to the daemon process parses and adapts the instruction request to obtain the adapted instruction request. The request parsing and adaptation module is configured with a request parsing and adaptation structure, which includes: first instruction information, second instruction information, instruction type identifier, and parsing result identifier. The first instruction information is used to store the instruction request initiated by the supercomputing node, the second instruction information is used to store the adapted instruction request, the instruction type identifier represents the instruction type of the adapted instruction request, and the parsing result identifier represents whether the instruction request was parsed successfully.

8. An interaction device for supercomputing nodes and quantum nodes oriented towards heterogeneous measurement and control boards, characterized in that, include: The request listening unit is configured to listen for requests to the supercomputing node through the daemon process corresponding to the heterogeneous measurement and control board. The receiving unit is configured to respond to the daemon process listening for instruction requests initiated by the supercomputing node, receive the instruction requests initiated by the supercomputing node, and parse and adapt the instruction requests to obtain the adapted instruction requests. The first transmission unit is configured to transmit the adapted command request to the heterogeneous measurement and control board via the daemon process and the PCIe bus. The request processing unit is configured to process the instruction request through the FPGA unit and digital-to-analog converter included in the heterogeneous measurement and control board to obtain an analog signal; The control unit is configured to control the operation of the quantum node based on analog signals and to generate control results, wherein the analog signals and control results are monitored by an oscilloscope; The analog-to-digital conversion unit is configured to convert the control result into a digital signal using an analog-to-digital converter. The second transmission unit is configured to transmit digital signals to the supercomputing node based on the FPGA unit and corresponding daemon process included in the heterogeneous measurement and control board.

9. An electronic device, characterized in that, include: One or more processors; A storage device on which one or more programs are stored; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1 to 7.

10. A computer-readable medium, characterized in that, It stores a computer program thereon, wherein the computer program, when executed by a processor, implements the method as described in any one of claims 1 to 7.

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