Low-power-consumption high-swing equalization circuit applied to high-speed interface transmitting end

Abstract

The invention discloses a low-power-consumption and high-swing equalization circuit applied to a high-speed interface transmitting end, which adopts a three-stage series architecture of feed-forward signal preprocessing-D latch-multi-chip parallel weight distribution, and realizes accurate processing of signals and channel loss compensation through adaptation of process characteristics and circuit structures. And requirements of transmission stability and low power consumption are considered. The feed-forward signal preprocessing module realizes hierarchical delay of input data by adjusting the stage number of a D latch; and a stable time sequence basis is provided for subsequent pre-emphasis compensation. The D latch adopts a customized transistor level structure, so that stable data transmission under high and low levels is ensured; meanwhile, an MOS transistor zero setting unit driven by a Pwron signal is integrated, and low-power-consumption control is achieved from the transistor level. The multi-chip parallel weight distribution module is composed of 40 parallel sub-circuits with consistent structures, and each sub-circuit adopts a CMOS differential driving architecture; by configuring the proportion of the number of sub-circuits driven by different signal paths, the weight is finely regulated and controlled.

Description

Technical Field

[0001] This invention relates to the field of high-speed serial communication technology, specifically to high-speed data transmission that achieves channel loss compensation, and particularly to a low-power, high-swing equalization circuit applied to the transmitting end of a high-speed interface. Background Technology

[0002] As serial communication interfaces evolve towards higher data rates, mainstream protocols such as PCIe 4.0 have increased data transmission rates to 16Gbps to meet the ever-growing demand for data throughput. However, at high speeds, non-ideal characteristics of the transmission channel, such as the skin effect, dielectric loss, and inter-symbol interference, are significantly aggravated, leading to severe degradation of signal integrity and becoming a core bottleneck restricting reliable transmission. Feedforward equalizers (FFEs), as a key technology for solving this problem, have been widely used in SerDes systems.

[0003] Existing feedforward equalization circuits have several limitations: Firstly, equalization circuits using traditional processes struggle to balance high-speed transmission with low power consumption, while designs employing advanced FinFET technology fail to fully leverage its high drive and low leakage characteristics, resulting in a mismatch between circuit performance and process potential. Secondly, feedforward signal preprocessing modules often employ single-delay paths or fixed-stage designs, leading to insufficient timing difference control precision and a tendency to cause signal level mismatch. Weight allocation modules typically use a small number of taps, resulting in coarse-grained weight control that cannot flexibly adapt to different channel loss scenarios. Furthermore, latch circuits, as the core of timing control, suffer from problems such as large transmission delays, weak noise immunity, and high standby power consumption in traditional structures, affecting the overall signal processing stability and energy efficiency of the equalization circuit. Therefore, this invention proposes a novel equalization circuit. This circuit combines a wide output swing with excellent low-voltage operating characteristics while ensuring excellent power consumption. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to address the deficiencies mentioned in the background art by providing a low-power, high-swing equalization circuit for use in high-speed interface transmitters.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0006] A low-power, high-swing equalization circuit for use in high-speed interface transmitters includes a feedforward signal preprocessing module and a weight allocation module.

[0007] The feedforward signal preprocessing module includes first to fifth D latches, first to seventh buffers, and first to second switches;

[0008] The first to fifth D latches have the same structure, each including first to eighth transistors and first to second inverters. The source of the first transistor is connected to an external power supply VDD, its gate is connected to an external control signal Pwr_on, and its drain is connected to the input of the first inverter, the input of the second inverter, the drain of the third transistor, the drain of the fourth transistor, the source of the seventh transistor, and the source of the eighth transistor, respectively. The output of the first inverter is connected to the gate of the second transistor and the gate of the fifth transistor, respectively. The source of the second transistor is connected to an external power supply VDD, and its drain is connected to the source of the third transistor. The third transistor's... The gate of the fourth transistor is connected to the inverted clock signal ck_m; the gate of the fifth transistor is connected to the positive clock signal ck_p, and its source is connected to the drain of the fifth transistor; the source of the fifth transistor is connected to the drain of the sixth transistor; the gate of the sixth transistor is connected to the external control signal Pwr_on, and its source is grounded; the gate of the seventh transistor is connected to the positive clock signal ck_p, and its drain is connected to the drain of the eighth transistor to serve as the input terminal of the D latch; the gate of the eighth transistor is connected to the inverted clock signal ck_m; the output of the second inverter serves as the output terminal of the D latch; the external control signal Pwr_on is used to control the power supply path of the D latch to be turned on and off;

[0009] The input terminal of the first D latch serves as the input terminal of the feedforward signal preprocessing module and also as the input terminal of the equalization circuit; the output terminal of the first D latch, the second D latch, the first buffer, and the input terminal of the third D latch are connected in sequence.

[0010] The output of the third D latch is connected to the input of the second buffer and the input of the fourth D latch, respectively.

[0011] The output of the second buffer, the third buffer, and one end of the first switch are connected in sequence.

[0012] The output of the fourth D latch is connected to the input of the fourth buffer and the input of the fifth D latch, respectively.

[0013] The output of the fourth buffer is connected to the input of the fifth buffer;

[0014] The output of the fifth D latch, the sixth buffer, the seventh buffer, and one end of the second switch are connected in sequence;

[0015] The other end of the first switch serves as the first output of the feedforward signal preprocessing module, the output of the fifth D latch serves as the second output of the feedforward signal preprocessing module, and the other end of the second switch serves as the third output of the feedforward signal preprocessing module.

[0016] The weight allocation module contains 40 weight allocation units;

[0017] The weighting unit includes a first inverter and nine to sixteenth transistors;

[0018] The source of the ninth transistor is connected to the external power supply VDD, the drain is connected to the source of the tenth transistor, and the gate is connected to the external signal Sel_eq_n.

[0019] The drain of the tenth transistor is connected to the drain of the eleventh transistor, the drain of the fourteenth transistor, the drain of the fifteenth transistor, and the input terminal of the third inverter. The gate of the tenth transistor is connected to the gate of the eleventh transistor and serves as the first input terminal of the weighting unit.

[0020] The source of the eleventh transistor is connected to the drain of the twelfth transistor;

[0021] The gate of the twelfth transistor is connected to the external signal Sel_eq, and the source is grounded;

[0022] The source of the thirteenth transistor is connected to the external power supply VDD, the drain is connected to the source of the fourteenth transistor, and the gate is connected to the external signal Sel_main_n.

[0023] The gates of the fourteenth transistor and the fifteenth transistor are connected to form the second input terminal of the weighting unit;

[0024] The source of the fifteenth transistor is connected to the drain of the sixteenth transistor;

[0025] The gate of the sixteenth transistor is connected to the external signal Sel_main, and the source is grounded;

[0026] The external signal Sel_eq is an inverted signal of Sel_eq_n, which is used to control the conduction of the ninth transistor and the twelfth transistor; the external signal Sel_main is an inverted signal of Sel_main_n, which is used to control the conduction of the sixteenth transistor and the thirteenth transistor.

[0027] The output of the third inverter serves as the output of the weight allocation unit.

[0028] The first input terminals of the 40 weight allocation units are connected in parallel and then connected to the first and third output terminals of the feedforward signal preprocessing module, respectively. The second input terminals of the 40 weight allocation units are connected in parallel and then connected to the second output terminal of the feedforward signal preprocessing module. The output terminals of the 40 weight allocation units are connected in parallel and then used as the output terminals of the equalization circuit.

[0029] As a further optimization of the low-power, high-swing equalization circuit applied to the high-speed interface transmitter of the present invention, the first to eighth transistors all adopt FinFET.

[0030] As a further optimization of the low-power, high-swing equalization circuit applied to the high-speed interface transmitter of the present invention, the first to eighth transistors are all MOS transistors.

[0031] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:

[0032] 1. A timing coordination architecture of "dual latch-hierarchical buffer" for high-speed multipath signals. Existing high-speed multipath distribution circuits rely on multi-phase clocks (requiring additional PLLs), resulting in low timing control accuracy and high circuit complexity. Dual D latch pre-synchronization unit: U3+U4 dual D latches are connected in series and are strictly synchronized with the system clock. Hierarchical D latch delay control: Through the difference in the number of levels, continuous timing difference control of Data_pre, Data_main, and Data_post is achieved (without additional PLLs).

[0033] 2. The D latch circuit integrates a power control unit, which drives the MOS transistor to cut off the standby power path through the Pwr_on signal. It combines the symmetrical data input unit and cross-coupled register unit designed with FinFET process characteristics to balance data transmission stability, timing control accuracy and low power consumption requirements.

[0034] 3. The weight allocation unit adopts a CMOS differential drive architecture, which realizes flexible selection of the equalization path and the main path through independent control signals. The 40-chip parallel configuration scheme greatly improves the granularity of weight control and can adapt to different channel loss scenarios. Compared with the traditional tapped structure, the compensation accuracy and flexibility are significantly improved.

[0035] 4. The overall circuit is implemented based on 16nm FinFET process, and the structure and process characteristics of each module are deeply adapted to fully leverage the advantages of FinFET devices in high drive and low leakage, so as to achieve synergistic optimization of signal processing performance and power consumption at high speed. Attached Figure Description

[0036] Figure 1 This is a circuit diagram of the present invention;

[0037] Figure 2 This is a circuit diagram of the feedforward signal preprocessing module in this invention;

[0038] Figure 3 This is a circuit diagram of the first D latch in this invention;

[0039] Figure 4 This is a circuit diagram of the weight allocation unit in this invention. Detailed Implementation

[0040] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings:

[0041] This invention can be implemented in many different forms and should not be considered limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully express the scope of the invention to those skilled in the art. In the drawings, components are enlarged for clarity.

[0042] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, and / or parts, these elements, components, and / or parts are not limited by these terms. These terms are merely used to distinguish elements, components, and / or parts from one another. Therefore, the first element, component, and / or part discussed below may be a second element, component, or part without departing from the teachings of this invention.

[0043] like Figure 1 As shown, this invention discloses a low-power, high-swing equalization circuit for use in high-speed interface transmitters, comprising a feedforward signal preprocessing unit D1 and multiple parallel weight allocation units D2. The architecture is implemented using a 16nm FinFET process.

[0044] The input terminal of the feedforward signal preprocessing unit D1 receives input data DATA, and the output terminal generates three signals with timing differences: Data_pre, Data_main, and Data_post.

[0045] The multi-chip parallel weight allocation unit D2 is composed of 40 identical sub-circuits in parallel. Its input terminal receives the three signals Data_pre, Data_main, and Data_post respectively, and is configured with Sel_eq, Sel_eq_n, Sel_main, and Sel_main_n control signal ports. The signal path of the corresponding sub-circuit is selected through the control signals, and the processed signal is finally output through the output terminal.

[0046] The signals involved can be divided into four main categories: functional path signals (Data_pre / main / post), control strobe signals (Sel start signals), power management signals (Pwr_on), and timing synchronization signals (ck_p / ck_m). Based on the circuit architecture logic and high-speed interface design principles, the meaning and function of each signal are as follows:

[0047] (1) Functional path signals: Data_pre, Data_main, Data_post

[0048] These three types of signals are the core outputs of the feedforward signal preprocessing unit (D1), providing the subsequent weight allocation module with "multipath signals with precise timing differences" to achieve "pre-emphasis compensation" and offset high-frequency channel losses.

[0049] Data_pre is the output signal of the short-delay path, generated by a "few-stage D latch + buffer" in the feedforward preprocessing unit (specifically, a three-stage D latch U1-U3 + a three-stage buffer BUF1-BUF3). It corresponds to the high-frequency components of the signal and its function is to enhance the high-frequency signal strength in subsequent weight allocation.

[0050] Data_main is the output signal of the medium-delay path, generated by "medium-level D latches + buffers" (U1-U4 four-level D latches + BUF1-BUF5 five-level buffers). Its timing is in the middle, corresponding to the fundamental frequency component of the signal (core data component), and it is the main force to ensure the "high swing" output of the signal, determining the basic transmission quality of the equalization circuit.

[0051] Data_post is the output signal of the long-delay path, generated by "the most numerous D latches + buffers" (U1-U5 five-stage D latches + BUF1-BUF7 seven-stage buffers). It has the latest timing and also corresponds to the high-frequency components of the signal (in coordination with Data_pre). Through the "pre- and post-delay pairing" with Data_pre, it achieves bidirectional compensation for high-frequency channel losses.

[0052] (2) Control gating signals: Sel_eq, Sel_eq_n, Sel_main, Sel_main_n

[0053] When Sel_eq (Equalization Select) is active high, it selects the "equalization path" (corresponding to the Data_pre / Data_post high-frequency signal channel) in the weight allocation unit, allowing high-frequency components to participate in signal superposition; when it is low, it closes the path.

[0054] Sel_eq_n is the inverted signal of Sel_eq. Together with Sel_eq, they form a "differential control" to avoid misjudgment caused by noise interference in the single-ended signal, ensuring stable switching of the equalization path at high speeds.

[0055] When Sel_main is active high, it selects the "main path" (corresponding to the Data_main basic signal channel) in the sub-circuit, allowing the basic frequency components to participate in signal superposition; when it is active low, it closes the path. Sel_main_n is the inverted signal of Sel_main, which works with Sel_main to implement differential control of the main path, ensuring the stability of the basic component transmission and avoiding swing attenuation caused by jitter in single-ended signals.

[0056] The coordination logic for four types of signals: By configuring the level combination of "Sel_eq / Sel_eq_n" and "Sel_main / Sel_main_n", the ratio of "equalization path sub-circuit number" and "main path sub-circuit number" in the 40-chip sub-circuit can be adjusted. If the channel high-frequency loss is large, the number of equalization path gates is increased; if the channel loss is small, the number of main path gates is increased, flexibly adapting to different application scenarios.

[0057] (3) Power management signal: Pwr_on

[0058] Pwr_on is the enable control signal for the D latch. Its core function is to cut off the power supply path in standby mode. Combined with the low leakage characteristics of the 16nm FinFET process, it significantly reduces static power consumption.

[0059] When Pwr_on is high, the MOS transistors (M1, M6) in the D latch are turned on, the core circuit (inverter register unit, data input unit) are normally connected to the power supply VDD and ground, the D latch is in "working state", and can complete transparent data transmission and latching.

[0060] When Pwr_on is low: M1 and M6 are cut off, cutting off the power supply path of the core circuit, and the D latch enters the "standby state"; at this time, the low leakage characteristics of the FinFET device can make the static current approach zero, achieving "near-zero standby power consumption", which meets the circuit's "low power consumption" design goal.

[0061] (4) Timing synchronization signals: ck_p, ck_m

[0062] ck_p (Clock Positive) and ck_m (Clock Negative) are timing control signals for the D latch, used to switch states and ensure stable data storage at high speeds. They are complementary clocks (opposite levels, no overlap).

[0063] When ck_p (positive clock) is active high, the MOS transistor (M7) driving the data input unit of the D latch is turned on, and the input data D can be transmitted to the output terminal Q in real time through the inverter (INV1-INV2) to realize the synchronous update of data.

[0064] When ck_m (inverting clock) is active high, the D latch is in "latch-and-hold state": the driving MOS transistor (M8) is turned on, the input data D is disconnected from the core register (cross-coupled inverter), and the inverter maintains the current output Q level through a positive feedback loop to avoid data jitter due to input changes.

[0065] like Figure 2 As shown, the feedforward signal preprocessing module consists of 5-stage D latches (U1-U5) and 7-stage buffers (BUF1-BUF7). The connection relationships of each component are as follows:

[0066] The input terminal of the first-stage D latch U1 is connected to the input signal DATA, and the output terminal is connected to the input terminal of the second-stage D latch U2.

[0067] The output of the second-stage D latch U2 is connected to the input of the first-stage buffer BUF1;

[0068] The output of the first-stage buffer BUF1 is connected to the input of the third-stage D latch U3;

[0069] The output of the third-stage D latch U3 is connected to the input of the second-stage buffer BUF2;

[0070] The output of the second-stage buffer BUF2 is connected to the input of the third-stage buffer BUF3, and the output of the third-stage buffer BUF3 is the output of the Data_pre signal.

[0071] A signal is taken from the output of the third-stage D latch U3 and connected to the input of the fourth-stage D latch U4;

[0072] The output of the fourth-stage D latch U4 is connected to the input of the fourth-stage buffer BUF4;

[0073] The output of the fourth-stage buffer BUF4 is connected to the input of the fifth-stage buffer BUF5, and the output of the fifth-stage buffer BUF5 is the output of the Data_main signal.

[0074] A signal is taken from the output of the fourth-stage D latch U4 and connected to the input of the fifth-stage D latch U5;

[0075] The output of the fifth-stage D latch U5 is connected to the input of the sixth-stage buffer BUF6;

[0076] The output of the sixth-level buffer BUF6 is connected to the input of the seventh-level buffer BUF7, and the output of the seventh-level buffer BUF7 is the output of the Data_post signal.

[0077] The timing difference configuration of the signals in each path is achieved by varying the number of cascaded D latches.

[0078] like Figure 3 As shown, the first to fifth D latch circuits include eight transistors M1-M8 and two inverters INV1-INV2. The connection relationships of each device are as follows:

[0079] The source of the first-stage transistor M1 is connected to the power supply VDD, the gate is connected to the signal Pwr_on, and the drain is connected to the source of the seventh-stage transistor M7 and the input terminal of the first-stage inverter INV1.

[0080] The source of the second-stage transistor M2 is connected to the power supply VDD, and the drain is connected to the source of the third-stage transistor M3.

[0081] The gate of the third-stage transistor M3 is connected to the signal ck_m, and the drain is connected to the output of the first-stage inverter INV1.

[0082] The gate of the fourth-stage transistor M4 is connected to the signal ck_p, the drain is connected to the drain of the third-stage transistor M3, and the source is connected to the drain of the fifth-stage transistor M5.

[0083] The source of the fifth-stage transistor M5 is connected to the drain of the sixth-stage transistor M6;

[0084] The gate of the sixth-stage transistor M6 is connected to the signal Pwr_on, and its source is grounded;

[0085] The gate of the seventh-stage transistor M7 is connected to the signal ck_p, and the drain is connected to the input signal D;

[0086] The gate of the eighth-stage transistor M8 is connected to the signal ck_m, the drain is connected to the input signal D, and the source is grounded.

[0087] The output of the first-stage inverter INV1 is connected to the drain of the fourth-stage transistor M4;

[0088] The input of the second-stage inverter INV2 is connected to the drain of the seventh-stage transistor M7, and the output is the signal output Q of the D latch.

[0089] like Figure 4 As shown, the circuit of the weight allocation unit includes eight transistors M9-M16 and a single-stage inverter INV3. The connection relationship of each device is as follows:

[0090] The source of the ninth-stage transistor M9 is connected to the power supply VDD, the gate is connected to the signal Sel_eq_n, and the drain is connected to the source of the tenth-stage transistor M10.

[0091] The gate of the tenth-stage transistor M10 is connected to the signal Data_pre, and its drain is connected to the drain of the eleventh-stage transistor M11.

[0092] The gate of the eleventh-stage transistor M11 is connected to the signal Data_post, and the source is connected to the drain of the twelfth-stage transistor M12.

[0093] The gate of the 12th transistor M12 is connected to the signal Sel_eq, and its source is grounded;

[0094] The source of the thirteenth stage transistor M13 is connected to the power supply VDD, the gate is connected to the signal Sel_main_n, and the drain is connected to the source of the fourteenth stage transistor M14.

[0095] The gate of the fourteenth-stage transistor M14 is connected to the signal Data_main, and its drain is connected to the drain of the fifteenth-stage transistor M15.

[0096] The source of the fifteenth stage transistor M15 is connected to the drain of the sixteenth stage transistor M16;

[0097] The gate of the sixteenth-stage transistor M16 is connected to the signal Sel_main, and the source is grounded.

[0098] The drain of the tenth-stage transistor M10 is connected to the drain of the fourteenth-stage transistor M14. Their common connection point is connected to the input of the first-stage inverter INV3. The output of the inverter INV3 is the signal output OUT of this sub-circuit.

[0099] Overall circuit coordinated connection, such as Figure 1 As shown, the Data_pre, Data_main, and Data_post signal ports of the feedforward signal preprocessing circuit are connected to the corresponding signal ports of the 40 weight allocation units, respectively; the OUT ports of the 40 weight allocation units are connected in parallel to serve as the final output ports of the equalization circuit.

[0100] The first through eighth transistors can be either FinFETs or MOSFETs.

[0101] The working principle of the circuit to improve the input common-mode range and reduce the mismatch current is as follows:

[0102] The core working principle of this equalization circuit, which achieves advantages such as low power consumption, high-precision compensation, and high stability, is based on a three-layer logic of "process characteristic adaptation + module function coordination + refined signal processing." This approach specifically addresses channel loss and circuit performance bottlenecks in high-speed transmission, as detailed below:

[0103] The low leakage current characteristic, combined with the power control unit in the module (such as M1 and M6 of the D latch), cuts off the power path in standby mode, further reducing static power consumption and achieving dual energy efficiency optimization of "low power consumption during operation + near-zero power consumption in standby".

[0104] The working principle of feedforward signal preprocessing is to generate a multipath signal with timing offset by using the delay difference of a tiered D latch:

[0105] The input data DATA is delayed by D latches of different levels (U1-U5) to form three signals: Data_pre (short delay), Data_main (medium delay), and Data_post (long delay). The timing difference between the three signals corresponds to different frequency components of the signal.

[0106] The inverter's level normalization function ensures that the logic levels of the three signals are consistent, avoiding level mismatch during subsequent superposition. This design allows the "multi-tap signals" required for pre-emphasis compensation to have precise timing and consistent levels, providing a stable signal source for high-frequency component enhancement.

[0107] The D latch operates on the principle of "transparent transmission-latch hold" switching under complementary clock control, plus positive feedback for stable storage: When clk_p is valid, M7 is turned on, and data D is transmitted to INV2 via INV1. The inverter pairs update the output Q in real time through the positive feedback loop (transparent transmission); when clk_m is valid, M8 is turned on, the input is disconnected from the register, and the positive feedback loop maintains the current Q state (latch hold). The high gain characteristics of FinFET devices enhance the positive feedback strength, ensuring the stability of the latch state at high speeds and avoiding signal jitter.

[0108] The Pwr_on signal drives M1 and M6 to cut off the power supply path. Utilizing the low leakage characteristics of FinFET, there is almost no static power consumption in standby mode, thus achieving dynamic power consumption control.

[0109] The working principle of multi-chip parallel weight allocation is to achieve precise superposition of signal components through the independent gating of 40 sub-circuits:

[0110] Each circuit chip contains an "equalization path (corresponding to Data_pre / Data_post, responsible for high-frequency components)" and a "main path (corresponding to Data_main, responsible for the basic swing)", and the corresponding path is selected by control signals such as Sel_eq / Sel_main;

[0111] The parallel configuration of 40 chips enables a weight adjustment granularity of 1 / 40: if the channel has high high-frequency loss, the number of equalization path selection sub-circuits can be increased to enhance the superposition ratio of Data_pre / Data_post (high-frequency component enhancement); if the channel loss is low, the number of main path selections can be increased to ensure the basic swing of the signal. This design breaks through the limitations of traditional coarse adjustment with a small number of taps and achieves precise adaptation to different channels.

[0112] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless defined as herein.

[0113] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-power, high-swing equalization circuit for use in a high-speed interface transmitter, characterized in that, It includes a feedforward signal preprocessing module and a weight allocation module; The feedforward signal preprocessing module includes first to fifth D latches, first to seventh buffers, and first to second switches; The first to fifth D latches have the same structure, each including first to eighth transistors and first to second inverters. The source of the first transistor is connected to an external power supply VDD, its gate is connected to an external control signal Pwr_on, and its drain is connected to the input of the first inverter, the input of the second inverter, the drain of the third transistor, the drain of the fourth transistor, the source of the seventh transistor, and the source of the eighth transistor, respectively. The output of the first inverter is connected to the gate of the second transistor and the gate of the fifth transistor, respectively. The source of the second transistor is connected to an external power supply VDD, and its drain is connected to the source of the third transistor. The third transistor's... The gate of the fourth transistor is connected to the inverted clock signal ck_m; the gate of the fifth transistor is connected to the positive clock signal ck_p, and its source is connected to the drain of the fifth transistor; the source of the fifth transistor is connected to the drain of the sixth transistor; the gate of the sixth transistor is connected to the external control signal Pwr_on, and its source is grounded; the gate of the seventh transistor is connected to the positive clock signal ck_p, and its drain is connected to the drain of the eighth transistor to serve as the input terminal of the D latch; the gate of the eighth transistor is connected to the inverted clock signal ck_m; the output of the second inverter serves as the output terminal of the D latch; the external control signal Pwr_on is used to control the power supply path of the D latch to be turned on and off; The input terminal of the first D latch serves as the input terminal of the feedforward signal preprocessing module and also as the input terminal of the equalization circuit; the output terminal of the first D latch, the second D latch, the first buffer, and the input terminal of the third D latch are connected in sequence. The output of the third D latch is connected to the input of the second buffer and the input of the fourth D latch, respectively. The output of the second buffer, the third buffer, and one end of the first switch are connected in sequence. The output of the fourth D latch is connected to the input of the fourth buffer and the input of the fifth D latch, respectively. The output of the fourth buffer is connected to the input of the fifth buffer; The output of the fifth D latch, the sixth buffer, the seventh buffer, and one end of the second switch are connected in sequence; The other end of the first switch serves as the first output of the feedforward signal preprocessing module, the output of the fifth D latch serves as the second output of the feedforward signal preprocessing module, and the other end of the second switch serves as the third output of the feedforward signal preprocessing module. The weight allocation module contains 40 weight allocation units; The weighting unit includes a first inverter and nine to sixteenth transistors; The source of the ninth transistor is connected to the external power supply VDD, the drain is connected to the source of the tenth transistor, and the gate is connected to the external signal Sel_eq_n. The drain of the tenth transistor is connected to the drain of the eleventh transistor, the drain of the fourteenth transistor, the drain of the fifteenth transistor, and the input terminal of the third inverter. The gate of the tenth transistor is connected to the gate of the eleventh transistor and serves as the first input terminal of the weighting unit. The source of the eleventh transistor is connected to the drain of the twelfth transistor; The gate of the twelfth transistor is connected to the external signal Sel_eq, and the source is grounded; The source of the thirteenth transistor is connected to the external power supply VDD, the drain is connected to the source of the fourteenth transistor, and the gate is connected to the external signal Sel_main_n. The gates of the fourteenth transistor and the fifteenth transistor are connected to form the second input terminal of the weighting unit; The source of the fifteenth transistor is connected to the drain of the sixteenth transistor; The gate of the sixteenth transistor is connected to the external signal Sel_main, and the source is grounded; The external signal Sel_eq is an inverted signal of Sel_eq_n, which is used to control the conduction of the ninth transistor and the twelfth transistor; the external signal Sel_main is an inverted signal of Sel_main_n, which is used to control the conduction of the sixteenth transistor and the thirteenth transistor. The output of the third inverter serves as the output of the weight allocation unit. The first input terminals of the 40 weight allocation units are connected in parallel and then connected to the first and third output terminals of the feedforward signal preprocessing module, respectively. The second input terminals of the 40 weight allocation units are connected in parallel and then connected to the second output terminal of the feedforward signal preprocessing module. The output terminals of the 40 weight allocation units are connected in parallel and then used as the output terminals of the equalization circuit.

2. A low-power, high-swing equalization circuit for a high-speed interface transmitter as described in claim 1, characterized in that, The first through eighth transistors all use FinFET.

3. A low-power, high-swing equalization circuit for a high-speed interface transmitter as described in claim 1, characterized in that, The first through eighth transistors are all MOS transistors.

Images