Two-dimensional image sensor readout circuit architecture suitable for single-photon detector

Abstract

The invention relates to a two-dimensional image sensor reading circuit architecture suitable for a single-photon detector, belongs to the field of two-dimensional single-photon image sensors, and aims to reduce the pixel dead zone time through an active quenching circuit and an active reset circuit so as to improve the dynamic range of the sensor and enable the pixel dead zone time to be controllable. And the conditions that the pixel is inactivated due to the metastable state and the exposure time is occupied by the dead time are prevented. And the pulse output processing circuit combines a plurality of paths of electrical pulses output by the plurality of single-photon detectors into one path of macro-pixel pulse signal, so that the dead zone time is further reduced, the limited shortest dead zone time of a single device caused by deterioration of the pixel filling rate is broken through, and the dynamic range of the sensor is further expanded. A stack type counter is adopted to replace a traditional binary digital counter, and the resolution of the sensor is improved. The parameter configuration circuit improves the flexibility of the two-dimensional image sensor, so that the two-dimensional image sensor can support the dynamic range, resolution and frame rate requirements of various sensors.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of two-dimensional single-photon image sensors, and particularly relates to a two-dimensional image sensor readout circuit architecture suitable for single-photon detectors. BACKGROUND

[0002] A two-dimensional single-photon detector is an image sensor based on a single-photon detector, which mainly converts a single photon incident to the single-photon detector into an electrical pulse signal, and records the number of pulses in a period of time by using a counter to realize scene image capture. The two-dimensional image sensor based on the single-photon detector has the advantages of high dynamic range, high light gain and high signal-to-noise ratio, and has good application prospects in intelligent driving, biological medicine and even aerospace fields. Since the dynamic range of the sensor is negatively related to the dead time of the pixel, an active quenching circuit is often used to reduce the dead time, but it is easy to cause problems such as uncontrollable dead time, metastable state inactivating the pixel, limited shortest dead time and dead time occupying exposure time. At the same time, the dynamic range of the sensor is positively related to the bit width of the pixel counter, but the resolution of the sensor is negatively related to the bit width of the pixel counter, which makes there is a contradictory balance relationship between the dynamic range of the sensor and the resolution of the sensor. SUMMARY

[0003] In order to solve the above problems existing in the prior art, the present application provides a two-dimensional image sensor readout circuit architecture suitable for single-photon detectors. The technical problem to be solved by the present application is realized by the following technical scheme: The application provides a two-dimensional image sensor readout circuit architecture suitable for a single photon detector, comprising: a single photon detector array, an active quenching and active reset circuit, a quenching and reset control circuit, a pulse output processing circuit, a counting mode control circuit, a stack counter circuit, an on-chip control circuit and a data preprocessing and storage circuit, wherein the single photon detector array comprises: a plurality of array arranged single photon detectors, each single photon detector inputs a single photon signal and is used for converting the single photon signal into an electrical pulse; the pulse output processing circuit is connected to the output end of the single photon detector array, is used for compressing the pulse width of the electrical pulse, and combines a plurality of electrical pulses output by the plurality of single photon detectors into a macro-pixel pulse signal; the counting mode control circuit is connected to the input end of the pulse output processing circuit, comprises a plurality of counting modes, and is used for inputting the plurality of macro-pixel pulse signals into a plurality of stack counter units of the stack counter circuit in the plurality of counting modes; the stack counter circuit comprises a plurality of chain connected stack counter units, is connected to the output end of the counting mode control circuit, and is used for obtaining the photon counting relative value of any adjacent macro-pixel according to the macro-pixel pulse signal input by the counting mode control circuit; the stack counter circuit is also used for outputting the counting data to the data preprocessing and storage circuit in the form of a shift register; the on-chip control circuit inputs an off-chip enable pulse signal and off-chip parameter data, outputs a plurality of control signals according to the off-chip enable pulse signal and the off-chip parameter data, and correspondingly controls the quenching and reset control circuit, the counting mode control circuit, the stack counter circuit and the data preprocessing and storage circuit; the quenching and reset control circuit is connected to the output end of the single photon detector array and the on-chip control circuit, and is used for obtaining a controlled quenching signal and a reset signal according to the electrical pulse and the control signal; the active quenching and active reset circuit is connected to the output end of the quenching and reset control circuit, and is used for correspondingly controlling the quenching, reset and exposure enable state of the single photon detector array according to the quenching signal and the reset signal; the data preprocessing and storage circuit is connected to the output end of the stack counter circuit and the on-chip control circuit, is used for obtaining two-dimensional gray scale image data according to the photon counting relative value, stores the two-dimensional gray scale image data and outputs.

[0004] In one embodiment of the present application, the on-chip control circuit comprises: a parameter configuration circuit and a sensor control circuit, wherein the parameter configuration circuit inputs off-chip parameter data for storing the off-chip parameter data; the parameter configuration circuit outputs the stored off-chip parameter data to the off-chip for verifying the off-chip parameter data; the sensor control circuit inputs an off-chip enable pulse signal, and the input end is connected to the output end of the parameter configuration circuit, for outputting a plurality of control signals according to the stored off-chip parameters and under the control of the off-chip enable pulse signal, so as to correspondingly control the quenching and reset control circuit, the counting mode control circuit, the stack counter circuit and the data preprocessing and storage circuit.

[0005] In one embodiment of the present application, the active quenching and active reset circuit comprises: a passive quenching circuit, an active quenching circuit and an active reset circuit, wherein the passive quenching circuit inputs a fixed power supply potential for preliminarily controlling the quenching state of the single photon detector array; the active quenching circuit is connected to the output end of the quenching and reset control circuit, for controlling the quenching state of the single photon detector array according to the quenching signal and the reset signal respectively, and stopping the quenching state when the quenching state of the single photon detector array conflicts with the reset state thereof; the active reset circuit is connected to the output end of the quenching and reset control circuit, for controlling the single photon detector array to enter the working state according to the reset signal.

[0006] In one embodiment of the present application, the quenching and reset control circuit comprises: a quenching signal edge trigger circuit, a quenching signal pulse width control circuit, a reset signal edge trigger circuit and a reset signal pulse width control circuit, wherein the quenching signal edge trigger circuit is connected to the output end of the single photon detector array, the quenching signal pulse width control circuit and the sensor control circuit respectively, for detecting the rising edge of the electrical pulse to obtain the quenching signal, and controlling the high and low level state of the quenching signal according to the control signal, so as to realize the switching control of the single photon detector array; the quenching signal pulse width control circuit inputs a first off-chip voltage signal for controlling the pulse width of the quenching signal according to the first off-chip voltage signal; the reset signal edge trigger circuit is connected to the output end of the quenching signal edge trigger circuit and the reset signal pulse width control circuit respectively, for detecting the falling edge of the quenching signal to obtain the reset signal; the reset signal pulse width control circuit inputs a second off-chip voltage signal for controlling the pulse width of the reset signal according to the second off-chip voltage signal.

[0007] In one embodiment of the present application, the counting mode control circuit is connected to the output of the sensor control circuit, and is configured to control the counting mode of the sensor control circuit according to the control signal. The counting mode of the counting mode control circuit includes: left-neighbor counting and right-neighbor counting; and the odd-numbered pixels are fixed pixels, the fixed pixels are connected to the same stack counter unit with the output of the even-numbered pixels on the left side of the fixed pixels in the left-neighbor counting, and the fixed pixels are connected to the same stack counter unit with the output of the even-numbered pixels on the right side of the fixed pixels in the right-neighbor counting.

[0008] In one embodiment of the present application, the stack counter circuit is connected to the output of the sensor control circuit, and is configured to control the working mode of each stack counter unit in the sensor control circuit according to the control signal. The working mode of each stack counter unit includes: reset, set and relative counting.

[0009] In one embodiment of the present application, the parameter configuration circuit includes: a serial-to-parallel circuit, a parallel-to-serial circuit and a data storage circuit. The serial-to-parallel circuit is configured to input an off-chip parameter, and the off-chip parameter includes: an exposure time parameter, an array size parameter and a dynamic range parameter. The serial-to-parallel circuit is configured to write the off-chip parameter to the data storage circuit. The data storage circuit is connected to the output of the serial-to-parallel circuit, and is configured to store the off-chip parameter. The parallel-to-serial circuit is configured to output the off-chip parameter stored in the data storage circuit to the off-chip.

[0010] In one embodiment of the present application, the sensor control circuit includes: a state machine circuit, a comparator circuit and a counter circuit. The state machine circuit is configured to input an off-chip enable pulse signal, and is connected to the output of the comparator circuit. The state machine circuit is configured to output a plurality of control signals according to the off-chip enable pulse signal and the control of the comparator circuit. The counter circuit is connected to the output of the state machine circuit, and is configured to count the plurality of control signals to obtain a time count value. The comparator circuit is connected to the output of the data storage circuit and the counter circuit, and is configured to compare the off-chip parameter stored in the data storage circuit with the time count value to obtain a corresponding flip signal, and control the state machine circuit through the corresponding flip signal.

[0011] In one embodiment of the present application, the plurality of control signals includes: a counting mode control signal, an exposure enable control signal, a data readout control signal and a data processing control signal. The counting mode control signal is configured to control the counting mode of the counting mode control circuit. The exposure enable control signal is configured to control the opening or closing of the single-photon detector array. The data readout control signal is configured to control the opening and closing of the data readout function of the stack counter circuit. The data processing control signal is configured to control the data processing and storage of the data preprocessing and storage circuit.

[0012] In one embodiment of the present application, the data preprocessing and storage circuit comprises: a data read-write control and addressing circuit, a static random memory circuit, a chain calculation circuit and a data mapping circuit, wherein the data read-write control and addressing circuit is connected to the output end of the state machine circuit, used to control the stack counter circuit to write the photon count relative value to the static random memory circuit according to the control signal, and control the readout order of the written photon count relative value; the static random memory circuit is connected to the output end of the stack counter circuit, the data read-write control and addressing circuit and the data mapping circuit, used to store the photon count relative value; the chain calculation circuit is connected to the output end of the static random memory circuit, used to read out the photon count relative value and calculate the pulse count absolute value according to the photon count relative value; and the data mapping circuit is connected to the output end of the chain calculation circuit, used to perform data mapping on the pulse count absolute value to obtain the incident light intensity information and write it to the static random memory circuit.

[0013] Compared with the prior art, the present application has the following beneficial effects: The two-dimensional image sensor readout circuit architecture suitable for single photon detectors of the present application reduces the pixel dead time through active quenching and active reset circuits to improve the sensor dynamic range, and can make the pixel dead time controllable, and prevent the pixel from being inactivated and the dead time from occupying the exposure time due to metastability. The pulse output processing circuit combines multiple electrical pulses into one macro-pixel, further reduces the dead time, breaks through the limited shortest dead time of a single device due to the deterioration of pixel fill factor, and further improves the sensor dynamic range. The stack counter is used instead of the traditional binary digital counter, which reduces the circuit area of the counter array while maintaining the high dynamic range of the sensor, thereby improving the sensor resolution.

[0014] The two-dimensional image sensor readout circuit architecture suitable for single photon detectors of the present application widens the adjustable dynamic range and adjustable resolution based on the parameter configuration circuit, improves the flexibility of the two-dimensional image sensor, and makes it can support various sensor dynamic range, resolution and frame rate requirements, which has been significantly optimized and improved in reliability and flexibility.

[0015] The above description is only a summary of the technical solutions of the present application, in order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are as follows. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1This is a structural block diagram of a two-dimensional image sensor readout circuit architecture suitable for single-photon detectors provided in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the workflow sequence of the active quenching and active reset circuit provided in an embodiment of the present invention. Figure 3 This is a structural block diagram of the active quenching and active reset circuit provided in an embodiment of the present invention; Figure 4 This is a structural block diagram of the quenching and reset control circuit provided in an embodiment of the present invention; Figure 5 This is a structural block diagram of the parameter configuration circuit provided in an embodiment of the present invention; Figure 6 This is a structural block diagram of the sensor control circuit provided in an embodiment of the present invention; Figure 7 This is a structural block diagram of the data preprocessing and storage circuit provided in an embodiment of the present invention.

[0017] Icons: 100 - Single-photon detector array; 200 - Active quenching and active reset circuit; 210 - Passive quenching circuit; 220 - Active quenching circuit; 230 - Active reset circuit; 300 - Quenching and reset control circuit; 310 - Quenching signal edge triggering circuit; 320 - Quenching signal pulse width control circuit; 330 - Reset signal edge triggering circuit; 340 - Reset signal pulse width control circuit; 400 - Pulse output processing circuit; 500 - Counting mode control circuit; 600 - Stack-type counter circuit; 700 - Parameter configuration circuit; 710 - Serial-in parallel-out circuit; 720 - Parallel-in serial-out circuit; 730 - Data storage circuit; 800 - Sensor control circuit; 810 - State machine circuit; 820 - Comparator circuit; 830 - Counter circuit; 900 - Data preprocessing and storage circuit; 910 - Data read / write control and addressing circuit; 920 - Static random access memory circuit; 930 - Chain-based calculation circuit; 940 - Data mapping circuit. Detailed Implementation

[0018] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a detailed explanation of a two-dimensional image sensor readout circuit architecture suitable for single-photon detectors proposed according to the present invention.

[0019] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0020] Example 1 Because sensor dynamic range is negatively correlated with pixel dead time and positively correlated with pixel counter bit width, but sensor resolution is negatively correlated with pixel counter bit width, there is a contradictory relationship between sensor dynamic range and sensor resolution. Therefore, to improve the performance of 2D image sensors, it is necessary to balance this contradiction and reduce the mutual influence between sensor dynamic range and sensor resolution.

[0021] In view of this, such as Figure 1 As shown, the present invention provides a readout circuit architecture for a two-dimensional image sensor suitable for single-photon detectors, including: a single-photon detector array 100, an active quenching and active reset circuit 200, a quenching and reset control circuit 300, a pulse output processing circuit 400, a counting mode control circuit 500, a stacked counter circuit 600, an on-chip control circuit, and a data preprocessing and storage circuit 900.

[0022] Specifically, the single-photon detector array 100 receives a single-photon signal at its input terminal and its output terminals are connected to the input terminals of the quenching and reset control circuit 300 and the pulse output processing circuit 400, respectively. The active quenching and reset circuit 200 has its input terminal connected to the output terminal of the quenching and reset control circuit 300, and its output terminal connected to the input terminal of the single-photon detector array 100. The quenching and reset control circuit 300 has its input terminals connected to the output terminals of the single-photon detector array 100 and the on-chip control circuit, respectively, and its output terminal connected to the input terminal of the active quenching and reset circuit 200. The pulse output processing circuit 400 has its input terminal connected to the output terminal of the single-photon detector array 100, and its output terminal connected to... The counting mode control circuit 500 has an input terminal; the input terminal of the counting mode control circuit 500 is connected to the output terminal of the pulse output processing circuit 400 and the on-chip control circuit, respectively, and the output terminal is connected to the input terminal of the stacked counter circuit 600; the stacked counter circuit 600 has an input terminal connected to the output terminal of the counting mode control circuit 500 and the on-chip control circuit, respectively, and the output terminal is connected to the input terminal of the data preprocessing and storage circuit 900; the on-chip control circuit receives an external enable pulse signal at its input terminal, and its output terminal is connected to the input terminals of the quenching and reset control circuit 300, the counting mode control circuit 500, the stacked counter circuit 600, and the data preprocessing and storage circuit 900, respectively.

[0023] In this embodiment, as Figure 1As shown, a single-photon detector array 100 includes: several arrayed single-photon detectors, each receiving a single-photon signal, used to convert the single-photon signal into an electrical pulse; a pulse output processing circuit 400, with its input connected to the output of the single-photon detector array 100, used to compress the pulse width of the electrical pulse and combine the several electrical pulses output from the several single-photon detectors into a single macro-pixel pulse signal; a counting mode control circuit 500, with its input connected to the pulse output processing circuit 400, including several counting modes, used to input the several macro-pixel pulse signals into several stacked counter units of a stacked counter circuit 600 under several counting modes; the stacked counter circuit 600 includes several chained stacked counter units, with its input connected to the output of the counting mode control circuit 500, used to obtain the relative photon count values ​​of any adjacent macro-pixels based on the macro-pixel pulse signals input to the counting mode control circuit 500; the stacked counter circuit 600 is also used to transfer the counts in the form of a shift register. Data is output to the data preprocessing and storage circuit 900; the on-chip control circuit, which receives external enable pulse signals and external parameter data, outputs several control signals according to the external enable pulse signals and external parameter data to control the operation of the quenching and reset control circuit 300, the counting mode control circuit 500, the stacked counter circuit 600, and the data preprocessing and storage circuit 900; the quenching and reset control circuit 300 has its input terminal connected to the single-photon detector array 100 and the output terminal of the on-chip control circuit, and is used to output several control signals according to the electrical... The system obtains controlled quenching and reset signals from pulse and control signals; the active quenching and active reset circuit 200, with its input connected to the output of the quenching and reset control circuit 300, is used to control the quenching, reset, and exposure enable states of the single-photon detector array 100 according to the corresponding quenching and reset signals; the data preprocessing and storage circuit 900, with its input connected to the output of the stacked counter circuit 600 and the on-chip control circuit, is used to obtain two-dimensional grayscale image data based on the relative value of photon counts, store the two-dimensional grayscale image data, and output it.

[0024] In one alternative implementation, such as Figure 1 , Figure 5 and Figure 6As shown, the on-chip control circuit includes a parameter configuration circuit 700 and a sensor control circuit 800. The parameter configuration circuit 700 inputs external parameter data and stores it. It also outputs the stored external parameter data to an external source for verification. The sensor control circuit 800 inputs an external enable pulse signal, and its input is connected to the output of the parameter configuration circuit 700. Based on the stored external parameters and under the control of the external enable pulse signal, it outputs several control signals to correspondingly control the operation of the quenching and reset control circuit 300, the counting mode control circuit 500, the stacked counter circuit 600, and the data preprocessing and storage circuit 900.

[0025] In one optional implementation, the active quenching and active reset circuit 200 is used to control whether the single-photon detector array 100 is working; it is also used to quench the output pulses of the single-photon detector array 100 and reset it to a state with single-photon detection capability; at the same time, it can also prevent metastability from causing pixel deactivation.

[0026] In one alternative implementation, such as Figure 2 and Figure 3 As shown, the active quenching and active reset circuit 200 includes: a passive quenching circuit 210, an active quenching circuit 220, and an active reset circuit 230. The passive quenching circuit 210 receives a fixed power supply potential and is used to initially control the quenching state of the single-photon detector array 100. The active quenching circuit 220 has its input connected to the output of the quenching and reset control circuit 300 and is used to control the quenching state of the single-photon detector array 100 according to the quenching signal and the reset signal, respectively, and to stop the quenching state when the quenching state of the single-photon detector array 100 conflicts with its reset state. The active reset circuit 230 has its input connected to the output of the quenching and reset control circuit 300 and is used to control the single-photon detector array 100 to enter the working state according to the reset signal.

[0027] Specifically, the passive quenching circuit 210 reduces the reverse bias value of the single-photon detector by increasing the anode voltage, thereby initially quenching its output avalanche current. The active quenching circuit 220, under the control of the quenching signal output by the quenching signal edge triggering circuit 310, introduces an additional pull-up current to accelerate the quenching process of the avalanche current; simultaneously, it is also controlled by the reset signal output by the reset signal edge triggering circuit 330 to prevent metastability from causing pixel deactivation. The active reset circuit 230, under the control of the reset signal output by the reset signal edge triggering circuit 330, introduces a pull-down current to allow the single-photon detector to re-enter the Geiger operating mode.

[0028] In an optional implementation, the quench and reset control circuit 300 outputs quench and reset signals to drive the active quench and active reset circuit 200. It also controls pixel dead time, prevents metastability from deactivating pixels, and prevents dead time from encroaching on exposure time.

[0029] In one alternative implementation, such as Figure 4 As shown, the quenching and reset control circuit 300 includes: a quenching signal edge triggering circuit 310, a quenching signal pulse width control circuit 320, a reset signal edge triggering circuit 330, and a reset signal pulse width control circuit 340. The quenching signal edge triggering circuit 310 has its input terminals connected to the output terminals of the single-photon detector array 100, the quenching signal pulse width control circuit 320, and the sensor control circuit 800, respectively. It is used to detect the rising edge of electrical pulses to obtain a quenching signal and to control the high and low level states of the quenching signal according to the control signal, thereby achieving... The circuit includes: a switching control for the single-photon detector array 100; a quenching signal pulse width control circuit 320, which receives a first external voltage signal and controls the pulse width of the quenching signal based on the first external voltage signal; a reset signal edge triggering circuit 330, whose input terminals are connected to the output terminals of the quenching signal edge triggering circuit 310 and the reset signal pulse width control circuit 340, respectively, for detecting the falling edge of the quenching signal to obtain a reset signal; and a reset signal pulse width control circuit 340, which receives a second external voltage signal and controls the pulse width of the reset signal based on the second external voltage signal.

[0030] Specifically, the quench signal edge triggering circuit 310 utilizes signal propagation delay to detect the rising edge of the electrical pulse output by the single-photon detector array 100. When the output potential of the single-photon detector array 100 rises to a threshold, it outputs a high-level quench signal, enabling an active quench current to accelerate the quenching process. Simultaneously, the falling edge of the quench signal drives the generation of a reset signal. Furthermore, under the control of the sensor control circuit 800, the high and low levels of the quench signal control the pixel bias state to achieve pixel switching control. The quench signal pulse width control circuit 320, under the control of the first external voltage signal, adjusts the signal propagation delay to control the quench signal pulse width, thereby controlling the pixel dead time. The reset signal edge triggering circuit 330 utilizes signal propagation delay to detect the falling edge of the quench signal. When the quench signal voltage value drops to a threshold, it outputs a low-level reset signal, enabling an active reset current to restore the pixel's single-photon detection capability. The reset signal pulse width control circuit 340, under the control of the second external voltage signal, adjusts the signal propagation delay to control the reset signal pulse width, ensuring that the pixel has enough time to recover single-photon detection capability.

[0031] In an optional implementation, pulse output processing circuitry 400 is used to compress the electrical pulse width of individual pixels and merge macro-pixel output signals. Macro-pixels can further reduce pixel dead time, overcoming the limitation on the shortest dead time per device caused by pixel fill rate degradation.

[0032] In an optional implementation, the counting mode control circuit 500, under the control of the sensor control circuit 800, inputs the macro-pixel pulse signal output by the pulse output processing circuit 400 to several stacked counter units of the stacked counter circuit 600.

[0033] In one alternative implementation, such as Figure 1 As shown, the counting mode control circuit 500 has its input terminal connected to the output terminal of the sensor control circuit 800. It is used to control its counting mode according to the control signal. The counting modes of the counting mode control circuit 500 include: left neighbor counting and right neighbor counting; with odd-numbered pixels as fixed pixels, when counting left neighbors, the output terminals of the fixed pixels and the even-numbered pixels to their left are connected to the same stacked counter unit; when counting right neighbors, the output terminals of the fixed pixels and the even-numbered pixels to their right are connected to the same stacked counter unit.

[0034] It's worth noting that, since the number of pixels in a row is even, in left-neighbor counting mode, the leftmost pixel in the row is connected to a separate stacked counter unit to directly obtain its macro-pixel pulse count absolute value, while the rightmost pixel in each row is left unconnected. Following the workflow of right-neighbor counting—data readout—left-neighbor counting—data readout, the relative pulse count values ​​between any two adjacent pixels can ultimately be obtained.

[0035] In one alternative implementation, such as Figure 1 As shown, the stacked counter circuit 600 has its input terminal connected to the output terminal of the sensor control circuit 800, and is used to control the working mode of each stacked counter unit according to the control signal; the working modes of each stacked counter unit include: reset, set, and relative counting.

[0036] Specifically, in relative counting mode, the two input signals are sampled synchronously to count the relative value of the pulse counts of the two macropixels. The highest bit of the output data is used as the binary sign bit. In set mode, the input set data is directly output to its output terminal. In reset mode, the output data of the stacked counter unit is reset to zero. The working principle of the chained structure of the stacked counter units is as follows: the output terminal of the previous stacked counter unit is shorted to the set input terminal of the next stacked counter unit. Therefore, in set mode, the counting data in the stacked counter circuit 600 flows in the form of a shift register, and finally outputs the relative value of the photon count to the data preprocessing and storage circuit 900, while resetting its own data. This data readout method is similar to the data readout method of a CCD image sensor. It is worth noting that if the stacked counter unit has only one input, its function is no different from that of a regular binary counter.

[0037] In an optional implementation, the parameter configuration circuit 700 can accept and store external parameters, output the stored external parameters to the outside of the chip to verify the correctness of the external parameters, and input the stored data to the sensor control circuit 800 to complete the system parameters in the control logic of the sensor control circuit 800.

[0038] In one alternative implementation, such as Figure 5 As shown, the parameter configuration circuit 700 includes: a serial-in parallel-out circuit 710, a parallel-in serial-out circuit 720, and a data storage circuit 730. The serial-in parallel-out circuit 710 inputs external parameters, including exposure time parameters, array size parameters, and dynamic range parameters, and writes these external parameters to the data storage circuit 730. The data storage circuit 730 has its input connected to the output of the serial-in parallel-out circuit 710, and its output connected to both the input of the parallel-in serial-out circuit 720 and the input of the sensor control circuit 800, for storing the external parameters. The parallel-in serial-out circuit 720 outputs the external parameters stored in the data storage circuit 730 to the external circuit.

[0039] Specifically, the serial-in parallel-out circuit 710 uses the shift register principle to sequentially write external parameter data into the data storage circuit 730. The parallel-in serial-out circuit 720 uses the shift register principle to sequentially read the external parameter data stored on-chip to the external location for external data verification. The data storage circuit 730 is used to store the external parameter data, which includes: exposure time parameters, used to control the exposure time used by the 2D image sensor to form one frame of image; array size parameters, used to adapt to 2D image sensors with different array sizes of single-photon detectors; and dynamic range parameters, used to control the imaging dynamic range of the 2D image sensor.

[0040] In one alternative implementation, the sensor control circuit 800, under the control of an off-chip enable pulse signal and off-chip parameters stored in the parameter configuration circuit 700, outputs different control signals to control the operation of the quenching and reset control circuit 300, the counting mode control circuit 500, the stacked counter circuit 600, and the data preprocessing and storage circuit 900, respectively.

[0041] In one alternative implementation, such as Figure 6 As shown, the sensor control circuit 800 includes: a state machine circuit 810, a comparator circuit 820, and a counter circuit 830. The state machine circuit 810 receives an external enable pulse signal as input and its input terminal is connected to the output terminal of the comparator circuit 820. It outputs several control signals based on the external enable pulse signal and the control of the comparator circuit 820. The counter circuit 830 receives an input terminal connected to the output terminal of the state machine circuit 810 and is used to time the several control signals to obtain a time count value. The comparator circuit 820 receives an input terminal connected to the output terminal of the data storage circuit 730 and the counter circuit 830. It compares the external parameters stored in the data storage circuit 730 with the time count value to obtain a corresponding toggle signal, and controls the state machine circuit 810 through the corresponding toggle signal.

[0042] In one optional implementation, the control signals include: a counting mode control signal, an exposure enable control signal, a data readout control signal, and a data processing control signal; wherein, the counting mode control signal is used to control the counting mode of the counting mode control circuit 500; the exposure enable control signal is used to control the opening or closing of the single-photon detector array 100; the data readout control signal is used to control the opening and closing of the data readout function of the stacked counter circuit 600; and the data processing control signal is used to control the data preprocessing and storage circuit 900 to perform data processing and storage.

[0043] Specifically, the state machine circuit 810, under the control of the output signal of the comparator circuit 820, switches between different states of the chip, controlling the high and low levels of different signals in different states to achieve overall control of the sensor chip. Simultaneously, during each state switch, the counter circuit 830 is reset and restarted. The comparator circuit 820 compares the count value of the counter circuit 830 with stored external parameters and outputs corresponding control signals to control the state machine circuit 810 toggles. The counter circuit 830, essentially using a clock cycle as the smallest unit, is used to time the duration of different signals.

[0044] In an optional implementation, the data preprocessing and storage circuit 900 is used to reconstruct two-dimensional grayscale image data from the relative photon count values ​​obtained by the stacked counter circuit 600 through a process of data reconstruction, chained calculation, and data mapping, and then store the data. Simultaneously, the stored processed data can also be accessed by an external host computer.

[0045] In one alternative implementation, such as Figure 7 As shown, the data preprocessing and storage circuit 900 includes: a data read / write control and addressing circuit 910, a static random access memory (SRAM) circuit 920, a chain-like computing circuit 930, and a data mapping circuit 940. The data read / write control and addressing circuit 910 has its input connected to the output of the state machine circuit 810. It controls the stack-type counter circuit 600 to write the relative photon count values ​​to the SRAM circuit 920 according to control signals, and controls the reading order of the written relative photon count values. The SRAM circuit 920 has its inputs connected to the stack-type counter circuit. The output terminals of the data read / write control and addressing circuit 910 and 600 are used to store the relative values ​​of photon counts; the chain calculation circuit 930, with its input terminal connected to the output terminal of the static random access memory circuit 920, is used to read out the relative values ​​of photon counts and calculate the absolute values ​​of pulse counts based on the relative values ​​of photon counts; the data mapping circuit 940, with its input terminal connected to the output terminal of the chain calculation circuit 930 and its output terminal connected to the input terminal of the static random access memory circuit 920, is used to perform data mapping on the absolute values ​​of pulse counts to obtain incident light intensity information and write it to the static random access memory circuit 920.

[0046] Specifically, after a frame of imaging is completed, the state machine circuit 810 sends a corresponding control signal to the data read / write control and addressing circuit 910. Upon receiving this signal, the data read / write control and addressing circuit 910 controls the output data of the stack-type counter circuit 600 to be written into the corresponding address of the static random access memory circuit 920 according to a certain rule. After the data writing is completed, it controls the data to be read out in a certain order for data processing by the chain-like calculation circuit 930. The static random access memory circuit 920 is used for data storage, and the data stored within it can be read from outside the chip. Since the obtained raw data consists of the relative pulse count values ​​of any two adjacent pixels and the absolute pulse count values ​​of the first column of pixels, the chain-like calculation circuit 930 can perform addition and subtraction operations starting from the second column of pixels, obtaining the absolute pulse count values ​​of each pixel sequentially. Because there is a non-linear relationship between the absolute pulse count values ​​of the macropixels of the single-photon detector and the incident light intensity, the data mapping circuit 940 maps the absolute pulse count values ​​to obtain the incident light intensity data, which is then rewritten into the static random access memory circuit 920.

[0047] The present invention provides a readout circuit architecture for a two-dimensional image sensor suitable for single-photon detectors. By employing active quenching and active reset circuits, it reduces pixel dead time to improve the sensor's dynamic range. Simultaneously, it makes pixel dead time controllable and prevents metastability from causing pixel inactivation and dead time from encroaching on exposure time. The pulse output processing circuit combines multiple electrical pulses into a single macropixel, further reducing dead time and overcoming the limitation on the shortest dead time for a single device caused by pixel fill rate degradation, thus further improving the sensor's dynamic range. A stacked counter is used instead of a traditional binary digital counter, reducing the circuit area of ​​the counter array while maintaining the sensor's high dynamic range, thereby improving sensor resolution.

[0048] The readout circuit architecture of the two-dimensional image sensor applicable to single-photon detectors of the present invention, based on parameter configuration circuit, broadens the adjustable dynamic range and adjustable resolution, improves the flexibility of the two-dimensional image sensor, and enables it to support the dynamic range, resolution and frame rate requirements of various sensors. It has achieved significant optimization and improvement in both reliability and flexibility.

[0049] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0050] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A readout circuit architecture for a two-dimensional image sensor suitable for single-photon detectors, characterized in that, include: The circuit includes a single-photon detector array (100), an active quenching and active reset circuit (200), a quenching and reset control circuit (300), a pulse output processing circuit (400), a counting mode control circuit (500), a stacked counter circuit (600), an on-chip control circuit, and a data preprocessing and storage circuit (900). The single-photon detector array (100) includes: a plurality of single-photon detectors arranged in an array, each of the single-photon detectors receiving a single-photon signal, used to convert the single-photon signal into an electrical pulse; The pulse output processing circuit (400) has its input terminal connected to the output terminal of the single-photon detector array (100) and is used to compress the pulse width of the electrical pulse and merge several electrical pulses output by several single-photon detectors into one macro-pixel pulse signal. The counting mode control circuit (500) has its input terminal connected to the pulse output processing circuit (400), and includes several counting modes for inputting several macro pixel pulse signals into several stacked counter units of the stacked counter circuit (600) in several counting modes. The stacked counter circuit (600) includes several chain-connected stacked counter units, with its input terminal connected to the output terminal of the counting mode control circuit (500). It is used to obtain the relative photon count values ​​of any adjacent macro pixels based on the macro pixel pulse signal input by the counting mode control circuit (500). The stacked counter circuit (600) is also used to output the counting data to the data preprocessing and storage circuit (900) in the form of a shift register. The on-chip control circuit takes in an off-chip enable pulse signal and off-chip parameter data, and outputs several control signals according to the off-chip enable pulse signal and off-chip parameter data to control the operation of the quenching and reset control circuit (300), the counting mode control circuit (500), the stacked counter circuit (600) and the data preprocessing and storage circuit (900). The quenching and reset control circuit (300) has its input terminal connected to the output terminal of the single-photon detector array (100) and the on-chip control circuit, and is used to obtain controlled quenching and reset signals according to the electrical pulse and the control signal; The active quenching and active reset circuit (200) has its input terminal connected to the output terminal of the quenching and reset control circuit (300), and is used to control the quenching, reset and exposure enable states of the single-photon detector array (100) according to the quenching signal and the reset signal. The data preprocessing and storage circuit (900) has its input terminal connected to the output terminal of the stacked counter circuit (600) and the on-chip control circuit. It is used to obtain two-dimensional grayscale image data based on the relative value of the photon count, store the two-dimensional grayscale image data, and output it.

2. The readout circuit architecture for a two-dimensional image sensor suitable for a single-photon detector according to claim 1, characterized in that, The on-chip control circuit includes: a parameter configuration circuit (700) and a sensor control circuit (800), wherein, The parameter configuration circuit (700) inputs external parameter data and stores the external parameter data; the parameter configuration circuit (700) is also used to output the stored external parameter data to an external device for verification of the external parameter data. The sensor control circuit (800) receives an external enable pulse signal and its input terminal is connected to the output terminal of the parameter configuration circuit (700). It is used to output a number of control signals according to the stored external parameters and under the control of the external enable pulse signal, so as to control the operation of the quenching and reset control circuit (300), the counting mode control circuit (500), the stacked counter circuit (600), and the data preprocessing and storage circuit (900).

3. The two-dimensional image sensor readout circuit architecture suitable for single-photon detectors according to claim 1, characterized in that, The active quenching and active reset circuit (200) includes: a passive quenching circuit (210), an active quenching circuit (220), and an active reset circuit (230), wherein, The passive quenching circuit (210) is input with a fixed power supply potential and is used to initially control the quenching state of the single-photon detector array (100). The active quenching circuit (220) has its input terminal connected to the output terminal of the quenching and reset control circuit (300), and is used to control the quenching state of the single-photon detector array (100) according to the quenching signal and the reset signal respectively, and to stop the quenching state when the quenching state of the single-photon detector array (100) conflicts with its reset state. The active reset circuit (230) has its input terminal connected to the output terminal of the quenching and reset control circuit (300), and is used to control the single-photon detector array (100) to enter the working state according to the reset signal.

4. The readout circuit architecture for a two-dimensional image sensor suitable for a single-photon detector according to claim 2, characterized in that, The quenching and reset control circuit (300) includes: a quenching signal edge triggering circuit (310), a quenching signal pulse width control circuit (320), a reset signal edge triggering circuit (330), and a reset signal pulse width control circuit (340), wherein, The quenching signal edge triggering circuit (310) has its input terminals connected to the output terminals of the single-photon detector array (100), the quenching signal pulse width control circuit (320), and the sensor control circuit (800), respectively. It is used to detect the rising edge of the electrical pulse to obtain the quenching signal, and to control the high and low level states of the quenching signal according to the control signal, so as to realize the switching control of the single-photon detector array (100). The quenching signal pulse width control circuit (320) receives a first external voltage signal and is used to control the pulse width of the quenching signal according to the first external voltage signal. The reset signal edge triggering circuit (330) has its input terminals connected to the output terminals of the quenching signal edge triggering circuit (310) and the reset signal pulse width control circuit (340), respectively, and is used to detect the falling edge of the quenching signal to obtain the reset signal. The reset signal pulse width control circuit (340) receives a second external voltage signal and controls the pulse width of the reset signal according to the second external voltage signal.

5. The readout circuit architecture for a two-dimensional image sensor suitable for a single-photon detector according to claim 2, characterized in that, The counting mode control circuit (500) has its input terminal connected to the output terminal of the sensor control circuit (800) and is used to control its counting mode according to the control signal. The counting modes of the counting mode control circuit (500) include: left neighbor counting and right neighbor counting. Odd-numbered pixels are designated as fixed pixels. When counting left neighbors, the output of the fixed pixel and the even-numbered pixel to its left are connected to the same stacked counter unit. When counting right neighbors, the output of the fixed pixel and the even-numbered pixel to its right are connected to the same stacked counter unit.

6. The two-dimensional image sensor readout circuit architecture suitable for single-photon detectors according to claim 2, characterized in that, The stacked counter circuit (600) has its input terminal connected to the output terminal of the sensor control circuit (800) and is used to control the operating mode of each of the stacked counter units according to the control signal; the operating modes of each stacked counter unit include: reset, set, and relative counting.

7. The readout circuit architecture for a two-dimensional image sensor suitable for a single-photon detector according to claim 2, characterized in that, The parameter configuration circuit (700) includes: a serial-in parallel-out circuit (710), a parallel-in serial-out circuit (720), and a data storage circuit (730), wherein, The serial-in parallel-out circuit (710) inputs external parameters, including exposure time parameters, array size parameters, and dynamic range parameters, and is used to write the external parameters to the data storage circuit (730). The data storage circuit (730) has its input terminal connected to the output terminal of the serial-in parallel-out circuit (710), and its output terminal connected to the input terminals of the parallel-in serial-out circuit (720) and the sensor control circuit (800), respectively, for storing the off-chip parameters; The parallel-in serial-out circuit (720) is used to output the off-chip parameters stored in the data storage circuit (730) to the off-chip.

8. The two-dimensional image sensor readout circuit architecture for single-photon detectors according to claim 7, characterized in that, The sensor control circuit (800) includes: a state machine circuit (810), a comparator circuit (820), and a counter circuit (830), wherein, The state machine circuit (810) receives an external enable pulse signal and its input terminal is connected to the output terminal of the comparator circuit (820). It is used to output the plurality of control signals according to the external enable pulse signal and the control of the comparator circuit (820). The counter circuit (830) has its input terminal connected to the output terminal of the state machine circuit (810) and is used to time the plurality of control signals respectively to obtain a time count value; The comparator circuit (820) has its input terminal connected to the output terminal of the data storage circuit (730) and the counter circuit (830). It is used to compare the external parameters stored in the data storage circuit (730) with the time count value to obtain the corresponding flip signal, and control the state machine circuit (810) through the corresponding flip signal.

9. The two-dimensional image sensor readout circuit architecture for single-photon detectors according to claim 8, characterized in that, The plurality of control signals include: a counting mode control signal, an exposure enable control signal, a data readout control signal, and a data processing control signal; The counting mode control signal is used to control the counting mode of the counting mode control circuit (500); the exposure enable control signal is used to control the opening or closing of the single-photon detector array (100); the data readout control signal is used to control the opening and closing of the data readout function of the stacked counter circuit (600); and the data processing control signal is used to control the data preprocessing and storage circuit (900) to perform data processing and storage.

10. The two-dimensional image sensor readout circuit architecture for single-photon detectors according to claim 8, characterized in that, The data preprocessing and storage circuit (900) includes: a data read / write control and addressing circuit (910), a static random access memory circuit (920), a chain-like computing circuit (930), and a data mapping circuit (940), wherein, The data read / write control and addressing circuit (910) has its input terminal connected to the output terminal of the state machine circuit (810). It is used to control the stacked counter circuit (600) to write the relative value of the photon count to the static random access memory circuit (920) according to the control signal, and to control the reading order of the written relative value of the photon count. The static random access memory circuit (920) has its input terminals connected to the output terminals of the stacked counter circuit (600), the data read / write control and addressing circuit (910), and the data mapping circuit (940), respectively, and is used to store the relative value of the photon count. The chain-type calculation circuit (930) has its input terminal connected to the output terminal of the static random access memory circuit (920) for reading the relative value of the photon count and calculating the absolute value of the pulse count based on the relative value of the photon count. The data mapping circuit (940) has its input terminal connected to the output terminal of the chain calculation circuit (930) and is used to perform data mapping on the absolute value of the pulse count to obtain incident light intensity information and write it to the static random access memory circuit (920).

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