Storage and calculation integrated system-in-package stack-up structure and manufacturing method
By using a vertically stacked in-memory computing system-level packaging method, the problems of large chip area and long RDL traces in in-memory computing are solved, thereby reducing chip area and improving read and write speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-29
- Publication Date
- 2026-04-07
AI Technical Summary
Existing memory computing chip packages suffer from issues such as excessively large area and long RDL traces, which affect electrical performance and layout efficiency.
The system-in-package method for in-memory computing is adopted by vertical stacking. Eight LPDDR memory chips are vertically stacked on a carrier chip, supported by auxiliary pads. The CPU control chip and the LPDDR memory chips are vertically connected by wire bonding and packaged in a plastic package. RDL wiring layer and ball bearing are set to achieve interconnection.
It effectively reduces the overall chip area by 50%, shortens the RDL interconnect lines, and improves read and write speeds.
Smart Images
Figure CN121815667A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory packaging technology, specifically to a stacking and manufacturing method for a memory computing system-level package. Background Technology
[0002] Current LPDDR+CPU in-memory computing chip packaging products mainly use a hybrid package of conventional arc wire bonding and flip-chip, with the LPDDR chip positioned above the CPU chip. Furthermore, the input / output connections primarily involve die-to-die interconnects, which are then wire bonded to gold fingers, ultimately connecting the gold fingers to internal traces on the substrate and solder balls on the back of the substrate.
[0003] To meet the demands of AI, it is necessary to increase the number of I / O operations. A common solution is: 1. The bonding wires of all 8 stacked chips are wired to the organic substrate, replacing the interconnections between the chips. This wire bonding requires 4 or more layers of arc wires. The large number of wire layers and the excessive length of the wires make them prone to short circuits.
[0004] 2, such as Figure 1 As shown, CPU chip 2 is placed on the front of two stacks of LPDDR chips 1, while the vertical bonding wires form an interconnect with the flip chip. However, since there are two stacks of LPDDR chips 1, the overall chip area is relatively large, which is not conducive to the overall PCB layout. Also, due to the large overall chip area, the RDL traces are relatively long, which is detrimental to electrical performance.
[0005] Therefore, it is necessary to design a stacking and manufacturing method for in-memory computing system-in-package to solve the problems of large chip area and long RDL traces. Summary of the Invention
[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a stacking and manufacturing method for an in-memory computing system-in-package to solve the problems of large in-memory computing chip area and long RDL traces.
[0007] To achieve the above objectives, this invention provides a stacked architecture for an in-memory computing system-in-package, comprising a carrier chip, LPDDR memory chips, auxiliary pads, a CPU control chip, vertical wire bonding, a molding compound, RDL routing layers, and ball bearings. Eight LPDDR memory chips are vertically stacked on the carrier chip, with adjacent LPDDR chips staggered horizontally. An auxiliary pad is positioned below the protruding parts of the six LPDDR memory chips located between the top and bottom layers. The CPU control chip is positioned on the top LPDDR memory chip, with its protrusions facing upwards. The CPU control chip and the LPDDR memory chips are connected by vertical wire bonding. The LPDDR memory chips, CPU control chip, auxiliary pads, and vertical wire bonding are encapsulated within the molding compound, with the wire ends of the vertical wire bonding and the protrusions of the CPU control chip exposed outside the molding compound. Several RDL routing layers are positioned above the molding compound, connecting the wire ends of the vertical wire bonding to the protrusions of the CPU control chip. Ball bearings connected to the RDL routing are positioned above the RDL routing layers.
[0008] A PI dielectric layer is provided between the plurality of RDL wiring layers, and the material of the PI dielectric layer is polyimide.
[0009] The carrier chip is a carrier wafer or substrate that carries the entire package.
[0010] The vertical stitching is gold thread.
[0011] The material of the RDL wiring layer is copper, and the material of the ball is tin-silver alloy.
[0012] A stacked manufacturing method for a memory computing system-in-package as described in claim 1 includes the following steps: Step 1, with the bumps of the control chip CPU facing upwards, arrange 8 memory chips LPDDR and auxiliary pads; Step 2, attach the bottom layer memory chip LPDDR and auxiliary pads to the surface of the carrier chip according to the arrangement in Step 1; Step 3, sequentially attach the other 7 memory chips LPDDR and 5 auxiliary pads to the bottom layer memory chip LPDDR and auxiliary pads, and attach the control chip CPU to the top layer memory chip LPDDR; Step 4, perform vertical wire bonding on the exposed part of the memory chip LPDDR, and then encapsulate the memory chip LPDDR, control chip CPU, auxiliary pads, and vertical wire bonding; Step 5, grind the surface of the encapsulation body to expose the wire ends of the vertical bonding and the bumps of the control chip CPU; Step 6, complete the interconnection between the control chip CPU and the memory chip LPDDR using RDL technology; Step 7, place ball bearings on the topmost RDL wiring layer.
[0013] The specific positions of the eight LPDDR memory chips and auxiliary spacers are as follows: The top layer of LPDDR memory chips is arranged according to the size and position of the control chip CPU, and the positions of the other seven LPDDR memory chips and auxiliary spacers are determined according to the vertical wiring standard.
[0014] The plant bulbs are cut into individual pieces.
[0015] Compared with existing technologies, this invention designs a stacking structure and manufacturing method for in-memory computing system-in-package. By vertically stacking, the overall chip area is reduced by 50%, while shortening the RDL interconnect between the control chip CPU and the memory chip LPDDR, thereby improving the read and write speed of the in-memory computing chip. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the existing technology.
[0017] Figure 2 This is a schematic diagram of the structure of the present invention.
[0018] Figure 3 This is a schematic diagram of the manufacturing method of the present invention. Figure 1 .
[0019] Figure 4 This is a schematic diagram of the manufacturing method of the present invention. Figure 2 .
[0020] Figure 5 This is a schematic diagram of the manufacturing method of the present invention. Figure 3 .
[0021] Figure 6 This is a schematic diagram of the manufacturing method of the present invention. Figure 4 . Detailed Implementation
[0022] The present invention will now be further described with reference to the accompanying drawings.
[0023] See Figure 2This invention is a stacked architecture for a system-in-memory computing (SIMC) package, comprising a carrier chip, LPDDR memory chips, auxiliary pads, a CPU control chip, vertical wire bonding, a molding compound, an RDL wiring layer, and ball bearings. The carrier chip 11 is a carrier wafer or substrate that carries the entire package. Eight LPDDR3 memory chips are vertically stacked on the carrier chip 11, with adjacent LPDDR3 memory chips staggered horizontally. Auxiliary pads 12 are positioned below the protruding parts of the six LPDDR3 memory chips located between the top and bottom layers. These auxiliary pads 12 support the upper LPDDR3 memory chips and prevent them from breaking. A total of six auxiliary pads 12 are present. The CPU control chip 5 is mounted on the top LPDDR3 memory chip, with its bump 6 facing upwards. The bump 6 is the interface portion of the CPU control chip 5. The control chip CPU5 and the memory chip LPDDR3 are connected by vertical bonding wires 4, which are typically gold wires. The memory chip LPDDR3, control chip CPU5, auxiliary pad 12, and vertical bonding wires 4 are encapsulated within a plastic package 7, with the wire ends of the vertical bonding wires 4 and the bumps 6 of the control chip CPU5 exposed outside the plastic package 7. The plastic package 7 is made of non-conductive material and is used to protect the memory chip LPDDR3, control chip CPU5, auxiliary pad 12, and vertical bonding wires 4. Several RDL routing layers 8 are disposed above the plastic package 7, connecting the wire ends of the vertical bonding wires 4 to the bumps 6 of the control chip CPU5. The material of the RDL routing layers 8 is copper. A PI dielectric layer 9, a non-conductive dielectric layer made of polyimide, is disposed between the several RDL routing layers 8. Above the RDL routing layers 8 are ball bearings 10 connected to the RDL routing. The ball bearings 10 are used to connect the memory chip to the PCB and are made of tin-silver alloy.
[0024] A method for manufacturing a stacked architecture of an in-memory computing system-in-package includes the following steps: Step 1: With the bump 6 of the control chip CPU5 facing upwards, arrange the positions of the 8 LPDDR3 memory chips and the auxiliary pad 12.
[0025] The specific positions of the 8 LPDDR3 memory chips and auxiliary spacers 12 are as follows: The top layer of LPDDR3 memory chips is arranged according to the size and position of the control chip CPU5, and the positions of the other 7 LPDDR3 memory chips and auxiliary spacers 12 are determined according to the vertical wiring standard.
[0026] Step 2: Attach the bottom layer memory chip LPDDR3 and auxiliary pad 12 to the surface of the carrier chip 11 according to the arrangement in Step 1.
[0027] Step 3: On the bottommost LPDDR3 memory chip and auxiliary spacer 12, sequentially attach the other 7 LPDDR3 memory chips and 5 auxiliary spacers 12. Then, attach the control chip CPU5 on the topmost LPDDR3 memory chip. Figure 3 As shown.
[0028] Step 4: Perform vertical wire bonding 4 on the exposed portion of the LPDDR3 memory chip, then encapsulate the LPDDR3 memory chip, CPU control chip 5, auxiliary spacer 12, and vertical wire bonding 4. Figure 4 As shown.
[0029] Step 5: Grind the surface of the molded body flat to expose the wire ends of the vertical bonding wire 4 and the bumps 6 of the control chip CPU 5, such as... Figure 5 As shown.
[0030] Step 6: Use RDL technology to complete the interconnection between the control chip CPU5 and the memory chip LPDDR3, such as... Figure 6 As shown, this not only reduces the overall area because the RDL lines between the control chip CPU5 and the memory chip LPDDR3 are shortened, but also improves the read and write speed of the in-memory computing chip. The number of layers in RDL routing layer 8 is made according to actual needs. The layers of RDL routing layer 8 are separated by PI dielectric layer 9.
[0031] Step 7: Place the ball bearings 10 on the topmost RDL wiring layer 8, and cut the ball bearings 10 into individual pieces. The finished product looks like this. Figure 2 As shown.
[0032] This invention designs a stacking structure and manufacturing method for in-memory computing system-in-package. By vertically stacking, the overall chip area is reduced by 50%, while shortening the RDL interconnect between the control chip CPU and the memory chip LPDDR, thereby improving the read and write speed of the in-memory computing chip.
Claims
1. A stacked architecture for an in-memory computing system-in-package, comprising a carrier chip, an LPDDR memory chip, auxiliary pads, a CPU control chip, vertical wire bonding, a molding compound, an RDL wiring layer, and ball bearings, characterized in that: Eight LPDDR (3) memory chips are vertically stacked on the carrier chip (11). The two adjacent LPDDR (3) memory chips are staggered left and right. An auxiliary pad (12) is provided below the protruding part of the six LPDDR (3) memory chips located between the top and bottom layers. A control chip CPU (5) is provided on the top layer LPDDR (3) memory chip, and the protrusion (6) of the control chip CPU (5) faces upward. The control chip CPU (5) and the memory chip LPDDR (3) are connected by a vertical wire bonding (4). The memory chip LPDDR (3), the control chip CPU (5), the auxiliary pad (12), and the vertical wire bonding (4) are packaged in a plastic package (7), and the wire ends of the vertical wire bonding (4) and the bumps (6) of the control chip CPU (5) are exposed in the plastic package (7). Several RDL wiring layers (8) are provided on the top of the plastic package (7). The RDL wiring layers (8) connect the wire ends of the vertical wire bonding (4) and the bumps (6) of the control chip CPU (5). A ball (10) connected to the RDL wiring is provided on the top of the RDL wiring layers (8).
2. The stacked architecture of a memory computing system-level encapsulation according to claim 1, characterized in that: A PI dielectric layer (9) is provided between the plurality of RDL wiring layers (8), and the material of the PI dielectric layer (9) is polyimide.
3. The stacked architecture of a memory computing system-level encapsulation according to claim 1, characterized in that: The carrier chip (11) is a carrier wafer or substrate that carries the entire package.
4. The stacked architecture of a memory computing system-level encapsulation according to claim 1, characterized in that: The vertical beading (4) mentioned above is a gold thread.
5. The stacked architecture of a memory computing system-level encapsulation according to claim 1, characterized in that: The material of the RDL wiring layer (8) is copper, and the material of the ball (10) is tin-silver alloy.
6. A method for manufacturing a stacked architecture of a memory computing system-in-package as described in claim 1, characterized in that: The steps include: Step 1, with the bump (6) of the control chip CPU (5) facing upwards, arrange the positions of 8 memory chips LPDDR (3) and auxiliary pads (12); Step 2, according to the positions arranged in Step 1, attach the bottom layer memory chip LPDDR (3) and auxiliary pads (12) to the surface of the carrier chip (11); Step 3, on the bottom layer memory chip LPDDR (3) and auxiliary pads (12), sequentially attach the other 7 memory chips LPDDR (3) and 5 auxiliary pads (12), and attach the control chip to the top layer memory chip LPDDR (3). Step 4: Vertical wire bonding (4) is performed on the exposed part of the memory chip LPDDR (3). Then, the memory chip LPDDR (3), the control chip CPU (5), the auxiliary pad (12), and the vertical wire bonding (4) are encapsulated. Step 5: The surface of the encapsulation body is ground flat to expose the wire ends of the vertical wire bonding (4) and the bumps (6) of the control chip CPU (5). Step 6: The interconnection between the control chip CPU (5) and the memory chip LPDDR (3) is completed using RDL process. Step 7: Balls (10) are placed on the topmost RDL wiring layer (8).
7. The stacked manufacturing method of a memory computing system-level package according to claim 6, characterized in that: The specific positions of the eight LPDDR (3) memory chips and the auxiliary pads (12) are as follows: The top layer of memory chip LPDDR (3) is arranged according to the size and position of the control chip CPU (5), and the positions of the other seven LPDDR (3) memory chips and the auxiliary pads (12) are determined according to the standard of vertical wiring.
8. The stacked manufacturing method of a memory computing system-in-package according to claim 6, characterized in that: The planted bulb (10) is cut into individual pieces.