Preparation method of junction barrier Schottky diode based on chemical mechanical polishing

Abstract

The invention provides a junction barrier Schottky diode preparation method based on chemical mechanical polishing, and belongs to the technical field of Schottky diode manufacturing, and the method comprises the steps: preparing an anode layer on the epitaxial layer side of a gallium oxide wafer, and enabling the hardness of the outer side of the anode layer to be higher than that of the epitaxial layer of the gallium oxide wafer; enabling the surface of the anode layer to be in close fit contact with a flexible polishing pad, and enabling the polishing pad to be squeezed into a gap of the anode layer and to be in contact with the surface of the epitaxial layer; and along with the rotation of the polishing pad, the polishing pad squeezed into the gap of the anode layer polishes the epitaxial layer through a polishing solution so as to form a groove corresponding to the gap, and then the gallium oxide device is obtained. The trench is manufactured in a chemical mechanical polishing mode, the problems that the number of lattice defects on the surface of the trench is large, the control difficulty of the morphology and roughness of the side wall of the trench is large, and impurities and defects are likely to be introduced are solved, the performance of a device is not affected in the trench forming process, the yield of the junction barrier Schottky diode can be effectively increased, and the preparation cost of the device is reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of Schottky diode manufacturing, and more particularly to a junction barrier Schottky diode preparation method based on chemical mechanical polishing. BACKGROUND

[0002] Power semiconductors play an important role in power systems and are key devices for power control and conversion, and are widely used in important fields such as aerospace, energy, and communication. Gallium oxide (Ga2O3) is a kind of ultra-wide bandgap semiconductor material, which has attracted more and more attention from the scientific research community and the industry in recent years. Compared with the third-generation semiconductors gallium nitride (GaN) and silicon carbide (SiC), Ga2O3 material has an ultra-wide bandgap (~4.8 eV) and an ultra-high critical breakdown field strength (~8 MV / cm), and the Baliga figure of merit (BFOM) is 4 times that of GaN material, 10 times that of SiC material, and 3444 times that of Si material. Under the same withstand voltage condition, Ga2O3-based power devices have smaller on-resistance and are very suitable for semiconductor materials applied in high-voltage and high-power fields. In addition, high-quality Ga2O3 single crystal substrate material can be mass-produced by a melting method, which will have more advantages in cost than SiC and GaN materials in the future.

[0003] Junction barrier Schottky diode (JBS) overcomes the shortcomings of traditional low breakdown voltage and high reverse leakage current, and combines the advantages of pn diode, and is an ideal rectifier with high voltage resistance and high speed, which has a wide application in high-frequency power systems.

[0004] The preparation of gallium oxide JBS diode is often through selective inductively coupled plasma etching (ICP etching) trench, which is a process combining physical bombardment and chemical reaction. The application of selective inductively coupled plasma etching has the following defects: first, a large number of lattice defects are generated on the surface of the epitaxial layer, which will become traps for charge carriers, significantly increase the leakage current of the device, reduce the mobility of electrons in the epitaxial layer, and thus increase the on-resistance of the device; after the P-type material is grown in the trench, the breakdown characteristics of the device will also be affected. Second, it is easy to have problems such as sidewall tilting, poor sidewall roughness control, and uneven trench profile, which affect the electrical performance and reliability of the device. Third, ICP etching needs to use a mask, which not only etches gallium oxide, but also inevitably etches the mask material, causing the size of the trench to deviate from the design value. Fourth, the material sputtered out during the etching process is easy to deposit in the trench, introducing impurities and defects and causing the crystal quality to decrease. Fifth, high-purity industrial special gases and other materials are continuously consumed during the etching process, which is costly.

[0005] It can be seen that the selective inductively coupled plasma etching has the problems of many surface lattice defects, difficulty in controlling the morphology and roughness of the trench sidewall, easy introduction of impurities and defects, and high cost, which adversely affect the performance and preparation cost of the device. SUMMARY

[0006] The application aims to provide a junction barrier Schottky diode preparation method based on chemical mechanical polishing, and aims to solve the problems of the technology of forming a trench by selective inductively coupled plasma etching, such as many surface lattice defects, difficulty in controlling the morphology and roughness of the trench sidewall, easy introduction of impurities and defects, and high cost, which adversely affect the performance and preparation cost of the device.

[0007] To achieve the above object, the technical scheme adopted by the application is: The application provides a junction barrier Schottky diode preparation method based on chemical mechanical polishing, comprising the following steps: The epitaxial layer side of the gallium oxide wafer has a plurality of chip functional areas, and an anode layer is prepared on the epitaxial layer side of each chip functional area, and the hardness of the outside of the anode layer is higher than that of the epitaxial layer of the gallium oxide wafer; The surface of the anode layer is tightly contacted with a flexible polishing pad, the polishing pad is squeezed into the gap of the anode layer in the same chip functional area, and the surface of the epitaxial layer is contacted; With the rotation of the polishing pad, the polishing pad squeezed into the gap of the anode layer grinds the epitaxial layer through the polishing liquid to form a trench corresponding to the gap, so that the chip functional area forms a gallium oxide device.

[0008] Compared with the prior art, the scheme shown in the application embodiment has the following advantages: the hardness of the anode layer is large, and the anode layer will not be removed during polishing. During polishing, the polishing pad squeezed into the gap of the anode layer cooperates with the polishing liquid to grind the epitaxial layer with low hardness at an appropriate speed, while the anode layer metal is not affected.

[0009] The application has the following beneficial effects by using the chemical mechanical polishing process to manufacture the trench: First, chemical mechanical polishing is a process dominated by chemical corrosion and assisted by mechanical grinding. It softens and removes materials through a mild chemical reaction, and does not involve high-energy particle bombardment at all. Therefore, the trench surface and sidewall formed by polishing can maintain the complete crystal structure, and the problem of many trench surface lattice defects is improved, and the performance degradation caused by etching damage is avoided from the source.

[0010] Second, the essential goal of the chemical mechanical polishing process is to achieve global planarization and super-smooth surface, therefore, the bottom and sidewall of the trench formed by chemical mechanical polishing can achieve high smoothness. This provides an ideal interface for subsequent epitaxial growth of P-type heterojunction, helps to reduce interface state density, improve the quality and reliability of the junction, and avoid affecting the breakdown characteristics of the device.

[0011] Third, the selected area of chemical mechanical polishing is realized by the protection of the anode layer material with high hardness. The removal rate of the polishing liquid for the anode layer and the gallium oxide wafer epitaxial layer is very different. As long as the anode layer is strong enough, the polishing process will stop precisely at the edge of the anode layer, thereby achieving precise pattern fidelity and critical dimension control. The shape of the trench is completely determined by the pattern of the anode layer.

[0012] Fourth, chemical mechanical polishing is a continuous "dissolution-flow-removal" process. The reaction products are continuously removed by the flowing polishing liquid, and there is no redeposition problem, which ensures the cleanliness of the trench and avoids introducing new impurities and defects, ensuring the quality of the crystal.

[0013] Fifth, the consumables such as polishing pad and polishing liquid used in the chemical mechanical polishing process are low in cost and low in equipment complexity, which can significantly improve the economic benefits. At the same time, the chemical mechanical polishing process provides a global and predictable material removal method, which can accurately control how much material is polished, thereby ensuring the accuracy of the trench size and the flatness of the trench surface. The process quality is controllable, which is also conducive to reducing the production cost of the device and improving the economic benefits. In summary, by using chemical mechanical polishing to manufacture the trench, the problems of many lattice defects on the surface of the trench, difficulty in controlling the morphology and roughness of the trench sidewall, and easy introduction of impurities and defects are effectively avoided. The process of trench forming does not affect the performance of the device, which can effectively improve the yield of the junction barrier Schottky diode, and is also conducive to reducing the production cost of the device and improving the economic benefits.

[0014] In one possible implementation, the pressure between the polishing pad and the anode layer is , the removal rate of the epitaxial layer is , the is proportional to the .

[0015] In one possible implementation, the rotation speed of the polishing pad is , the removal rate of the epitaxial layer is , the is proportional to the .

[0016] In one possible implementation, the polishing pad is one of a damping cloth polishing pad, a non-woven cloth polishing pad, and a fabric polishing pad.

[0017] In a possible implementation, the depth of the trench is 100 nm to 3 μm.

[0018] In a possible implementation, the anode layer comprises a first anode metal layer and a second anode metal layer, the first anode metal layer is located between the second anode metal layer and the epitaxial layer. The hardness of the second anode metal layer is higher than that of the epitaxial layer, and the first anode metal layer forms a Schottky contact with the epitaxial layer.

[0019] In a possible implementation, before the anode layer is prepared on the side of the epitaxial layer of the gallium oxide wafer, the method further comprises: A cathode layer is prepared on the side of the substrate layer of the gallium oxide wafer.

[0020] In some embodiments, before the outer side surface of the anode layer is brought into close contact with the polishing pad, the method further comprises: The side of the cathode layer away from the gallium oxide wafer is adhered to a carrier table; The gallium oxide wafer is moved downwardly towards the polishing pad until the anode layer is in close contact with the polishing pad.

[0021] In a possible implementation, after the gallium oxide device is obtained, a heterojunction material is grown in the trench.

[0022] In some embodiments, after the heterojunction material is grown in the trench, the method further comprises: A metal electrode layer is prepared on the surface layer of the heterojunction material and the surface layer of the epitaxial layer, so as to form an ohmic contact between the heterojunction material and the epitaxial layer. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0024] Figure 1 Step one of the junction barrier Schottky diode preparation method based on chemical mechanical polishing provided by the embodiments of the present application; Figure 2 Step two of the junction barrier Schottky diode preparation method based on chemical mechanical polishing provided by the embodiments of the present application; Figure 3Step three of the preparation method of the junction barrier Schottky diode based on chemical mechanical polishing provided by the embodiment of the present application; Figure 4 Step four of the preparation method of the junction barrier Schottky diode based on chemical mechanical polishing provided by the embodiment of the present application; Figure 5 Step five of the preparation method of the junction barrier Schottky diode based on chemical mechanical polishing provided by the embodiment of the present application; Figure 4 Figure 6 Step six of the preparation method of the junction barrier Schottky diode based on chemical mechanical polishing provided by the embodiment of the present application; Figure 7 Step seven of the preparation method of the junction barrier Schottky diode based on chemical mechanical polishing provided by the embodiment of the present application. Figure 8 In the figure: 100, gallium oxide wafer; 110, epitaxial layer; 120, substrate layer; 200, anode layer; 210, first anode metal layer; 220, second anode metal layer; 300, polishing pad; 310, protruding part; 400, gap; 500, groove; 600, cathode layer; 700, polishing liquid; 800, metal electrode layer; 900, heterojunction material. DETAILED DESCRIPTION

[0025] In order to make the technical problems, technical solutions and beneficial effects of the present application clearer, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0026] It should be noted that when an element is referred to as "disposed on" another element, it can be directly on the other element or indirectly on the other element. It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0027] It should be noted that when an element is referred to as "disposed on" another element, it can be directly on the other element or indirectly on the other element. It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0028] ​The terms "first", "second", etc. are used only for descriptive purposes and are not to be construed as indicating or implying relative importance or an indicated number of features. Thus, a feature defined with "first", "second" can explicitly or implicitly include one or several of the features. In the description of the present application, the meaning of "several" is two or more, unless otherwise explicitly and specifically limited.

[0029] The reasons for the defects of the existing scheme of using selected area inductively coupled plasma etching trench are as follows: First, high-energy ion bombardment can cause the atomic bonds on the surface of gallium oxide to break, resulting in point defects such as vacancies and interstitial atoms, and even forming an amorphous layer. During the etching process, the removal rates of gallium and oxygen atoms can be different, causing the surface stoichiometric ratio to deviate from Ga2O3, forming a gallium-rich or oxygen-rich layer.

[0030] These lattice defects can become traps for charge carriers, significantly increasing the leakage current of the device; defects can scatter carriers, reducing the mobility of electrons in the epitaxial layer, thereby increasing the on-resistance of the device. The subsequent growth of P-type material in the trench will form a heterojunction with this damaged surface, and the defects at the interface will become recombination centers, reducing the minority carrier lifetime and possibly affecting the breakdown characteristics of the junction.

[0031] Second, during the trench forming process, it is an ideal goal to obtain vertical and smooth sidewalls, but it is difficult to achieve in the etching forming process. Improper control of etching process parameters (such as pressure, bias power) can cause the sidewall to appear forward or reverse tilt (i.e. sidewall tilt); microscopically rough sidewalls can increase the surface area, potentially creating defects during the subsequent growth of P-type material, and causing electric field concentration, reducing the breakdown voltage of the device; etching can produce a "fence" effect or an uneven bottom, affecting the performance and uniformity of the device. These non-ideal sidewall morphologies will directly affect the electrical performance and reliability of the device.

[0032] Third, ICP etching requires a mask (such as photoresist, metal or dielectric hard mask), and during the etching process, not only the gallium oxide will be etched, but also the mask material will be inevitably etched. If the etching rate of the mask material is similar to that of gallium oxide (low selectivity), then by the time the etching reaches the desired depth, the mask may have been completely consumed or severely thinned, failing to effectively protect the non-etching area. Furthermore, the erosion of the edges of the mask can cause the etching pattern to deform, the size of the trench top to deviate from the design value, and affect the integration density and performance of the device.

[0033] Fourth, the materials sputtered out during the etching process (including gallium oxide and mask material) may not be immediately pumped away by the vacuum system, but instead redeposited on the sidewalls or bottom of the trench. The deposits can hinder the vertical progress of etching, causing the etching to stop, and the deposits can become nucleation centers during the subsequent growth of P-type material, leading to a decrease in crystal quality.

[0034] Fifth, the etching needs to continuously consume high-purity industrial special gas, the vacuum system, the radio frequency power supply, the conveying system consume high energy, and the material and power cost is high, which is not conducive to the economic benefits of gallium oxide.

[0035] To solve the above problems, the application provides a junction barrier Schottky diode preparation method based on chemical mechanical polishing. Figures 1 to 8 The application provides a junction barrier Schottky diode preparation method based on chemical mechanical polishing. The initial state of the gallium oxide wafer 100 is shown in Figure 1 The epitaxial layer side of the gallium oxide wafer 100 has a plurality of chip functional areas, and an anode layer 200 is prepared on the epitaxial layer side of each chip functional area (as shown in Figure 3 The hardness of the outside of the anode layer 200 is higher than that of the epitaxial layer 110 of the gallium oxide wafer 100. The surface of the anode layer 200 is tightly contacted with the flexible polishing pad 300, the polishing pad 300 is squeezed into the gap 400 of the anode layer 200 in the same chip functional area, and the surface of the epitaxial layer 110 is contacted, as shown in Figure 4 . With the rotation of the polishing pad 300, the polishing pad 300 squeezed into the gap 400 of the anode layer 200 grinds the epitaxial layer 110 through the polishing liquid 700 to form a groove 500 corresponding to the gap 400 (as shown in Figure 6 ), so as to form a gallium oxide device in the chip functional area.

[0036] In this embodiment, in order to facilitate manufacturing, a plurality of chip functional areas are arranged on a single gallium oxide wafer 100, each chip functional area corresponds to a gallium oxide device, and finally a single device is obtained by means of dicing.

[0037] In this embodiment, the gallium oxide wafer 100 is wafer, which comprises a substrate layer 120 and an epitaxial layer 110, the substrate layer 120 is a heavily doped substrate containing , and the epitaxial layer 110 contains .

[0038] In this embodiment, the polishing pad 300 is not absolutely rigid, but has a certain softness and elasticity, which enables the polishing pad 300 to be micro-deformed when subjected to pressure. The wafer surface has a convex anode layer 200 and a concave gap 400 region, and the polishing pad 300 is pressed to this uneven surface under pressure. Under the action of the downward pressure applied, the relatively soft polishing pad 300 is forced to elastically deform like a memory sponge, extruding and extending to the concave gap 400 region, forming a micro-scale mechanical compliance and filling, forming Figure 4 With Figure 5 The convex part 310 shown in the figure is filled in the gap 400.

[0039] After such deformation, the polishing pad 300 not only maintains close contact with the surface of the convex anode layer 200, but also makes contact with the surface of the epitaxial layer 110 with the part extruded into the gap 400. When the wafer and the polishing pad 300 move relatively, the polishing liquid 700 impregnated in the polishing pad 300 can act on the surface of the epitaxial layer 110 and the surface of the anode layer 200, thereby achieving polishing of the epitaxial layer 110.

[0040] In this embodiment, the "hardness" refers to the Mohs hardness.

[0041] The preparation method of the junction barrier Schottky diode based on chemical mechanical polishing provided in the application has the following advantages compared with the prior art: Since the hardness of the anode layer 200 is large, it will not be removed during polishing. During polishing, the polishing pad 300 extruded into the gap 400 of the anode layer 200 cooperates with the polishing liquid 700 to polish the epitaxial layer 110 with low hardness at an appropriate speed, without affecting the metal of the anode layer 200.

[0042] The application has the following beneficial effects by using the chemical mechanical polishing process to manufacture the trench 500: First, chemical mechanical polishing is a process dominated by chemical corrosion and assisted by mechanical grinding. It softens and removes materials through a mild chemical reaction, and does not involve high-energy particle bombardment at all. Therefore, the surface and sidewall of the trench 500 formed by polishing can maintain an intact crystal structure, improve the problem of many lattice defects on the surface of the trench 500, and avoid performance degradation caused by etching damage from the source.

[0043] Second, the essential goal of the chemical mechanical polishing process is to achieve global planarization and super-smooth surface. Therefore, the bottom and sidewall of the trench 500 formed by chemical mechanical polishing can achieve high smoothness. This provides an ideal interface for subsequent epitaxial growth of P-type heterojunction, helps to reduce interface state density, improve the quality and reliability of the junction, and avoid affecting the breakdown characteristics of the device.

[0044] Third, the selective area of the chemical mechanical polishing is realized by the protection of the material of the anode layer 200 with higher hardness, and the removal rate of the polishing liquid 700 to the anode layer 200 and the epitaxial layer 110 of the gallium oxide wafer 100 is very large. As long as the anode layer 200 is strong enough, the polishing process will stop precisely at the edge of the anode layer 200, so as to realize precise pattern fidelity and critical dimension control, and the shape of the trench 500 is completely determined by the pattern of the anode layer 200.

[0045] Fourth, the chemical mechanical polishing is a continuous "dissolution-flow-removal" process, and the reaction products will be continuously removed by the flowing polishing liquid 700, and there is no problem of redeposition, which ensures the cleanliness in the trench 500 and avoids introducing new impurities and defects, and the crystal quality is ensured.

[0046] Fifth, the consumables such as polishing pad and polishing liquid used in the chemical mechanical polishing process are low in cost and low in equipment complexity, which can significantly improve the economic benefits. At the same time, the chemical mechanical polishing process provides a global and predictable material removal method, which can accurately control how much material is polished, so as to ensure the accuracy of the size of the trench 500 and the flatness of the surface of the trench 500, and the process quality is controllable, which is also beneficial to reduce the production cost of the device and improve the economic benefits.

[0047] In summary, by the way of chemical mechanical polishing to manufacture the trench 500, the problems of many lattice defects on the surface of the trench 500, difficulty in controlling the morphology and roughness of the sidewall of the trench 500, and easy to introduce impurities and defects are effectively avoided. The process of forming the trench 500 does not affect the performance of the device, which can effectively improve the yield of the junction barrier Schottky diode, and is also beneficial to reduce the production cost of the device and improve the economic benefits.

[0048] In some embodiments, the polishing pad 300 is selected to be a flexible polishing pad 300 such as a damping cloth polishing pad 300, a non-woven fabric polishing pad 300, and a fabric polishing pad 300. The flexible polishing pad 300 can ensure that the polishing pad 300 can enter the gap 400 of the anode layer 200 and tightly adhere to the epitaxial layer 110.

[0049] Optionally, the polishing liquid 700 is selected as a nano-silica sol polishing liquid. The SiO2particles in the nano-silica sol are spherical, monodisperse and uniform in size. During polishing, the SiO2particles "roll" or "slide" rather than "shave" like irregular abrasives. This action mode can effectively remove material while greatly reducing surface scratches, cracks and damage. In addition, the nano-silica sol particles are small in size (as low as tens of nanometers) and narrow in distribution. The nano-silica sol particles can uniformly act on the high and low points on the wafer surface. The high points are subjected to greater pressure and are softened and removed at a faster rate, while the low points are hardly affected. Through this selective removal, a nanoscale or even atomic scale highly flat surface can be ultimately achieved.

[0050] In some embodiments, the pressure between the polishing pad 300 and the anode layer 200 is , and the removal rate of the epitaxial layer 110 is , and are directly proportional. Optionally, the pressure ranges from 25 g / cm 2 to 300 g / cm 2 , for example, 50 g / cm 2 , 100 g / cm 2 , 150 g / cm 2 , 200 g / cm 2 , 250 g / cm 2 .

[0051] Chemical mechanical polishing is a combination of chemical action of the polishing liquid 700 and mechanical friction of the polishing pad 300 to remove material. The pressure is , and the removal rate is . The effect of the pressure on the removal rate is as follows: First, the flexible polishing pad 300 is squeezed into the gap 400 between the anode layers 200 and directly contacts the epitaxial layer 110 to be removed. This means that the effective pressure of the exposed epitaxial layer 110 area is relatively high, so that the polishing pad 300 can form very close and microscopic contact with the surface of the epitaxial layer 110. The greater the pressure , the closer and more complete the microscopic contact, and the stronger the shearing and scraping action of the polishing pad 300 on the surface of the epitaxial layer 110, directly improving the mechanical removal rate.

[0052] Secondly, the polishing liquid 700 usually contains chemical etchants (for softening the material) and abrasive particles (such as silicon dioxide, cerium oxide, etc., for mechanical scraping). The increase of pressure P forces more polishing liquid 700 into the tiny gap between the polishing pad 300 and the epitaxial layer 110, and more abrasive particles participate in cutting and rolling, directly increasing the mechanical removal rate. Moreover, the chemical etchants can reach the reaction interface faster, and the reaction products can be carried away faster, maintaining a high chemical reaction rate.

[0053] Thirdly, when the polishing pad 300 rotates, it has a relative speed with the wafer surface. The applied pressure P is directly converted into the normal force between the polishing pad 300 and the epitaxial layer 110, and according to the principle of tribology, the friction force (i.e., shear force) is proportional to the normal force, so under the condition that other conditions (such as rotation speed, polishing liquid concentration, temperature) remain unchanged, the removal rate is naturally proportional to the pressure P.

[0054] It should also be noted that the pressure P is also related to the surface quality of the groove 500. If the polishing pad 300 is excessively squeezed (i.e., the pressure P is too large), micro scratches, micro cracks and broken layers will be generated on the surface of the groove 500 by the polishing pad 300 itself and the large particles in the polishing liquid 700 entrained, seriously damaging the surface quality. If the polishing pad 300 cannot be fully squeezed into the gap 400 of the anode layer 200 (i.e., the pressure P is too small), the normal pressure and shear force acting on the surface of the epitaxial layer 110 are insufficient, forming a groove 500 with uneven surface and high roughness, resulting in poor surface finish of the groove 500.

[0055] It can be seen that by reasonably adjusting the pressure P between the polishing pad 300 and the anode layer 200, the removal rate of the epitaxial layer 110 can be accurately controlled to be , and the surface flatness of the groove 500 can also be effectively controlled. In some embodiments, the rotation speed of the polishing pad 300 is , and the removal rate of the epitaxial layer 110 is , proportional to the rotation speed . The rotation speed ranges from 20 r / min to 200 r / min, for example, 40 r / min, 80 r / min, 120 r / min, 160 r / min, 180 r / min.

[0056] Chemical mechanical polishing is a combination of the chemical action of the polishing liquid 700 and the mechanical friction of the polishing pad 300 to remove material, and the rotation speed of the polishing pad 300 is proportional to the removal rate.​ The impact is as follows: First, the relative speed between the polishing pad 300 and the epitaxial layer 110 surface of the gallium oxide wafer 100 increases, resulting in an increase in the rate of friction (shear force) acting on the epitaxial layer 110 surface. It can be understood that, in a unit of time, more polishing pad 300 fibers and abrasive particles are "scraped" from the epitaxial layer 110 surface. Each friction and scraping can remove a small amount of material. The rotation speed increases, meaning that the number of times of friction and scraping in a unit of time is roughly doubled, thereby directly leading to a proportional increase in the total amount of material removed in a unit of time (i.e., the removal rate ).

[0057] Second, higher rotation speed can generate stronger centrifugal force and shear force, which can more quickly and effectively transport fresh polishing liquid 700 to the contact area between the polishing pad 300 and the epitaxial layer 110, especially those parts squeezed into the gap 400 of the anode layer 200. Fresh polishing liquid 700 contains unspent chemical corrosion agents, which can continuously react with the epitaxial layer 110 surface to soften it or generate a softened layer that is easily removed by mechanical action. In addition, high-speed rotation can timely throw away the by-products generated by the reaction and the debris that have been ground off from the processing area, preventing them from accumulating in the gap 400 and causing the polishing pad 300 to be passivated or scratch the surface.

[0058] It should also be noted that the rotation speed is also related to the surface quality of the groove 500. The rotation speed not only linearly increases the material removal rate , but also deeply affects the surface flatness, micro roughness, and defect number of the groove 500 by controlling the interfacial friction heat, fluid dynamics, and reaction time. Too low rotation speed may lead to uneven material removal and passivation contamination; too high rotation speed may lead to unstable fluid dynamics, introducing scratches and tremor marks.

[0059] As can be seen, by reasonably adjusting the rotation speed of the polishing pad 300 to , the removal rate of the epitaxial layer 110 can be accurately controlled to , and the surface flatness of the groove 500 can also be effectively controlled.

[0060] In order to improve production efficiency, a batch of experimental wafers can be prepared first, and the removal rate is experimented on the experimental wafers, and according to the experimental results, each experimental parameter (mainly the pressure and the rotation speed These experimental parameters can be adjusted and then directly applied to the actual production process, reducing the need for parameter adjustments and improving the yield rate. An example of the experimental method is as follows: A pressure was fixed on a batch of experimental wafers. Then change the speed (For example, take multiple points from low to high), and measure the removal rate corresponding to each point. ; On a batch of experimental wafers, a fixed rotation speed was established. Then change the pressure Measure the removal rate at each point. ; Based on the two sets of data above, a graph was drawn. and (when (when fixed) and and (when The relationship curve (when fixed) is used to determine the process window; Using the above data, through the formula Calculate the Preston coefficient under specific process conditions (specific polishing fluid, polishing pad, temperature). ; Establish a mathematical model: This provides a quantitative basis for precise control.

[0061] In mathematical models Based on this, the removal rate can be flexibly and precisely adjusted according to different production goals. Examples of regulatory strategies are as follows: Strategy 1: Coarse Adjustment and Fine Adjustment Change pressure This usually results in a significant and linear change in the removal rate. However, when a large adjustment is needed... When (e.g., when the total polishing time needs to be adjusted between different batches due to differences in epitaxial layer thickness), prioritize adjusting the pressure. More efficient. That is, by changing the pressure. Achieve coarse adjustment.

[0062] Rotation speed control is typically very precise and stable. Fine-tuning of the rotation speed is used when precise adjustments are needed to compensate for minor process variations or to achieve extremely high groove depth uniformity. It's a better choice. By changing the pressure... After completing the coarse adjustment, change the speed. Make minor adjustments.

[0063] Strategy 2: Constant Rate Control Suppose the removal rate needs to be stabilized at a target value , according to the process model , set the initial combination of and . This combination should be in the safe region of the process window, avoiding too high pressure or rotation speed leading to defects. In actual production, if the real-time deviates from

[0064] , the following two types of solutions appear: If the deviation is small, fine-tune , for example, slightly lower than the target, then slightly increase in proportion. If the deviation is large, it may be necessary to adjust to quickly correct, and then use

[0065] to fine-tune. Strategy three: optimize process results (uniformity and defect control) Accurate control not only controls the rate, but also controls the quality.

[0066] and have different effects on polishing uniformity and surface defects, and need to be weighed. When pursuing better intra-wafer uniformity, the pressure needs to be appropriately reduced to avoid high pressure leading to inconsistent deformation of the flexible polishing pad 300 at the center and the outer edge of the wafer, resulting in non-uniform problems. To compensate for the reduced

[0067] due to pressure reduction, the rotation speed can be increased proportionally. Since the effect of rotation speed is usually more uniform globally, this helps to improve the consistency of the trench 500 depth while maintaining the target removal rate. When pursuing lower surface defects, the rotation speed needs to be appropriately reduced because the impact and friction of abrasive particles and reaction byproducts in the polishing liquid 700 on the surface are more intense at high rotation speeds, which may increase the risk of scratches. To compensate for the reduced

[0068] due to speed reduction, the pressure can be increased proportionally. In some embodiments, the depth of the trench 500 is 100 nm to 3 μm (e.g., 150 nm, 500 nm). Reasonable control of the trench 500 depth has the following beneficial effects:

[0069] In some embodiments, the depth of the trench 500 is 100 nm to 3 μm (e.g., 150 nm, 500 nm). Reasonable control of the trench 500 depth has the following beneficial effects: ​First, as a kind of ultra-wide bandgap semiconductor, the application target of gallium oxide is high voltage. The depth of the trench 500 directly determines the shape and strength of the electric field. The trench 500 must be deep enough (for example, ≥ 100 nm) to effectively modulate the electric field at the anode edge. A deeper trench 500 can push the electric field peak from the surface of the metal-semiconductor contact to the inside of the body material, avoiding premature breakdown at the surface. A too deep trench 500 (for example, > 3 μm) will reduce the effective thickness of the drift region, to some extent, limit the increase of the breakdown voltage, and will unnecessarily increase the on-resistance of the device. In preparation, a too deep trench 500 requires a longer polishing time, increases the process difficulty and cost, and may affect the morphology and quality of the trench 500 sidewall. Therefore, this depth range is the key to achieving the best balance between high breakdown voltage and low on-resistance.

[0070] Second, the core of the junction barrier Schottky diode is the "junction barrier", which is usually realized by ion implantation to form a p-type region on the sidewall and bottom of the trench 500, and the depth of the trench 500 directly affects the formation and quality of the junction. A depth of more than 100 nm provides enough space for ion implantation to form a p-type region with sufficient longitudinal size and uniform concentration, thereby building an effective junction barrier to effectively suppress the lowering of the Schottky barrier. If the trench 500 is too shallow, high-energy ion implantation may damage the lattice at the bottom of the trench 500, and even affect the underlying drift layer, introducing too many defects, which become a leakage current channel and a reliability risk. A moderate depth provides a buffer interval for implantation damage, and the subsequent annealing process can also more effectively repair defects.

[0071] Third, if the target depth is less than 100 nm, the process window is too narrow, and it is easy to cause insufficient polishing (the trench 500 is too shallow) due to slight process fluctuations, and an effective electric field termination cannot be formed. If the target depth is greater than 3 μm, the polishing time is too long, not only the efficiency is low, but also the wear of the polishing pad 300 and the consumption of the polishing liquid 700 are great. More importantly, long-time polishing may cause the trench 500 in some areas to penetrate the epitaxial layer 110 due to uniformity problems, causing device short circuit failure. Therefore, reasonable design of the depth of the trench 500 can effectively ensure the process feasibility and yield.

[0072] In some embodiments, referring to Figures 3 to 8The anode layer 200 comprises a first anode metal layer 210 and a second anode metal layer 220, the first anode metal layer 210 is located between the second anode metal layer 220 and the epitaxial layer 110; the hardness of the second anode metal layer 220 is higher than that of the epitaxial layer 110; the first anode metal layer 210 forms a Schottky contact with the epitaxial layer 110. The second anode metal layer 220 has high hardness and good adhesion, and will not be removed during polishing, so that the polishing process basically removes only the exposed epitaxial layer 110, without affecting the second anode metal layer 220 and the epitaxial layer 110 below.

[0073] In some embodiments, the preparation process of the anode layer comprises the following steps: Spin coating photoresist on the surface of the epitaxial layer 110, and performing selective area by photoetching and developing; Growing the anode layer 200 in the selected area.

[0074] Optionally, the growth method of the anode layer 200 includes but is not limited to electron beam evaporation method and magnetron sputtering method.

[0075] If the anode layer 200 comprises the first anode metal layer 210 and the second anode metal layer 220, the first anode metal layer 210 and the second anode metal layer 220 are prepared in sequence by the above-mentioned scheme during preparation.

[0076] In some embodiments, the implementation of the first anode metal layer 210 includes but is not limited to a Ni metal layer, and the implementation of the second anode metal layer 220 includes but is not limited to an Au metal layer, a W metal layer, a Pt metal layer, and a Pd metal layer.

[0077] In some embodiments, referring to Figure 2 Before preparing the anode layer 200 on the epitaxial layer side of the gallium oxide wafer 100, the following steps are further included: Preparing the cathode layer 600 on the substrate layer side of the gallium oxide wafer 100.

[0078] The cathode layer 600 functions to: Firstly, current needs to flow from the external circuit into the semiconductor device. If there is no good ohmic contact, a potential barrier will be formed at the metal-semiconductor interface, hindering the flow of carriers, resulting in power loss and reduced efficiency. The cathode layer 600 can align the energy bands of the metal and the semiconductor, eliminate or reduce the potential barrier height, thereby realizing a low-resistance ohmic contact, providing a "barrier-free" outlet and inlet for current.

[0079] Secondly, the cathode layer 600 is the basis for the electrical connection between the device and the external package or test platform. The cathode layer 600 is fixed to the tube shell by solder or conductive glue. The cathode layer 600 can enhance the structural integrity of the substrate layer 120, especially in the subsequent polishing or scribing process, and provide better mechanical support. The cathode layer 600 can also form an effective heat dissipation path to conduct the Joule heat generated by the device out of the tube shell and the heat sink to the environment, ensuring the reliability and service life of the device.

[0080] In some embodiments, the cathode layer 600 is a metal layer, and the implementation of the cathode layer 600 includes but is not limited to a Ti / Au alloy layer.

[0081] Optionally, the preparation process of the cathode layer 600 includes the following steps: Growth of a metal layer by electron beam evaporation; Annealing the metal layer at a temperature of 400-500°C under N2 atmosphere for 1-2 min, and finally forming the cathode layer 600.

[0082] The cathode layer 600 obtained after annealing can form a good ohmic contact with the substrate layer 120.

[0083] In some embodiments, before the outer side of the anode layer 200 is in contact with the polishing pad 300, it further includes: The side of the cathode layer 600 away from the gallium oxide wafer 100 is adhered to the stage; The gallium oxide wafer 100 is moved downward with the anode layer 200 facing the polishing pad 300 until the anode layer 200 is in close contact with the polishing pad 300.

[0084] The adhesion can achieve uniform pressure distribution. When the stage is moved downward, the pressure is uniformly transmitted to the entire wafer through the adhesive layer, forcing the anode layer 200 of the wafer to form close contact with the flexible polishing pad 300, and the depth of the polishing pad 300 squeezed into the anode layer 200 gap 400 is consistent, thereby ensuring that the removal rate of all grooves 500 is the same, and finally forming grooves 500 with uniform depth.

[0085] In some embodiments, the cathode layer 600 and the stage are adhered by an adhesive. The adhesive can be a thermoplastic adhesive (such as paraffin, synthetic thermoplastic polymer), which has the property of softening or melting with viscosity when heated, and solidifying to provide adhesion after cooling, and softening and losing viscosity again when heated.

[0086] The adhesive can also be a UV-curable adhesive (e.g., UV glue), which is liquid or film-like before curing and has a certain initial adhesion, so as to temporarily fix the wafer; the UV-curable adhesive is irradiated with UV light through the transparent objective table (usually glass or quartz), so that the adhesive is cross-linked and cured within a few seconds to tens of seconds, and a very high adhesive strength is obtained to withstand the polishing pressure and shear force; after polishing, the cured adhesive layer is degraded by irradiating with UV light of a specific wavelength (sometimes with the aid of heating), so that the adhesive strength is sharply reduced, thereby realizing the lossless separation of the wafer.

[0087] The adhesive can also be a pressure-sensitive adhesive, which can be adhered by applying pressure at room temperature. The pressure-sensitive adhesive usually exists in the form of a film, and is very easy to operate without the need for heating or light at room temperature.

[0088] In some embodiments, after the trench 500 is formed, the surface of the gallium oxide wafer 100 and the surface of the anode layer 200 are cleaned to obtain a gallium oxide device.

[0089] The cleaning step is as follows: The first cleaning liquid (H2O:H2O2:NH4OH) is used for preliminary rinsing, and the rinsing time is not less than 15 minutes, so as to remove organic matter and part of the metal; The residual first cleaning liquid is thoroughly rinsed with deionized water; The second cleaning liquid (H2O:H2O2:HCl) is used for rinsing, so as to remove heavy metal ions and stabilize the surface; The surface is overflow rinsed with deionized water, the residual second cleaning liquid is thoroughly rinsed under the premise of megasonic assistance, and it is ensured that the extremely small particles adsorbed on the surface are also removed; When the wafer is slowly pulled out of the deionized water, it enters an atmosphere filled with organic vapor, and under the action of the surface tension gradient, the water film spontaneously shrinks from the surface, thereby realizing non-contact and spotless drying.

[0090] The ratio of the first cleaning liquid can be 5H2O:1H2O2:1NH4OH, 6H2O:1H2O2:1NH4OH, 5H2O:1H2O2:0.5NH4OH, etc. The ratio of the second cleaning liquid can be 5H2O:1H2O2:1HCl, 6H2O:1H2O2:1HCl.

[0091] In some embodiments, referring to Figure 7After the gallium oxide device is obtained, the heterojunction material 900 is grown in the trench 500. The heterojunction material 900 is a p-type doped heterojunction material 900, which can better disperse the electric field and also inhibit edge breakdown. The band offset of the heterojunction can also be used to further improve the blocking capability of the carrier (electron), thereby reducing the reverse leakage current of the device. In addition, when working at high temperature, the potential barrier provided by the heterojunction is more stable, so that the reverse characteristics of the device at high temperature are more stable, the high-temperature leakage current is smaller, and the reliability is higher.

[0092] Optionally, the heterojunction material 900 can be nickel oxide (NiO), cuprous oxide (Cu2O), gallium nitride (GaN), etc. The growth position is controlled by photolithography mask, and the p-type doping concentration is controlled by changing the growth conditions.

[0093] In some embodiments, referring to Figure 8 After the heterojunction material 900 is grown in the trench 500, it further includes: A metal electrode layer 800 is prepared on the surface layer of the heterojunction material 900 and the surface layer of the epitaxial layer 110, so as to form an ohmic contact between the heterojunction material 900 and the epitaxial layer 110, and realize a low-resistance current path.

[0094] In addition, the trench 500 and the heterojunction therein divide the epitaxial layer 110 below the anode into a plurality of parallel "island regions". The metal electrode layer 800 on the top connects these "island regions" and the heterojunction in the trench 500 in parallel on the top, forming a unified anode. After ensuring that the current enters from the external lead, it can be uniformly distributed to all active areas of the entire device.

[0095] Optionally, the preparation method of the metal electrode layer 800 includes but is not limited to electron beam, magnetron sputtering, etc.

[0096] The application proposes a junction barrier Schottky diode preparation method based on chemical mechanical polishing. The chemical mechanical polishing (CMP) is used to replace the ICP etching trench 500, and the anode metal is used as a mask. Since the Mohs hardness of the gallium oxide epitaxial layer 110 is low, the polishing pad 300 with high softness and elasticity and the nano-silica sol polishing liquid 700 can be used for chemical mechanical polishing, and the trench 500 can be gradually formed on the surface of the epitaxial layer 110 at a certain removal rate. The material of the anode layer 200 has good conductivity and high hardness, and is difficult to remove by chemical mechanical polishing, and the removal rate is much lower than that of the epitaxial layer 110. Moreover, the damage caused by the chemical mechanical polishing for preparing the trench 500 is small, and the removal depth is controllable, which can greatly reduce the preparation cost of the gallium oxide device and improve the economic benefit.

[0097] The above only describes preferred embodiments of the present application and is not used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method for fabricating a junction barrier Schottky diode based on chemical mechanical polishing, characterized in that, Includes the following steps: The gallium oxide wafer (100) has several chip functional regions on the epitaxial layer side, and an anode layer (200) is prepared on the epitaxial layer side of each of the chip functional regions. The hardness of the outer side of the anode layer (200) is higher than the hardness of the epitaxial layer (110) of the gallium oxide wafer (100). The surface of the anode layer (200) is brought into close contact with the flexible polishing pad (300), the polishing pad (300) is squeezed into the gap (400) of the anode layer (200) in the same functional area of ​​the chip, and contacts the surface of the epitaxial layer (110); As the polishing pad (300) rotates, the polishing pad (300) squeezed into the gap (400) of the anode layer (200) polishes the epitaxial layer (110) with polishing liquid (700) to form a trench (500) corresponding to the gap (400), thereby forming a gallium oxide device in the functional area of ​​the chip.

2. The method for fabricating a junction barrier Schottky diode based on chemical mechanical polishing as described in claim 1, characterized in that, The pressure between the polishing pad (300) and the anode layer (200) is The removal rate of the epitaxial layer (110) is The With the It is directly proportional.

3. The method for fabricating a junction barrier Schottky diode based on chemical mechanical polishing as described in claim 1, characterized in that, The rotational speed of the polishing pad (300) is The removal rate of the epitaxial layer (110) is The With the It is directly proportional.

4. The method for fabricating a junction barrier Schottky diode based on chemical mechanical polishing as described in claim 1, characterized in that, The polishing pad (300) is one of the following: damping cloth polishing pad (300), non-woven fabric polishing pad (300), and fabric polishing pad (300).

5. The method for fabricating a junction barrier Schottky diode based on chemical mechanical polishing as described in claim 1, characterized in that, The depth of the trench (500) is 100nm~3μm.

6. The method for fabricating a junction barrier Schottky diode based on chemical mechanical polishing as described in claim 1, characterized in that, The anode layer (200) includes a first anode metal layer (210) and a second anode metal layer (220), wherein the first anode metal layer (210) is located between the second anode metal layer (220) and the epitaxial layer (110); The hardness of the second anode metal layer (220) is higher than that of the epitaxial layer (110), and the first anode metal layer (210) forms a Schottky contact with the epitaxial layer (110).

7. The method for fabricating a junction barrier Schottky diode based on chemical mechanical polishing as described in claim 1, characterized in that, Before fabricating the anode layer (200) on the epitaxial layer side of the gallium oxide wafer (100), the following steps are also included: A cathode layer (600) is prepared on the substrate side of the gallium oxide wafer (100).

8. The method for fabricating a junction barrier Schottky diode based on chemical mechanical polishing as described in claim 7, characterized in that, Before bringing the outer surface of the anode layer (200) into contact with the polishing pad (300), the process further includes: The side of the cathode layer (600) facing away from the gallium oxide wafer (100) is attached to the stage; With the anode layer (200) facing the polishing pad (300), the gallium oxide wafer (100) is moved downward until the anode layer (200) and the polishing pad (300) are in close contact.

9. The method for fabricating a junction barrier Schottky diode based on chemical mechanical polishing as described in claim 1, characterized in that, After obtaining the gallium oxide device, a heterojunction material (900) is grown in the trench (500).

10. The method for fabricating a junction barrier Schottky diode based on chemical mechanical polishing as described in claim 9, characterized in that, After growing the heterojunction material (900) within the trench (500), the process further includes: A metal electrode layer (800) is prepared on the surface of the heterojunction material (900) and the surface of the epitaxial layer (110) to form an ohmic contact between the heterojunction material (900) and the epitaxial layer (110).

Images