Planar SiC MOS (Metal Oxide Semiconductor) gate-controlled thyristor device based on epitaxial surface and manufacturing method of planar SiC MOS gate-controlled thyristor device

Abstract

The invention discloses a planar SiC MOS (Metal Oxide Semiconductor) gate-controlled thyristor device based on an epitaxial surface and a manufacturing method thereof, effectively avoids the problem of using a triple ion implantation process traditionally by ingeniously introducing an n-type epitaxial layer, and utilizes the advantages of high growth speed, low material defect, good process stability and the like of an epitaxial growth technology to improve the performance of the device. The semiconductor layer with lower surface defect density can be obtained, the mobility of channel carriers is effectively improved, and the working performance of the device is improved. By introducing the n-type epitaxial region, the separation design of the p-type ion implantation well region and the n-type ion implantation well region is realized, the doping concentration can be controlled more accurately by the surface structure of the epitaxial layer, and the deeper junction depth of the p-type ion implantation well region and the deeper base region width of the n-type ion implantation well region can be controlled and realized. The design difficulty that the ion implantation junction depth of the device needs to exceed 1 [mu] m is reduced, and the problem that the original lattice structure of the material is damaged by SiC high-temperature ion implantation is avoided.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface and its manufacturing method. Background Technology

[0002] SiC materials possess excellent properties such as wide bandgap, high critical breakdown electric field, high electron saturation velocity, and high thermal conductivity, making SiC power devices ideal for high-temperature, high-voltage, and high-power applications. Among them, SiC thyristors, as high-voltage, high-power devices, have very high voltage blocking capability, excellent current handling capability, and high on-state di / dt capability, and are therefore widely used in power electronic equipment such as high-power inverters, high-voltage pulse switches, and uninterruptible power supplies.

[0003] Traditional planar SiC MOS gate-controlled thyristors, such as Figure 1 As shown, a triple ion implantation process is required to achieve device structures with different doping types and concentrations, including P-type ion implantation well region, N-type ion implantation well region, P+ source region, N+ source region, and terminal region. For SiC material, considering the incomplete ionization of impurities and the significant difference in ionization rates between N and Al dopants, controlling the doping concentration of triple ion implantation in the device presents certain difficulties. High-temperature ion implantation of SiC will destroy the original crystal structure of the material, requiring annealing temperatures above 1600℃ for repair, which will affect the mobility of the surface inversion layer. Generally, the ion implantation junction depth does not exceed 1μm. To achieve an ion implantation junction depth of more than 1μm, extremely high energy is required, posing a challenge to the process and equipment. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface and its manufacturing method. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, embodiments of the present invention provide a method for manufacturing a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface, the method comprising: An n-type SiC substrate was obtained, and a p-type epitaxial field cutoff layer and a p-type epitaxial drift region were sequentially grown on the upper surface of the n-type SiC substrate. Ion implantation is performed in the middle region of the p-type epitaxial drift region to form an n-type ion implantation trap region. A first n-type epitaxial region is epitaxially grown on the p-type epitaxial drift region and the n-type ion implantation trap region; Ion implantation is performed on the first n-type epitaxial regions at both ends of the device to form p-type ion implantation JFET regions. Ion implantation is performed on the first n-type epitaxial region in the middle region of the device to form p-type ion implantation trap regions. Ion implantation is performed on the first n-type epitaxial region between the p-type ion implantation JFET region and the p-type ion implantation trap regions to form a second n-type epitaxial region and an n-type ion implantation channel region stacked from top to bottom. The n-type ion implantation channel region is in contact with the n-type ion implantation trap region. Ion implantation is performed on the middle region of the p-type ion implantation trap region to form a P+ source region, and ion implantation is performed on the two ends of the p-type ion implantation trap region to form an N+ source region. A gate dielectric layer is grown on the p-type ion implanted JFET region, the second n-type epitaxial region, the p-type ion implanted trap region, the P+ source region, and the N+ source region. A gate electrode is grown on the gate dielectric layer excluding the anode region; An insulating oxide layer is grown on the gate electrode and the remaining gate dielectric layer; The insulating oxide layer in the anode region is etched down to the upper surface of the P+ source region and the N+ source region, and the anode is grown on the P+ source region and the N+ source region. A cathode is grown on the lower surface of an n-type SiC substrate.

[0005] In one embodiment of the present invention, ion implantation is performed in the middle region of the p-type epitaxial drift region to form an n-type ion implantation trap region, including: Ion implantation is performed in the middle region of the p-type epitaxial drift region to form a junction with a depth of 0.5 μm to 1 μm and a doping concentration of 8e. 16 cm -3 ~5e 17 cm -3 n-type ion implantation trap region.

[0006] In one embodiment of the present invention, a first n-type epitaxial region is epitaxially grown on a p-type epitaxial drift region and an n-type ion implantation trap region, including: Epitaxial growth with a thickness of 0.5 μm to 1 μm and a doping concentration range of 1e was performed on the p-type epitaxial drift region and the n-type ion implantation trap region. 15 cm -3 ~1e 16 cm -3 The first n-type extensional region.

[0007] In one embodiment of the present invention, the junction depth of the p-type ion implanted JFET region is greater than or equal to the thickness of the first n-type epitaxial region.

[0008] In one embodiment of the present invention, ion implantation is performed on the first n-type epitaxial regions at both ends of the device to form p-type ion-implanted JFET regions, including: Ion implantation is performed on the first n-type epitaxial regions at both ends of the device to form junctions with a depth of 0.5 μm to 1 μm and a doping concentration range of 1e. 16 cm -3 ~5e 17 cm -3 p-type ion implantation into the JFET region.

[0009] In one embodiment of the present invention, the junction depth of the p-type ion implantation trap region is less than or equal to the thickness of the first n-type epitaxial region.

[0010] In one embodiment of the present invention, ion implantation is performed on the first n-type epitaxial region in the middle region of the device to form a p-type ion implantation trap region, including: Ion implantation is performed on the first n-type epitaxial region in the middle region of the device to form a junction with a depth of 0.3 μm to 1 μm and a doping concentration range of 1e. 17 cm -3 ~5e 18 cm -3 p-type ion implantation trap region.

[0011] In one embodiment of the present invention, ion implantation is performed on a first n-type epitaxial region between a p-type ion implantation JFET region and a p-type ion implantation trap region to form a second n-type epitaxial region and an n-type ion implantation channel region stacked from top to bottom, including: Ion implantation is performed on the first n-type epitaxial region between the p-type ion implantation JFET region and the p-type ion implantation trap region to form a stacked junction with a depth of 0 μm to 0.5 μm and a doping concentration of 1e from top to bottom. 15 cm -3 ~1e 16 cm -3 The second n-type epitaxial region has a junction depth of 0.5 μm to 1 μm and a doping concentration range of 4e. 16 cm -3 ~1e 17 cm -3 n-type ion implantation channel region.

[0012] Secondly, embodiments of the present invention provide a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface, wherein the planar SiC MOS gate-controlled thyristor device is manufactured according to any of the manufacturing methods for a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface as described in the first aspect; the corresponding planar SiC MOS gate-controlled thyristor device includes: n-type SiC substrate, and p-type epitaxial field cutoff layer and p-type epitaxial drift region sequentially located on the upper surface of n-type SiC substrate; The n-type ion implantation trap region is located within the p-type epitaxial drift region in the middle region; The first n-type epitaxial region is located on the n-type ion implantation trap region; The p-type ion implantation trap region is located within the first n-type epitaxial region in the middle region; The second n-type epitaxial region and the n-type ion implantation channel region are stacked from top to bottom and are located within the first n-type epitaxial region at both ends; wherein, the upper surface of the second n-type epitaxial region is flush with the upper surface of the first n-type epitaxial region; the n-type ion implantation channel region is in contact with the n-type ion implantation trap region; p-type ion implantation into the JFET region, located on the p-type epitaxial drift region at both ends; The P+ source region is located within the p-type ion implantation trap region in the middle region; The N+ source region is located within the p-type ion implantation trap region at both ends; The gate dielectric layer is located on the p-type ion implantation JFET region, the second n-type epitaxial region, the p-type ion implantation trap region, and part of the N+ source region at both ends of the device; The gate electrode is located on the gate dielectric layer; An insulating oxide layer is located on the gate electrode and on the gate dielectric layer on one side of the gate electrode. The anode is located in the P+ source region and the remaining part of the N+ source region; The cathode is located on the lower surface of the n-type SiC substrate.

[0013] The beneficial effects of this invention are: This invention proposes a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface. By cleverly introducing an n-type epitaxial layer, it effectively avoids the problems associated with traditional triple ion implantation processes. Leveraging the advantages of epitaxial growth technology, such as fast growth rate, low material defects, and good process stability, it achieves a semiconductor layer with lower surface defect density, effectively improving channel carrier mobility and enhancing device performance. The introduction of the n-type epitaxial region enables the separation of the p-type and n-type ion implantation well regions. The epitaxial layer surface structure allows for more precise control of doping concentration and enables control over achieving deeper junction depths in the p-type and n-type ion implantation well regions, reducing the design difficulty of requiring ion implantation junction depths exceeding 1 μm and avoiding the problem of SiC high-temperature ion implantation damaging the original crystal structure. In summary, the manufacturing method proposed in this invention is compatible with mature CMOS technology, has low device manufacturing difficulty, high production efficiency, and produces planar SiC MOS gate-controlled thyristors with better working performance, making them more suitable for use in power electronic equipment such as high-power inverters, high-voltage pulse switches, and uninterruptible power supplies.

[0014] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of a traditional planar SiC MOS gate-controlled thyristor device; Figure 2 This is a schematic flowchart of a method for manufacturing a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface, according to an embodiment of the present invention. Figures 3(a) to 3(j) This is a schematic diagram of the corresponding structure during the manufacturing process of the planar SiC MOS gate-controlled thyristor device based on the epitaxial surface provided in the embodiments of the present invention; Figure 4 This is a schematic diagram of a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface, provided by an embodiment of the present invention.

[0016] Explanation of reference numerals in the attached figures: 1- n-type SiC substrate; 2- p-type epitaxial field cutoff layer; 3- p-type epitaxial drift region; 4- n-type ion implantation trap region; 5- first n-type epitaxial region; 6- p-type ion implantation trap region; 7- p-type ion implantation JFET region; 8- n-type ion implantation channel region; 9- N+ source region; 10- P+ source region; 11- gate dielectric layer; 12- gate electrode; 13- insulating oxide layer; 14- anode; 15- cathode. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0018] Firstly, please see Figure 2 This invention provides a method for manufacturing a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface, the method comprising: S10. Obtain an n-type SiC substrate 1, and sequentially grow a p-type epitaxial field cutoff layer 2 and a p-type epitaxial drift region 3 on the upper surface of the n-type SiC substrate 1.

[0019] In this embodiment of the invention, an n-type SiC substrate 1 is obtained, such as a 4H-SiC substrate material, with a doping concentration range of 5e. 18 cm -3 ~1e 19 cm -3 On the upper surface of n-type SiC substrate 1, CVD (Chemical Vapor Deposition) was used to grow sequentially from bottom to top a thickness of 0.5 μm to 6 μm with a doping concentration of 1e. 16 cm -3 ~5e 17 cm -3 p-type epitaxial field-stop layer 2, with a thickness of 40μm~150μm and a doping concentration of 1e 14 cm-3 ~1e 15 cm -3 The p-type epitaxial drift region 3 is shown in Figure 3(a).

[0020] S20. Ion implantation is performed in the middle region of the p-type epitaxial drift region 3 to form an n-type ion implantation trap region 4.

[0021] In this embodiment of the invention, a mask is used to form an ion implantation region in the middle region of the p-type epitaxial drift region 3 for N-ion implantation, forming a junction depth of 0.5 μm to 1 μm and a doping concentration range of 8e. 16 cm -3 ~5e 17 cm -3 The n-type ion implantation trap region 4 was then removed, as shown in Figure 3(b).

[0022] S30. A first n-type epitaxial region 5 is epitaxially grown on the p-type epitaxial drift region 3 and the n-type ion implantation trap region 4.

[0023] This invention utilizes CVD technology to epitaxially grow a first n-type epitaxial region 5 on a p-type epitaxial drift region 3 and an n-type ion implantation trap region 4, including: epitaxially growing a region with a thickness of 0.5 μm to 1 μm and a doping concentration range of 1e on the p-type epitaxial drift region 3 and the n-type ion implantation trap region 4. 15 cm -3 ~1e 16 cm -3 The first n-type extensional region 5 is shown in Figure 3(c).

[0024] S40. Ion implantation is performed on the first n-type epitaxial region 5 at both ends of the device to form a p-type ion implantation JFET region 7. Ion implantation is performed on the first n-type epitaxial region 5 in the middle region of the device to form a p-type ion implantation trap region. Ion implantation is performed on the first n-type epitaxial region 5 between the p-type ion implantation JFET region 7 and the p-type ion implantation trap region 6 to form a second n-type epitaxial region and an n-type ion implantation channel region 8 stacked from top to bottom. The n-type ion implantation channel region 8 is in contact with the n-type ion implantation trap region 4.

[0025] This embodiment of the invention utilizes a mask to perform ion implantation on the first n-type epitaxial regions 5 at both ends of the device to form p-type ion-implanted JFET regions 7, including: performing ion implantation on the first n-type epitaxial regions 5 at both ends of the device to form a junction depth of 0.5 μm to 1 μm and a doping concentration range of 1e. 16 cm -3 ~5e 17 cm -3The p-type ion implanted JFET region 7 is described above. In this embodiment of the invention, the junction depth of the p-type ion implanted JFET region 7 is greater than or equal to the thickness of the first n-type epitaxial region 5. For example, when the thickness of the first n-type epitaxial region 5 is 0.5 μm, the junction depth of the p-type ion implanted JFET region 7 can be 0.6 μm; when the thickness of the first n-type epitaxial region 5 is 1 μm, the junction depth of the p-type ion implanted JFET region 7 can be 1 μm, depending on the maximum junction depth that can be implanted by the ion implantation process.

[0026] This embodiment of the invention utilizes a mask to perform ion implantation on the first n-type epitaxial region 5 in the middle region of the device to form a p-type ion implantation trap region 6, including: performing ion implantation on the first n-type epitaxial region 5 in the middle region of the device to form a junction depth of 0.3 μm to 1 μm and a doping concentration range of 1e. 17 cm -3 ~5e 18 cm -3 The p-type ion implantation well region 6 is formed by implanting ions into the first n-type epitaxial region 5. In this embodiment, the junction depth of the p-type ion implantation well region 6 is less than or equal to the thickness of the first n-type epitaxial region 5. For example, when the thickness of the first n-type epitaxial region 5 is 1 μm, the junction depth of the p-type ion implantation well region 6 is 0.5 μm, or the junction depth of the p-type ion implantation well region 6 is 1 μm. Therefore, this invention forms the p-type ion implantation well region 6 by implanting ions into the first n-type epitaxial region 5. This p-type ion implantation well region 6 is separated from the n-type ion implantation well region 4 on the surface of the p-type epitaxial drift region 3, avoiding the design of triple ion implantation and reducing lattice damage caused by multiple ion implantations. Compared to the traditional method of forming the p-type ion implantation well region 6 by ion implantation within the n-type ion implantation well region 4, the p-type ion implantation well region 6 can be formed deeper, resulting in better device conductivity.

[0027] This invention utilizes a mask to perform ion implantation on a first n-type epitaxial region 5 between a p-type ion implantation JFET region 7 and a p-type ion implantation trap region 6 to form a second n-type epitaxial region and an n-type ion implantation channel region 8 stacked from top to bottom. This includes: performing ion implantation on the first n-type epitaxial region 5 between the p-type ion implantation JFET region 7 and the p-type ion implantation trap region 6 to form a stacked junction depth of 0 μm to 0.5 μm and a doping concentration of 1e from top to bottom. 15 cm -3 ~1e 16 cm -3 The second n-type epitaxial region has a junction depth of 0.5 μm to 1 μm and a doping concentration range of 4e. 16 cm -3 ~1e 17 cm -3The n-type ion implantation channel region 8 is designed to prevent lateral punch-through problems caused by excessively low doping concentration in the first n-type epitaxial region 5. For example, if the thickness of the first n-type epitaxial region 5 is 1 μm, and the junction depth of the n-type ion implantation channel region 8 is 1 μm, then the junction depth of the second n-type epitaxial region is 0 μm; if the junction depth of the n-type ion implantation channel region 8 is 0.5 μm, then the junction depth of the second n-type epitaxial region is 0.5 μm.

[0028] After the above ion implantation, the device structure is formed as shown in Figure 3(d).

[0029] It should be noted that, starting from Figure 3(d), in order to reflect the characteristics of the epitaxial layer, the second n-type epitaxial region in the stack is marked as 5. After ion implantation, the second n-type epitaxial region and the first n-type epitaxial region maintain the same doping concentration. The difference is that part of the first n-type epitaxial region forms an n-type ion implantation channel region, and the remaining part serves as the second n-type epitaxial region.

[0030] S50. Ion implantation is performed on the middle region of the p-type ion implantation trap region 6 to form a P+ source region 10, and ion implantation is performed on the two ends of the p-type ion implantation trap region 6 to form an N+ source region 9.

[0031] In this embodiment of the invention, a mask is used to implant ions into the middle region of the p-type ion implantation trap region 6 to form a P+ source region 10, and ions are implanted into the two ends of the p-type ion implantation trap region 6 to form an N+ source region 9. The junction depths of the N+ source region 9 and the P+ source region 10 are both smaller than the junction depth of the p-type ion implantation trap region 6, as shown in Figure 3(e).

[0032] S60. A gate dielectric layer 11 is grown on the p-type ion implanted JFET region 7, the second n-type epitaxial region, the p-type ion implanted trap region 6, the P+ source region 10, and the N+ source region 9.

[0033] In this embodiment of the invention, a gate dielectric layer 11 with a thickness of 45nm~55nm is grown on the device surface using a thermal oxidation process or a PECVD (Plasma-Enhanced Chemical Vapor Deposition) process. The gate dielectric layer 11 can be made of SiO2 and fully covers the surface of the p-type ion implantation JFET region 7, the second n-type epitaxial region, the p-type ion implantation trap region 6, the P+ source region 10, and the N+ source region 9, as shown in Figure 3(f).

[0034] S70. A gate electrode 12 is grown on the gate dielectric layer 11, excluding the anode region.

[0035] In this embodiment of the invention, an electron beam evaporation process is used to deposit a conductive polysilicon layer with a thickness of 400nm~800nm ​​on the gate dielectric layer 11. The layer is then patterned using photolithography and etching processes. The conductive polysilicon layer in the anode region is etched away, while the conductive polysilicon layer in the region other than the anode region is retained. Specifically, the conductive polysilicon layers on the p-type ion implantation JFET region 7, the second n-type epitaxial region, the p-type ion implantation trap region 6, and part of the N+ source region 9 are retained to form the gate electrode 12 as shown in Figure 3(g).

[0036] S80. An insulating oxide layer 13 is grown on the gate electrode 12 and the remaining gate dielectric layer 11.

[0037] In this embodiment of the invention, an insulating oxide layer 13 is grown on the gate electrode 12 and the remaining gate dielectric layer 11 using the PECVD process. The material of the insulating oxide layer 13 can be SiO2, as shown in Figure 3(h).

[0038] S90, etch the insulating oxide layer 13 in the anode region until the upper surface of the P+ source region 10 and N+ source region 9, and grow the anode 14 on the P+ source region 10 and N+ source region 9.

[0039] In this embodiment of the invention, the insulating oxide layer 13 of the anode region is etched using ICP (Inductively Coupled Plasma) technology until the upper surfaces of the P+ source region 10 and the N+ source region 9 are exposed. Then, an electron beam evaporation process is used to evaporate the anode metal 14, such as an Al / Ti / Ni multilayer metal material, into the P+ source region 10 and the N+ source region 9, forming the anode 14 as shown in Figure 3(g), to form an ohmic contact with the N+ source region 9 and the P+ source region 10.

[0040] S100, A cathode 15 is grown on the lower surface of an n-type SiC substrate 1.

[0041] In this embodiment of the invention, the lower surface of the n-type SiC substrate 1 is thinned and polished, and a cathode 15 metal, such as Ni metal material, is grown on the lower surface of the n-type SiC substrate 1 using an electron beam evaporation process to form the cathode 15 as shown in Figure 3(i), so as to form an ohmic contact with the lower surface of the n-type SiC substrate 1.

[0042] As can be seen from the manufacturing process S10~S80 above, compared with the traditional manufacturing process, the advantages of the manufacturing method proposed in this invention are mainly reflected in: by introducing the first n-type epitaxial region 5, the separate design of the p-type ion implantation trap region 6 and the n-type ion implantation trap region 4 is realized. Separate design allows for easy control of doping concentration in specific regions. Traditional designs need to consider the difference in ionization rates between p-type and n-type dopants in SiC. In the separate design proposed in this invention, the n-type ion implantation well region 4 mainly serves as the short base region of the thyristor and achieves forward breakdown voltage; the threshold voltage design for the PMOS used for device turn-on is mainly achieved by controlling the doping concentration of the epitaxial layer; and the threshold voltage design for the NMOS used for device turn-off is mainly achieved by controlling the surface doping concentration of the p-type ion implantation well region 6.

[0043] Separate design can avoid multiple ion implantations in the same area, reducing lattice damage to the device caused by multiple ion implantations.

[0044] The separate design allows for deeper junctions without requiring higher ion implantation energies. In conventional designs, the p-type ion implantation well region 6 and the n-type ion implantation well region 4 overlap in a certain area, resulting in an effective junction depth for the n-type ion implantation well region 4 equal to the difference between the two. The separate design proposed in this invention allows for the separate design of the n-type ion implantation well region 4 to achieve a deeper base region width, and the separate design of the p-type ion implantation well region 6 to achieve a deeper anode region width.

[0045] In summary, the method for manufacturing a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface proposed in this invention cleverly introduces an n-type epitaxial layer, effectively avoiding the problems associated with traditional triple ion implantation processes. Utilizing the advantages of epitaxial growth technology, such as fast growth rate, low material defects, and good process stability, a semiconductor layer with lower surface defect density can be obtained, effectively improving the channel carrier mobility and enhancing device performance. By introducing the n-type epitaxial region, the p-type and n-type ion implantation well regions are separated. The surface structure of the epitaxial layer allows for more precise control of the doping concentration and enables control over achieving a deeper junction depth in the p-type ion implantation well region and a deeper base width in the n-type ion implantation well region. This reduces the design difficulty of requiring an ion implantation junction depth exceeding 1 μm and avoids the problem of SiC high-temperature ion implantation damaging the original crystal structure of the material. In summary, the manufacturing method proposed in this invention is compatible with mature CMOS technology, has low device manufacturing difficulty, high production efficiency, and produces planar SiC MOS gate-controlled thyristors with better working performance, making them more suitable for use in power electronic equipment such as high-power inverters, high-voltage pulse switches, and uninterruptible power supplies.

[0046] Secondly, please see Figure 4This invention provides a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface, wherein the planar SiC MOS gate-controlled thyristor device is manufactured according to any of the manufacturing methods for planar SiC MOS gate-controlled thyristors based on an epitaxial surface as described in the first aspect; the corresponding planar SiC MOS gate-controlled thyristor includes: n-type SiC substrate 1, and p-type epitaxial field cutoff layer 2 and p-type epitaxial drift region 3 sequentially located on the upper surface of n-type SiC substrate 1; n-type ion implantation trap region 4 is located within the p-type epitaxial drift region 3 in the middle region; The first n-type epitaxial region 5 is located on the n-type ion implantation trap region 4; p-type ion implantation trap region 6 is located within the first n-type epitaxial region 5 in the middle region; The second n-type epitaxial region and the n-type ion implantation channel region 8 are stacked from top to bottom and are located within the first n-type epitaxial region 5 at both ends; wherein, the upper surface of the second n-type epitaxial region is flush with the upper surface of the first n-type epitaxial region 5; the n-type ion implantation channel region 8 is in contact with the n-type ion implantation trap region 4; p-type ion implantation JFET region 7 is located on p-type epitaxial drift region 3 at both ends; P+ source region 10 is located within p-type ion implantation trap region 6 in the middle region; N+ source region 9 is located within p-type ion implantation trap region 6 at both ends; The gate dielectric layer 11 is located on the p-type ion implantation JFET region 7, the second n-type epitaxial region, the p-type ion implantation trap region 6, and part of the N+ source region 9 at both ends of the device; Gate electrode 12 is located on gate dielectric layer 11; An insulating oxide layer 13 is located on the gate electrode 12 and on the gate dielectric layer 11 on one side of the gate electrode 12; Anode 14 is located on P+ source region 10 and the remaining portion of N+ source region 9; The cathode 15 is located on the lower surface of the n-type SiC substrate 1.

[0047] As for the structural embodiment of the second aspect, since it is basically similar to the manufacturing method embodiment of the first aspect, the description is relatively simple, and relevant details can be found in the description of the manufacturing method embodiment of the first aspect.

[0048] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0049] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0050] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface, characterized in that, The manufacturing method includes: An n-type SiC substrate was obtained, and a p-type epitaxial field cutoff layer and a p-type epitaxial drift region were sequentially grown on the upper surface of the n-type SiC substrate. Ion implantation is performed in the middle region of the p-type epitaxial drift region to form an n-type ion implantation trap region. A first n-type epitaxial region is epitaxially grown on the p-type epitaxial drift region and the n-type ion implantation trap region; Ion implantation is performed on the first n-type epitaxial regions at both ends of the device to form p-type ion implantation JFET regions. Ion implantation is performed on the first n-type epitaxial region in the middle region of the device to form p-type ion implantation trap regions. Ion implantation is performed on the first n-type epitaxial region between the p-type ion implantation JFET region and the p-type ion implantation trap regions to form a second n-type epitaxial region and an n-type ion implantation channel region stacked from top to bottom. The n-type ion implantation channel region is in contact with the n-type ion implantation trap region. Ion implantation is performed on the middle region of the p-type ion implantation trap region to form a P+ source region, and ion implantation is performed on the two ends of the p-type ion implantation trap region to form an N+ source region. A gate dielectric layer is grown on the p-type ion implanted JFET region, the second n-type epitaxial region, the p-type ion implanted trap region, the P+ source region, and the N+ source region. A gate electrode is grown on the gate dielectric layer excluding the anode region; An insulating oxide layer is grown on the gate electrode and the remaining gate dielectric layer; The insulating oxide layer in the anode region is etched down to the upper surface of the P+ source region and the N+ source region, and the anode is grown on the P+ source region and the N+ source region. A cathode is grown on the lower surface of an n-type SiC substrate.

2. The method for manufacturing a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface according to claim 1, characterized in that, Ion implantation is performed in the middle region of the p-type epitaxial drift region to form an n-type ion implantation trap region, including: Ion implantation is performed in the middle region of the p-type epitaxial drift region to form a junction with a depth of 0.5 μm to 1 μm and a doping concentration of 8e. 16 cm -3 ~5e 17 cm -3 n-type ion implantation trap region.

3. The method for manufacturing a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface according to claim 1, characterized in that, A first n-type epitaxial region is epitaxially grown on the p-type epitaxial drift region and the n-type ion implantation trap region, including: Epitaxial growth with a thickness of 0.5 μm to 1 μm and a doping concentration range of 1e was performed on the p-type epitaxial drift region and the n-type ion implantation trap region. 15 cm -3 ~1e 16 cm -3 The first n-type extensional region.

4. The method for manufacturing a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface according to claim 1, characterized in that, The junction depth of the p-type ion implanted JFET region is greater than or equal to the thickness of the first n-type epitaxial region.

5. The method for manufacturing a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface according to claim 1, characterized in that, Ion implantation is performed on the first n-type epitaxial regions at both ends of the device to form p-type ion-implanted JFET regions, including: Ion implantation is performed on the first n-type epitaxial regions at both ends of the device to form junctions with a depth of 0.5 μm to 1 μm and a doping concentration range of 1e. 16 cm -3 ~5e 17 cm -3 p-type ion implantation into the JFET region.

6. The method for manufacturing a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface according to claim 1, characterized in that, The junction depth of the p-type ion implantation trap region is less than or equal to the thickness of the first n-type epitaxial region.

7. The method for manufacturing a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface according to claim 1, characterized in that, Ion implantation is performed on the first n-type epitaxial region in the middle region of the device to form a p-type ion implantation trap region, including: Ion implantation is performed on the first n-type epitaxial region in the middle region of the device to form a junction with a depth of 0.3 μm to 1 μm and a doping concentration range of 1e. 17 cm -3 ~5e 18 cm -3 p-type ion implantation trap region.

8. The method for manufacturing a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface according to claim 1, characterized in that, Ion implantation is performed on the first n-type epitaxial region between the p-type ion implantation JFET region and the p-type ion implantation trap region to form a second n-type epitaxial region and an n-type ion implantation channel region stacked from top to bottom, including: Ion implantation is performed on the first n-type epitaxial region between the p-type ion implantation JFET region and the p-type ion implantation trap region to form a stacked junction with a depth of 0 μm to 0.5 μm and a doping concentration of 1e from top to bottom. 15 cm -3 ~1e 16 cm -3 The second n-type epitaxial region has a junction depth of 0.5 μm to 1 μm and a doping concentration range of 4e. 16 cm -3 ~1e 17 cm -3 The n-type ion implantation channel region.

9. A planar SiC MOS gate-controlled thyristor device based on an epitaxial surface, characterized in that, The planar SiCMOS gate-controlled thyristor device is manufactured by the method for manufacturing a planar SiC MOS gate-controlled thyristor device based on an epitaxial surface according to any one of claims 1 to 8; the corresponding planar SiC MOS gate-controlled thyristor includes: n-type SiC substrate, and p-type epitaxial field cutoff layer and p-type epitaxial drift region sequentially located on the upper surface of n-type SiC substrate; The n-type ion implantation trap region is located within the p-type epitaxial drift region in the middle region; The first n-type epitaxial region is located on the n-type ion implantation trap region; The p-type ion implantation trap region is located within the first n-type epitaxial region in the middle region; The second n-type epitaxial region and the n-type ion implantation channel region are stacked from top to bottom and are located within the first n-type epitaxial region at both ends; wherein, the upper surface of the second n-type epitaxial region is flush with the upper surface of the first n-type epitaxial region; the n-type ion implantation channel region is in contact with the n-type ion implantation trap region; p-type ion implantation into the JFET region, located on the p-type epitaxial drift region at both ends; The P+ source region is located within the p-type ion implantation trap region in the middle region; The N+ source region is located within the p-type ion implantation trap region at both ends; The gate dielectric layer is located on the p-type ion implantation JFET region, the second n-type epitaxial region, the p-type ion implantation trap region, and part of the N+ source region at both ends of the device; The gate electrode is located on the gate dielectric layer; An insulating oxide layer is located on the gate electrode and on the gate dielectric layer on one side of the gate electrode. The anode is located in the P+ source region and the remaining part of the N+ source region; The cathode is located on the lower surface of the n-type SiC substrate.

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