Transistor with programmable horizontal double floating gate homojunction and preparation method thereof

Abstract

The invention provides a transistor with a programmable horizontal double-floating-gate homojunction. The transistor comprises two floating gate layers which are independent from each other and are composed of multiple layers of graphene; the tunneling layer is positioned above the floating gate layer; the channel layer is positioned above the tunneling layer; the source electrode and the drain electrode are located above the two ends of the channel layer respectively, so that the floating gate layer can achieve regulation and control of source-drain contact, and then it is guaranteed that a floating gate electric field can achieve regulation and control of Schottky barriers of the source electrode and the drain electrode; and the two direct tunneling electrodes are respectively positioned above two ends of the tunneling layer and are not in contact with the channel layer, so as to inject charges into the floating gate layer. The invention also provides a preparation method of the transistor. According to the transistor provided by the invention, a bilateral floating gate is used for regulating and controlling an energy band in contact with two sides, and any one of four junctions (a p-n junction, an n-p junction, a p-p junction and an n-n junction) can be freely formed and switched.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic device technology. Specifically, this invention relates to a transistor having a programmable horizontal double floating gate homojunction and its fabrication method. Background Technology

[0002] Two-dimensional (2D) semiconductor materials have garnered significant attention from academia and industry due to their superior electrical properties. As a strong contender for future silicon-based semiconductors, 2D semiconductors, with their atomically flat interfaces and dangling-bond-free surfaces, hold the promise of overcoming the bottlenecks of existing semiconductor transistors and further extending Moore's Law. One important aspect is that 2D materials can be used as ultrathin channels in FETs to resist short-channel effects and provide opportunities for novel device concepts. Developing 2D semiconductor doping methods is a crucial issue in electronic and microelectronic applications. However, the situation becomes unique when 2D materials are involved. Due to the weaker shielding ability of electric fields in 2D materials, defects generated by high-energy particles during ion implantation form deep-level defects. These defects act as scattering centers, reducing mobility, and as charge recombination centers, reducing carrier lifetime, thereby degrading the overall device performance. Therefore, ion implantation doping techniques for 2D materials often disrupt their structural integrity, introducing defect states into the energy bands, thus reducing device performance.

[0003] Therefore, the academic community currently uses methods other than ion implantation to achieve doping of two-dimensional semiconductors. As a basic device unit, lateral pn homojunctions based on two-dimensional semiconductors often employ methods other than ion implantation to achieve doping, in order to circumvent the problems mentioned above. These include methods such as gate separation control, thickness engineering, ferroelectric polarization control, semi-floating gate control, chemical doping, and donor or acceptor doping. These methods achieve doping by adjusting the degree of band bending in the lateral direction of the channel material. However, previous methods typically have the following drawbacks.

[0004] Modulating charge density through a split gate requires a continuous external voltage input, making it difficult to achieve reconfigurable in-memory computing functionality. Furthermore, the non-uniform charge distribution induced by the gate may reduce the efficiency of surface light emission.

[0005] Thickness engineering and donor / acceptor doping methods are difficult to apply to industrial production because they rely on mechanical exfoliation. Furthermore, the thickness of the underlying materials cannot be precisely controlled, thus hindering precise bandgap modulation.

[0006] For ferroelectric-based modulation, nonvolatility remains a key challenge, and the fatigue problem of ferroelectric materials has not been fully resolved.

[0007] Semi-floating gates offer good retention and durability, but they cannot dynamically adjust the orientation of the lateral pn junction as flexibly as decoupled gates.

[0008] While chemical doping is effective, it is usually irreversible and can introduce defects and impurities; once completed, it is difficult to remove or adjust the doping level by simple means.

[0009] The existing technology (Li, D., Chen, M., Sun, Z. et al. Two-dimensional non-volatile programmable p–n junctions. Nature Nanotech 12, 901–906 (2017)) uses the charge of the floating gate as a modulation method, achieving good retention and durability. However, because it only has one floating gate, it can only modulate the energy band of one side of the contact, and the direction of the formed pn junction cannot be changed, resulting in a low barrier height and a relatively poor rectification ratio.

[0010] Therefore, developing a reliable, efficient, and programmable doping method for constructing lateral pn homojunctions based on two-dimensional semiconductors remains a challenge. Summary of the Invention

[0011] The purpose of this invention is to provide a transistor with a programmable horizontal double floating gate homojunction, which uses a double floating gate instead of a single-sided floating gate to control the energy bands of the two contacts, and can be freely formed and switched to any one of four junctions (pn junction, np junction, pp junction, nn junction).

[0012] The above-mentioned objective of the present invention is achieved through the following technical solution.

[0013] In a first aspect, the present invention provides a transistor having a programmable horizontal double floating gate homojunction, comprising:

[0014] Two independent floating grid layers composed of multiple layers of graphene;

[0015] The tunneling layer located above the floating grid layer;

[0016] The channel layer located above the tunnel layer;

[0017] The source and drain electrodes are respectively located above the two ends of the channel layer, so that the floating gate layer can achieve source-drain contact modulation, thereby ensuring that the floating gate electric field can modulate the Schottky barrier of the source and drain electrodes; and

[0018] Two direct tunneling electrodes, located above the two ends of the tunneling layer and not in contact with the channel layer, are used to inject charge into the floating gate layer.

[0019] The inventors of this application unexpectedly discovered that when a traditional graphite floating gate is separated into two parts using reactive ion etching, and a direct tunneling electrode is deposited on the tunneling layer of the floating gate for individually injecting charge into any one of the floating gates, the polarity and barrier height of the homojunction contact portion can be freely adjusted. Different charge polarities within the floating gate correspond to different channel polarities. Different charge densities within the floating gate result in different barrier heights in the junction region. Homojunctions controlled by this doping method can easily achieve the construction of pn, np, nn, and pp junctions.

[0020] Preferably, in the transistor with a programmable horizontal double floating gate homojunction according to the present invention, the thickness of the floating gate layer is 3nm-20nm.

[0021] Preferably, in the transistor with a programmable horizontal double floating gate homojunction according to the present invention, the tunneling layer is composed of one or more insulating gate dielectric materials selected from hexagonal boron nitride, SiO2, Al2O3 and HfO2.

[0022] Preferably, in the transistor with a programmable horizontal double floating gate homojunction according to the present invention, the channel layer is composed of one or more two-dimensional semiconductor materials selected from WSe2, MoS2, WS2 and MoTe2.

[0023] Preferably, in the transistor with a programmable horizontal double floating gate homojunction according to the present invention, the thickness of the tunneling layer is 7nm-20nm.

[0024] Preferably, in the transistor with a programmable horizontal double floating gate homojunction according to the present invention, the thickness of the channel layer is 3nm-15nm.

[0025] Preferably, in the transistor with a programmable horizontal double floating gate homojunction according to the present invention, the transistor further includes a barrier layer located below the floating gate layer.

[0026] Preferably, in the transistor with a programmable horizontal double floating gate homojunction according to the present invention, the barrier layer is composed of SiO2.

[0027] Preferably, in the transistor with a programmable horizontal double floating gate homojunction according to the present invention, the transistor further includes a control gate located below the barrier layer.

[0028] Preferably, in the transistor with a programmable horizontal double floating gate homojunction according to the present invention, the control gate is made of Si(P) ++ It is composed of heavily doped p-type Si.

[0029] Secondly, the present invention provides a method for fabricating a transistor having a programmable horizontal double floating gate homojunction, comprising the following steps in sequence:

[0030] (1) The materials constituting the channel layer, tunneling layer and floating grid layer are separated by mechanical stripping method to obtain the thin material of the channel layer, the thin material of the tunneling layer and the thin material of the floating grid layer;

[0031] (2) The thin layer material of the floating gate layer is transferred and stacked on the barrier layer;

[0032] (3) The floating gate layer thin film material is divided into two independent floating gate layers composed of multiple layers of graphene using electron beam lithography and reactive ion etching technology;

[0033] (4) The thin material of the tunneling layer and the thin material of the trench layer are sequentially transferred and stacked on the floating grid layer to form the tunneling layer and the trench layer respectively;

[0034] (5) The source and drain are fabricated above the two ends of the channel layer using electron beam lithography and metal evaporation technology, so that the floating gate layer can achieve source-drain contact control, thereby ensuring that the floating gate electric field can control the Schottky barrier of the source and drain.

[0035] (6) Two direct tunneling electrodes are fabricated at positions located above the two ends of the tunneling layer and not in contact with the channel layer using electron beam lithography and metal evaporation technology, so as to inject charge into the floating gate layer.

[0036] In a specific embodiment of the present invention, a silicon chip with a 285 nm silicon dioxide layer, i.e., SiO2 / Si(P) ++ The graphene was then subjected to oxygen plasma treatment. Next, multilayer graphene was transferred using a dry transfer method with 3M tape and annealed at 400°C for 200 minutes in a vacuum furnace containing 10% H2 / Ar atmosphere. Subsequently, few-layer graphene was patterned by electron beam lithography and subjected to oxygen plasma treatment. Using a transfer stage under an optical microscope, mechanically exfoliated h-BN and WSe2 on PDMS were aligned and transferred onto a graphene floating gate. The operation was performed in a glove box with O2 and H2O concentrations below 0.1 ppm. 5 / 50 nm Cr / Au metal electrodes were fabricated using conventional electron beam lithography, electron beam deposition, and exfoliation processes. The thicknesses of WSe2, h-BN, and MLG sheets were measured using atomic force microscopy (AFM, Asylum Research, Cypher S) in ambient conditions under tapping mode.

[0037] The present invention has the following beneficial effects:

[0038] 1. No external power supply required for continuous operation.

[0039] Decoupled gates require a continuous external voltage supply, which cannot meet current requirements for low power consumption and programmability. Using a decoupled dual floating gate, after programming, the charge within the floating gate naturally regulates the channel to form a homojunction, eliminating the need for external voltage support.

[0040] 2. Compatible with current industrial processes

[0041] Floating gate technology has achieved great success in industry due to its unique non-volatile characteristics, stable storage density, and mature manufacturing advantages. Semi-floating gate structures have also been realized industrially, so this horizontal dual-floating gate structure is not particularly difficult to manufacture and has strong compatibility with silicon-based processes.

[0042] 3. Excellent non-volatile properties

[0043] In existing technologies, ferroelectric modulation shares advantages with some dual-floating-gate modulation methods, such as homojunction orientation, non-volatility, and precise bandgap adjustment. However, ferroelectric fatigue remains a problem that needs to be fully solved, making ferroelectric modulation inferior to floating-gate modulation in terms of durability and non-volatility. In industrial applications, floating-gate modulation can achieve millions of rewrite cycles and decades of storage time, which ferroelectric modulation cannot achieve.

[0044] 4. Improve the electrical performance of two-dimensional semiconductor devices

[0045] Compared to the control of a half-side floating gate, the double-side floating gate of this invention can more conveniently and precisely control the band gap on both sides of the channel to improve the electrical performance of its horizontal homojunction, such as rectification ratio, ideality factor, and photovoltage responsivity. The purpose of this electrostatic doping method is to compensate for the shortcomings of ion implantation in two-dimensional semiconductor doping, thereby expanding the application range of two-dimensional semiconductor devices.

[0046] 5. Horizontal homojunction programming is simple and versatile, allowing independent control of both floating gates. The device can be programmed and erased via both FN tunneling and direct tunneling. Simultaneous programming of both floating gates can be achieved by applying a ±30V, 160ns voltage pulse to the control gate. Alternatively, individual control (electron or hole injection) of the source or drain floating gate can be achieved by applying a ±15V, 1.6μs voltage pulse to the direct tunneling electrode at the source or drain. After injecting charge into the floating gates using these two methods, pn, np, nn, and pp homojunctions can be easily realized.

[0047] 6. This invention has considerable application prospects. Specifically, it can be used in: floating gate memory arrays, reconfigurable logic circuits, two-dimensional semiconductor logic devices, optoelectronic devices, low-light detectors, and photovoltaic cells. Attached Figure Description

[0048] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings, wherein:

[0049] Figure 1 The structure and band diagram of a WSe2 lateral homojunction transistor with dual floating gate control according to Embodiment 1 of the present invention are shown.

[0050] Figure 2 The transistor working principle, pn junction rectification curve, control gate transfer curve, source tunneling electrode transfer curve, and drain electrode transfer curve of Embodiment 1 of the present invention are shown.

[0051] Figure 3 The data retention performance, durability test, and two types of inverters of the transistor of Embodiment 1 of the present invention are shown.

[0052] Figure 4 The photovoltaic and photoelectric characteristics of the transistor of Embodiment 1 of the present invention are shown;

[0053] Figure 5 The diagram shows the fill factor, photoelectric conversion efficiency, photovoltaic responsivity, open-circuit voltage, and short-circuit current of the transistor in Embodiment 1 of the present invention under different optical powers. Detailed Implementation

[0054] The present invention will be further described in detail below with reference to specific embodiments. The embodiments given are only for illustrating the present invention and are not intended to limit the scope of the present invention.

[0055] Example 1

[0056] (1) Preparation of two-dimensional material master tape

[0057] Using Scotch-Coated Invisible Tape, adhere it to a block of graphite (Gr), hexagonal boron nitride (h-BN), or tungsten diselenide (WSe2), and quickly peel off a layer of two-dimensional material onto the tape. Tear off another piece of tape, stick it onto the tape containing the two-dimensional material, and then quickly peel it off again, causing the two-dimensional material to dissociate further, until the two-dimensional material reaches a sufficient thickness, resulting in the master tape of the two-dimensional material. The thickness of the multilayer graphene is 5nm, the h-BN is 15nm, and the WSe2 is 4nm.

[0058] (2) Transfer of multilayer graphene

[0059] For silicon wafers with a surface silica thickness of 285 nm, i.e., SiO2 / Si(P) ++The silicon wafer was then subjected to oxygen plasma treatment. The wafer was placed in an oxygen plasma cleaning agent, evacuated to 50 Pa, and 400 sccm of oxygen was introduced. After 1 minute to stabilize the airflow, the RF power supply was turned on, and the plasma bombarded the silicon wafer surface for 2 minutes. The chamber was opened, the wafer was removed, and the previously prepared graphene master tape was pressed firmly onto the silicon dioxide surface. The wafer, with the tape still attached, was placed on a 105°C hot plate and heated for 2 minutes, continuously pressing it down by hand to ensure full contact between the two-dimensional material and the silicon wafer surface. After cooling to room temperature, the tape was quickly peeled off, leaving the graphene on the silicon dioxide surface. Subsequently, the wafer was annealed at 400°C for 200 minutes in a vacuum furnace containing 10% H2 / Ar atmosphere.

[0060] (3) Fabrication of a separate graphite grating

[0061] A polymethyl methacrylate (PMMA) 950 A5 electron resist solution was spin-coated onto the target sample surface at 4000 r / min, and heated at 150℃ for 2 min on a hot stage to allow solvent evaporation. Using an electron beam lithography system, a strip dividing the graphite into two parts was exposed in the middle. After exposure, the graphite was developed for 30 s in a 1:3 mixture of methyl isobutyl ketone (MIBK) and isopropanol (IPA), and then fixed in IPA for 40 s to expose the graphite to be etched. Subsequently, the sample was placed in a reactive ion etching (RIE) machine using 100 sccm of O2 at a pressure of 100 mTorr and an RF power of 50 W for 40 s to separate a single graphite block into two graphite gratings. The sample was then immersed in acetone solution for 3 minutes to dissolve the electron resist, followed by cleaning with IPA to remove any remaining acetone and drying with a nitrogen gun.

[0062] (4) Preparation and transfer of h-BN and WSe2 nanosheets

[0063] Samples were adhered to pre-prepared h-BN and WSe2 master tapes using polydimethylsilane (PDMS). Thickness was determined by contrast under an optical microscope, and nanosheets of appropriate thickness were selected. In this example, the h-BN thickness was 15 nm, and the WSe2 thickness was 4 nm. The Gr / h-BN / WSe2 heterojunction was aligned and stacked using a transfer stage.

[0064] (5) Forming contact electrodes and direct tunneling electrodes

[0065] PMMA was spin-coated again, followed by a second exposure. This second exposure was primarily used to form the contact electrodes and the direct tunneling electrodes. The contact electrodes form the source and drain, located on both sides of WSe2, and above the two floating gates. The direct tunneling electrodes did not contact WSe2 but contacted h-BN, and were also positioned directly above the two floating gates. The optical microscopy image of the device is shown below. Figure 1After exposure, development and fixing are performed. The sample is placed in an electron beam evaporation chamber, and 5 nm of metallic chromium is deposited as an adhesion layer at a rate of 0.1 Å / s, and 50 nm of metallic gold is deposited as a contact electrode at a rate of 0.3 Å / s. The low-speed electrode deposition ensures minimal damage to the channel.

[0066] (6) Lift-off in acetone, heated to 50°C and immersed for 15 minutes to dissolve the electron resist and separate the metal. Then clean in isopropanol to remove acetone residue. The exposed electrodes remain on the silicon wafer, forming a double floating gate horizontal homojunction device.

[0067] It should be noted that the term V in the following diagram... DS Indicates the source-drain voltage; V DTS Indicates the direct tunneling electrode voltage at the source; V DTD Indicates the direct tunneling electrode voltage at the drain terminal; V BG Indicates back gate voltage; S represents source terminal; D represents drain terminal; FGS represents source floating gate; FGD represents drain floating gate; "h + " indicates a hole; "e - " represents electron; V" CG Indicates the control gate voltage; l DS Indicates source-drain current; V DD Indicates the operating voltage; GND indicates the ground terminal; V IN Indicates input voltage; V OUT Indicates the output voltage; P EL Indicates power generation capacity; l SC Represents short-circuit current; EQE represents external quantum efficiency; V OC This indicates the open-circuit voltage.

[0068] Figure 1 Figure 1 shows the transistor structure and energy band diagram of a WSe2 lateral homojunction controlled by a dual floating gate. Figure a is a schematic diagram of the WSe2 lateral homojunction device; Figure b is a photomicrograph of a typical WSe2 lateral homojunction device; Figure c is a circuit schematic diagram of the dual floating gate device; Figure d shows the energy band diagrams of different types of homojunctions under the condition of storing charge polarities in the two floating gates; Figure e shows the energy band diagrams of different floating gate polarities (FGD (floating gate on the drain side) and FGS (floating gate on the source side)) and V... DS Under these conditions, different current states and dominant carrier types exist within the device.

[0069] Figure 2This diagram illustrates the operation and electrical behavior of a programmable two-dimensional WSe2 lateral pn junction controlled by dual floating gates. Figure a shows the operating principle of the lateral dual floating gate device: Figure a(i) shows how an electron in the channel tunnels through the h-BN and stores in the two floating gates by applying a 30 V, 160 ns pulse to the back gate; Figure a(ii) shows how a hole passes through the h-BN and neutralizes the electrons in the floating gates by applying a 15 V, 1.6 μs pulse to the DTS (direct tunneling electrode on the source side); Figure a(iii) shows how, after storing opposite charges in the two floating gates, a V... DS = 1 V Measuring the channel current; Figure b shows the current after programming at V DS The output characteristic curves of a two-dimensional WSe2 homojunction at 1V. Figure c shows the output characteristic curves of a two-dimensional WSe2 homojunction at 1V. DS = 1 V, the transfer characteristic curve obtained by the voltage on the dual-scan back control gate; Figures d and e are the transfer characteristic curves at VDS = ±1 V when the FGD stores electrons (d) or holes (e), with a dual-scan voltage (range -15 to +15 V) applied to the DTS electrode from negative to positive and then back to negative.

[0070] Figure 3 This is a multi-stage non-volatile memory and digital inverter based on a two-dimensional WSe2 lateral homojunction. Figure a shows the effect of adjusting the polarity of the charges within the two floating gates at room temperature, and at V... DS Read the current I when = ±1 V DS The data records the evolution of three current levels over time, demonstrating the retention characteristics of non-volatile memory. The three numbers in parentheses represent the pulse polarity applied to the back gate, the pulse polarity applied to the DTD, and V, respectively. DS The polarity. For example, (1, 1, 1) represents applying a +30 V, 160 ns pulse to the back gate, followed by a +15 V, 1.6 μs pulse to the DTD (direct tunneling electrode on the drain side), and then... DS = 1 V measurement I DS Figures b and c show the alternating application of V when the FGS pre-stores electrons (b) or holes (c). DTS, 脉冲 = ±15 V, 1.6 μs and at V DS = ±1 V Read I DS The circuit alternates between three current levels to demonstrate the durability of the non-volatile memory. Figures d and f show inverter circuits based on the WSe2 homojunction, where FGS (or FGD) stores holes, the source electrode is grounded, and the drain and DTD (or DTS) electrodes are connected to the output and input terminals, respectively. DD The device is driven via a 5 GΩ resistor; Figure e shows the inverter at different V values ​​when DTS is used as an input. DDThe output curve below (the black curve is V) DD = 0.5 V, then increase from 0.5 to 2.5 V in 0.5 V steps. Figure g shows the inverter at different V values ​​when DTS is used as input. DD The output curve below (the black curve is VDD = 0.5 V, and then it changes from 0.5 V to 3 V in 0.5 V increments).

[0071] Figure 4 Figure 1 shows the photovoltaic and optoelectronic characteristics of WSe2 pn and np junctions. Figure a is a schematic diagram of the WSe2 homojunction device under 633 nm laser irradiation; Figure b shows the output curves of the WSe2 np (top) and pn (bottom) junctions under darkness (black) and 633 nm laser irradiation with 5.62 nW power (red); Figure c shows the I²S of the two-dimensional WSe2 pn homojunction under darkness and 633 nm laser irradiation with different powers. DS -V DS Output curves; laser power increases sequentially from 0 (black) to 0.09 (red), 0.22 (blue), 2.8 (green), 22.4 (purple), and 180 (khaki) nW; Figure d shows the output power at V... DS At 0 V, the short-circuit photocurrent of the WSe2 np (red) and pn (blue) junctions changes over time under dark conditions and illumination with a 5.62 nW 633 nm laser, showing a clear and stable photoelectric response of the WSe2p-n and np junctions; Figure e shows the short-circuit photocurrent of the WSe2 np (red) and pn (blue) junctions at 0 V. DS At 0 V, the photocurrent of the WSe2 pn junction changes with increasing 633 nm laser power; Figure f shows the output electrical power (P) at different laser powers. EL ) with V DS The changing relationship.

[0072] Figure 5 The short-circuit current (I) of the WSe2 pn homojunction SC ) and open-circuit voltage (V OC ) with incident laser power (P) 激光 The relationship between the changes in open-circuit voltage (V) and the photoelectric properties of the WSe2 homojunction under different laser powers is shown in Figure a. OC ), short-circuit current (I) SC ), maximum output power (P) EL, MAX ), fill factor (FF), power conversion efficiency (η) EPCE ) and responsiveness; Figure b shows, I SC With P 激光 The changes demonstrate a power-law relationship I SC ∝ P 激光 α, where α = 0.96; Figure c shows the I from (b). SC -P 激光 P extracted by curve fitting 激光 Dependent external quantum efficiency (EQE). Figure d shows P. 激光 V on the logarithmic scale OC The relationship between the changes is that β = 1.53 is extracted from the linear fitting curve.

[0073] The embodiments of the present invention demonstrate the following facts.

[0074] 1. Homojunction exhibits excellent electrical performance.

[0075] After programming, the pn and np homojunctions are in V DS When the voltage is ±1V, it can reach 10. 5 The rectification ratio. In V DS When V = 1 V, the forward conduction current is approximately 1 × 10⁻⁶. -8 A, V DS When the voltage is -1 V, the reverse cutoff current is approximately 1 × 10⁻⁶. -13 A. Substituting into the Shockley equation, the ideality factors of the two junctions are found to be 1.56 and 1.57, respectively, which fully demonstrates the interchangeability consistency and electric field symmetry of the homojunction.

[0076] 2. Excellent storage performance

[0077] As a homojunction for floating gate control, its retention time and durability are outstanding. It has four junctions (pn junction, np junction, nn junction, pp junction) and two current directions (V... DS = +1 V、V DS = -1 V), with no significant current drop within 500 s across a total of 8 current states, indicating excellent current retention. The device can freely switch between the 8 current states, and experiments have shown that there is no significant current degradation in 250 cycles of 8-state transitions, demonstrating excellent durability and suitability for repeated use.

[0078] 3. Implementation of inverter logic

[0079] Figure 3 Figures d and f show two circuit diagrams illustrating inverter logic. The logic operation function can be achieved by adjusting the junction type through different charge injections. The inverter operates at V... DD A gain of 4.3 is achieved at 3.0 V.

[0080] 4. The device can achieve low-light detection.

[0081] Under 0.09 nW, 633 nm laser irradiation, the device can achieve 6.67 × 10⁻⁶.9 The photovoltaic response in V / W. The external quantum effect EQE of the device peaks at 2.4% under 0.22 nW, 633 nm laser irradiation.

[0082] Compared to previous methods (discrete gate, ferroelectric modulation, surface charge transfer doping, semi-floating gate doping, thickness engineering), the doping method of this invention requires no external power supply after programming, can maintain the programmed state for a long time, and can repeatedly modify the programming state. The orientation and barrier height of the pn junction can be freely adjusted and maintained. Floating gates, as a mature industrial product, are compatible with silicon-based processes and are not difficult to industrialize.

Claims

1. A transistor having a programmable horizontal double floating gate homojunction, comprising: Two independent floating grid layers composed of multiple layers of graphene; The tunneling layer located above the floating grid layer; The trench layer located above the tunnel layer; The source and drain are located above the two ends of the channel layer, respectively, so that the floating gate layer can control the source and drain contacts, thereby ensuring that the floating gate electric field can control the Schottky barrier of the source and drain. as well as Two direct tunneling electrodes, located above the two ends of the tunneling layer and not in contact with the channel layer, are used to inject charge into the floating gate layer.

2. The transistor with a programmable horizontal double floating gate homojunction according to claim 1, wherein, The thickness of the floating gate layer is 3nm-20nm.

3. The transistor with a programmable horizontal double floating gate homojunction according to claim 1, wherein, The tunneling layer is composed of one or more materials selected from hexagonal boron nitride, SiO2, Al2O3 and HfO2.

4. The transistor having a programmable horizontal double floating gate homojunction according to claim 1, wherein, The channel layer is composed of one or more materials selected from WSe2, MoS2, WS2 and MoTe2.

5. The transistor having a programmable horizontal double floating gate homojunction according to claim 1, wherein, The thickness of the tunneling layer is 7nm-20nm.

6. The transistor having a programmable horizontal double floating gate homojunction according to claim 1, wherein, The thickness of the channel layer is 3nm-15nm.

7. The transistor having a programmable horizontal double floating gate homojunction according to claim 1, wherein, The transistor also includes a barrier layer located below the floating gate layer.

8. The transistor having a programmable horizontal double floating gate homojunction according to claim 7, wherein, The barrier layer is composed of SiO2.

9. The transistor having a programmable horizontal double floating gate homojunction according to claim 1, wherein, The transistor also includes a control gate located below the barrier layer; Preferably, the control gate is made of Si(P) ++ )constitute.

10. A method for fabricating a transistor having a programmable horizontal double floating gate homojunction as described in any one of claims 1-9, comprising the following steps in sequence: (1) The materials constituting the channel layer, tunneling layer and floating grid layer are separated by mechanical stripping method to obtain the thin material of the channel layer, the thin material of the tunneling layer and the thin material of the floating grid layer; (2) The thin layer material of the floating gate layer is transferred and stacked on the barrier layer; (3) The floating gate layer thin film material is divided into two independent floating gate layers composed of multiple layers of graphene using electron beam lithography and reactive ion etching technology; (4) The thin material of the tunneling layer and the thin material of the trench layer are sequentially transferred and stacked on the floating grid layer to form the tunneling layer and the trench layer respectively; (5) The source and drain are fabricated above the two ends of the channel layer using electron beam lithography and metal evaporation technology, so that the floating gate layer can achieve source-drain contact control, thereby ensuring that the floating gate electric field can control the Schottky barrier of the source and drain. (6) Two direct tunneling electrodes are fabricated at positions located above the two ends of the tunneling layer and not in contact with the channel layer using electron beam lithography and metal evaporation technology, so as to inject charge into the floating gate layer.

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