P-GaN HEMT device and preparation method thereof

Abstract

According to the p-GaN HEMT device and the preparation method thereof provided by the invention, the insertion layer with a specific energy band structure is introduced between the p-GaN cap layer and the gate metal layer, so that asymmetric regulation and control of electron and hole transport are realized. Specifically, the conduction band bottom energy of the insertion layer is higher than the conduction band bottom energy of the p-GaN cap layer, and the valence band top energy of the insertion layer is higher than the valence band top energy of the p-GaN cap layer, so that the electron barrier is remarkably improved by the energy band design, and the injection of electrons from the p-GaN cap layer to the gate metal layer interface is effectively inhibited, thereby avoiding the continuous bombardment of channel electrons to the gate interface, and improving the performance of the device. And the threshold voltage stability and the gate reliability of the device are obviously improved. Meanwhile, the lower hole potential barrier ensures that holes can be effectively injected into the p-GaN cap layer, the hole shortage problem of the device under the high-voltage or large-current working condition is relieved, and the current collapse and the dynamic on-resistance are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device manufacturing, in particular to a p-GaN HEMT device and a preparation method thereof. BACKGROUND

[0002] With the rapid development of fast charging, 5G base stations and electric vehicles, the demand for high-reliability gallium nitride high electron mobility transistor (GaN HEMT) devices has surged, among which p-GaN gate HEMT has become the mainstream solution due to its normally off characteristics. However, the gate breakdown voltage (BV_g) of existing p-GaN HEMT devices is insufficient, leading to many problems. When switching at high frequencies, the gate withstands transient voltage spikes, for example, when the inductive load is turned off, local breakdown is prone to occur in the conventional structure. During long-term operation, charge injection caused by gate leakage can change the ionization state of the p-GaN layer, leading to unstable threshold voltage, for example, the threshold voltage drift of the electric vehicle motor drive is required to be less than 0.3V. In addition, in the wafer acceptance test, gate breakdown is one of the main failure modes, which seriously affects the process yield and cost of the device.

[0003] To solve the above problems, existing solutions have certain limitations. For example, increasing the thickness of the p-GaN layer can increase the gate breakdown voltage by about 20%, but a too thick p-GaN layer will cause the magnesium (Mg) doping activation rate to decrease, the threshold voltage to shift positively, and it will be difficult to meet the demand for low on-resistance. Another solution is to insert an n-GaN layer under the gate metal to form a PN junction to enhance the gate voltage resistance, but this method needs to offset the memory effect of Mg doping, and the inserted n-GaN layer usually has a high doping concentration and a thick thickness (about 15nm), which causes the gate metal to be far away from the aluminum gallium nitride (AlGaN) / GaN channel layer, which is not conducive to pinch off the channel, resulting in more serious short channel effects such as drain high voltage under off-state, causing the device off-state current to increase, and hindering the development of gallium nitride devices to short gate length and low voltage applications. In addition, by adding an insulating layer between the gate metal and the p-GaN to form a metal-insulator-semiconductor (MIS) gate structure, the gate reliability can be improved, but the nanoscale oxidation depth and conditions are difficult to control, and the gate operating voltage can be improved by limited (about 1V). There is also atomic layer deposition (ALD) growth of aluminum oxide (Al2O3) on the p-GaN to prepare a gate dielectric, but this method requires additional ALD equipment, and a thicker insulating medium will block the injection of holes from the metal into the p-GaN, causing the p-GaN region to be in an electrically floating state, hindering the opening of the device. SUMMARY

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a p-GaN HEMT device and a preparation method thereof, which are used to solve the problems of insufficient gate breakdown voltage and unstable threshold voltage of the p-GaN HEMT device in the prior art.

[0005] To achieve the above-mentioned purpose and other related purposes, the present application provides a preparation method of a p-GaN HEMT device, which comprises the following steps:

[0006] providing a substrate, and sequentially forming a buffer layer, a channel layer and a barrier layer on the substrate;

[0007] forming a p-GaN cap layer on a preset gate position of the barrier layer;

[0008] forming an insertion layer on the p-GaN cap layer, and forming a gate metal layer on the insertion layer; the valence band maximum energy of the p-GaN cap layer is E v1 , the conduction band minimum energy of the p-GaN cap layer is E c1 , the valence band maximum energy of the insertion layer is E v2 , and the conduction band minimum energy of the insertion layer is E c2 ; wherein, E c2 <E c1 , E v2 <E v1 +0.5eV;

[0009] forming a source layer and a drain layer on a preset position of the barrier layer, and forming a passivation layer on the barrier layer between the source layer, the p-GaN cap layer and the drain layer.

[0010] Optionally, a carbon-doped GaN layer is further formed between the buffer layer and the channel layer.

[0011] Optionally, the material of the barrier layer comprises AlGaN.

[0012] Optionally, the thickness of the insertion layer is 0.5nm-10nm.

[0013] Optionally, the process method for forming the insertion layer on the p-GaN cap layer comprises MOCVD process, PECVD process, LPCVD process or ALD process.

[0014] Optionally, E v1 =7.5eV, E c1 =4.1eV, E c2 <4.1eV, and E v2 <8eV.

[0015] Optionally, the material of the insertion layer comprises SiN or h-BN.

[0016] The application further provides a p-GaN HEMT device, comprising:

[0017] a substrate, a buffer layer, a channel layer and a barrier layer formed in sequence on the substrate;

[0018] a p-GaN cap layer formed on a preset gate position of the barrier layer;

[0019] an insertion layer formed on the p-GaN cap layer, wherein the valence band maximum energy of the p-GaN cap layer is E v1 , the conduction band minimum energy of the p-GaN cap layer is E c1 , the valence band maximum energy of the insertion layer is E v2 , and the conduction band minimum energy of the insertion layer is E c2 ; wherein E c2 <E c1 , E v2 <E v1 +0.5eV.

[0020] a gate metal layer formed on the insertion layer;

[0021] a source layer and a drain layer formed on a preset position of the barrier layer;

[0022] a passivation layer formed on the barrier layer between the source layer, the p-GaN cap layer and the drain layer.

[0023] Optionally, the material of the insertion layer comprises SiN or h-BN.

[0024] Optionally, the thickness of the insertion layer is 0.5nm-10nm.

[0025] As described above, the p-GaN HEMT device and the preparation method thereof have the following beneficial effects: by introducing the insertion layer with specific band structure between the p-GaN cap layer and the gate metal layer, asymmetric regulation of electron and hole transport is realized. Specifically, the conduction band minimum energy (E c2 ) of the insertion layer is higher than the conduction band minimum energy (E c1 ) of the p-GaN cap layer, and the valence band maximum energy (E v2 ) of the insertion layer is higher than the valence band maximum energy (E v1), which significantly improves the electron potential barrier, effectively suppresses the injection of electrons from the p-GaN cap layer to the gate metal layer interface, thereby avoiding the continuous bombardment of the channel electrons on the gate interface, and significantly improving the threshold voltage stability and gate reliability of the device. At the same time, the lower hole potential barrier ensures that the holes can be effectively injected into the p-GaN cap layer, alleviating the problem of hole deficiency of the device under high voltage or large current working conditions, reducing the current collapse and dynamic on-resistance, solving the problems of insufficient gate breakdown voltage and unstable threshold voltage of the p-GaN HEMT device in the prior art, and being particularly suitable for high-voltage (650V) to medium-low-voltage (40V~200V) power devices. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A flowchart showing the preparation method of the p-GaN HEMT device of the present application.

[0027] Figure 2 A cross-sectional structure schematic diagram of the p-GaN HEMT device of the present application.

[0028] Figure 3 A band diagram of the p-GaN and the insertion layer of the present application.

[0029] Element number explanation: 1 substrate, 2 buffer layer, 3 carbon-doped GaN layer, 4 channel layer, 5 barrier layer, 6 passivation layer, 7 source layer, 8 drain layer, 9 p-GaN cap layer, 10 insertion layer, 11 gate metal layer, S1~S4 steps. DETAILED DESCRIPTION

[0030] The embodiments of the present application will be described in detail below with specific reference to specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the disclosure of the present specification. The present application can also be implemented or applied in different specific embodiments, and various modifications or changes can be made to the details in the specification without departing from the spirit of the present application.

[0031] Please refer to Figures 1 to 3 . It should be noted that the diagrams provided in the present embodiment only illustrate the basic concept of the present application in a schematic manner, and only show the components related to the present application in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be arbitrarily changed in terms of shape, number and proportion, and the layout pattern of the components may be more complex.

[0032] The present embodiment provides a preparation method of a p-GaN HEMT device, as shown in Figure 1 The preparation method comprises:

[0033] S1, providing a substrate, and sequentially forming a buffer layer, a channel layer and a barrier layer on the substrate;

[0034] S2, a p-GaN cap layer is formed at a preset gate position of the barrier layer;

[0035] S3, an insertion layer is formed on the p-GaN cap layer, and a gate metal layer is formed on the insertion layer; the valence band top energy of the p-GaN cap layer is E. v1 The conduction band bottom energy of the p-GaN cap layer is E c1 The valence band top energy of the inserted layer is E v2 The conduction band bottom energy of the insertion layer is E c2 Among them, E c2 <E c1 E v2 <E v1 +0.5eV;

[0036] S4, a source layer and a drain layer are formed at a preset position of the barrier layer, and a passivation layer is formed on the barrier layer between the source layer, the p-GaN cap layer and the drain layer.

[0037] The fabrication method of the p-GaN HEMT device in this embodiment achieves asymmetric control of electron and hole transport by introducing an insertion layer with a specific band structure between the p-GaN cap layer and the gate metal layer. Specifically, the conduction band bottom energy (E0) of this insertion layer... c2 The conduction band bottom energy (E) is higher than that of the p-GaN cap layer. c1 ), and its valence band peak energy (E) v2 The energy is higher than the valence band top energy of the p-GaN cap layer (E). v1 This bandgap design significantly enhances the electron barrier, effectively suppressing electron injection from the p-GaN cap layer to the gate metal layer interface. This prevents continuous bombardment of the gate interface by channel electrons, significantly improving the device's threshold voltage stability and gate reliability. Simultaneously, the lower hole barrier ensures effective hole injection into the p-GaN cap layer, alleviating hole depletion issues under high voltage or high current operating conditions, reducing current collapse and dynamic on-resistance, and resolving the problems of insufficient gate breakdown voltage and unstable threshold voltage in existing p-GaN HEMT devices.

[0038] The method for fabricating the semiconductor packaging structure of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0039] like Figure 2 As shown, in step S1, a substrate 1 is provided, and a buffer layer 2, a channel layer 4 and a barrier layer 5 are sequentially formed on the substrate 1.

[0040] As an example, the material of the substrate 1 includes one of silicon (Si), sapphire, silicon carbide (SiC) and silicon germanium (SiGe), which can be designed according to actual needs, and is not limited here.

[0041] Specifically, the channel layer 4 and the barrier layer 5 are different materials, and a two-dimensional electron gas is formed at the interface of the channel layer 4 and the barrier layer 5, which serves as the channel of the HEMT device and provides a conductive channel between the source 7 and the drain 8 of the device. The forming method and material of the buffer layer 2, the channel layer 4 and the barrier layer 5 can be designed according to actual needs, and are not limited here. The material of the barrier layer 4 includes but is not limited to AlGaN, and can further be Al 0.25 Ga 0.75 N.

[0042] As an example, a carbon-doped GaN layer 3 can be formed between the buffer layer 2 and the channel layer 4 to reduce the leakage of the HEMT device. Other transition layers can also be formed between the buffer layer 2 and the channel layer 4, which can be designed according to actual needs, and are not limited here.

[0043] As Figure 2 shown, step S2 is performed to form a p-GaN cap layer 9 on the preset gate position of the barrier layer 5.

[0044] As Figure 2 shown, step S3 is performed to form an insertion layer 10 on the p-GaN cap layer 9, and a gate metal layer 11 on the insertion layer 10. Figure 3 As shown, the valence band maximum energy of the p-GaN cap layer 9 is E v1 , the conduction band minimum energy of the p-GaN cap layer 9 is E c1 , the valence band maximum energy of the insertion layer 10 is E v2 , and the conduction band minimum energy of the insertion layer 10 is E c2 ; wherein E c2 <E c1 , E v2 <E v1 +0.5eV. That is, the conduction band minimum energy (E c2 ) of the insertion layer 10 is lower than the conduction band minimum energy (E c1 ) of the p-GaN cap layer 9, and the valence band maximum energy (E v2 ) of the insertion layer 10 is lower than the valence band maximum energy (E v1) plus 0.5eV, this band matching structure significantly improves the electron barrier, effectively inhibits the injection of electrons from the p-GaN cap layer 9 to the interface of the gate metal layer 11, thereby avoiding the continuous bombardment of the channel electrons on the gate interface in the on state, significantly improving the threshold voltage stability and gate reliability of the device. At the same time, the lower hole barrier ensures that the holes can be effectively injected into the p-GaN cap layer 9, alleviating the problem of hole deficiency of the device under high voltage or large current working conditions, and reducing the current collapse and dynamic on-resistance.

[0045] As a specific example, the valence band top energy E v1 of the p-GaN cap layer 9 is 7.5eV, the conduction band bottom energy E c1 of the p-GaN cap layer 9 is 4.1eV, the conduction band bottom energy E c2 of the insertion layer 10 is less than 4.1eV, and the valence band top energy E v2 of the insertion layer 10 is less than 8eV.

[0046] As an example, the thickness of the insertion layer 10 is 0.5nm-10nm, so as to ensure that the carriers have a shorter transmission path during the operation of the HEMT device, thereby reducing the energy loss in the transmission process and improving the switching speed and overall performance of the device.

[0047] As an example, the process method for forming the insertion layer 10 on the p-GaN cap layer 9 includes but is not limited to metal organic chemical vapor deposition (MOCVD) process, plasma enhanced chemical vapor deposition (PECVD) process, low pressure chemical vapor deposition (LPCVD) process or atomic layer deposition (ALD) process.

[0048] As an example, the material of the insertion layer 10 includes silicon nitride (SiN) or hexagonal boron nitride (h-BN), and other materials with adapted band structure can also be selected according to requirements, not limited to the present embodiment.

[0049] As shown in Figure 2 , step S4 is performed to form a source layer 7 and a drain layer 8 on a predetermined position of the barrier layer 5, and a passivation layer 6 is formed on the barrier layer 5 between the source layer 7, the p-GaN cap layer 9 and the drain layer 8.

[0050] The above preparation method provided by the present embodiment is not limited in any step sequence, and can be reasonably adjusted according to requirements.

[0051] The source layer 7, the drain layer 8, the gate metal layer 11 and the passivation layer 6 can all be prepared by using conventional preparation methods in the art, which will not be described in detail here.

[0052] The embodiment also provides a p-GaN HEMT device, referring to Figure 2 , which comprises:

[0053] a substrate 1, a buffer layer 2, a channel layer 4 and a barrier layer 5 formed on the substrate 1 in sequence;

[0054] a p-GaN cap layer 9 formed on a preset gate position of the barrier layer 5;

[0055] an insertion layer 10 formed on the p-GaN cap layer 9, referring to Figure 3 , a valence band maximum energy of the p-GaN cap layer 9 is E v1 , a conduction band minimum energy of the p-GaN cap layer 9 is E c1 , a valence band maximum energy of the insertion layer 10 is E v2 , a conduction band minimum energy of the insertion layer 10 is E c2 ; wherein, E c2 <E c1 , E v2 <E v1 +0.5eV;

[0056] a gate metal layer 11 formed on the insertion layer 10;

[0057] a source layer 7 and a drain layer 8 formed on a preset position of the barrier layer 5;

[0058] a passivation layer 6 formed on the barrier layer 5 between the source layer 7, the p-GaN cap layer 9 and the drain layer 8.

[0059] The p-GaN HEMT device can be prepared by the preparation method of the p-GaN HEMT device described above, but is not limited thereto, and other suitable preparation methods can also be used, and the beneficial effects that can be achieved can be referred to the specific description in the preparation method, which will not be described here.

[0060] Specifically, as an example, the material of the insertion layer 10 comprises SiN or h-BN.

[0061] As a specific example, the valence band maximum energy E v1 of the p-GaN cap layer 9 is 7.5eV, the conduction band minimum energy E c1 of the p-GaN cap layer 9 is 4.1eV, the conduction band minimum energy E c2 of the insertion layer 10 is less than 4.1eV, and the valence band maximum energy E v2 of the insertion layer 10 is less than 8eV.

[0062] As an example, the thickness of the insertion layer 10 is 0.5nm-10nm.

[0063] In summary, the p-GaN HEMT device and the preparation method thereof of the present application, by introducing an insertion layer with a specific band structure between the p-GaN cap layer and the gate metal layer, realizes the asymmetric regulation of electron and hole transport. Specifically, the conduction band minimum energy (E c2 ) of the insertion layer is higher than the conduction band minimum energy (E c1 ) of the p-GaN cap layer, and the valence band maximum energy (E v2 ) of the insertion layer is higher than the valence band maximum energy (E v1 ) of the p-GaN cap layer. This band design significantly improves the electron barrier, effectively suppresses the injection of electrons from the p-GaN cap layer to the gate metal layer interface, thereby avoiding the continuous bombardment of the channel electrons on the gate interface, significantly improving the threshold voltage stability and gate reliability of the device. At the same time, the lower hole barrier ensures that the holes can be effectively injected into the p-GaN cap layer, alleviates the problem of hole deficiency of the device under high voltage or large current working conditions, reduces the current collapse and dynamic on-resistance, and solves the problems of insufficient gate breakdown voltage and unstable threshold voltage of the p-GaN HEMT device in the prior art. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0064] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for fabricating a p-GaN HEMT device, characterized in that, The preparation method includes: A substrate is provided, and a buffer layer, a channel layer and a barrier layer are sequentially formed on the substrate; A p-GaN cap layer is formed at a predetermined gate position of the barrier layer; An insertion layer is formed on the p-GaN cap layer, and a gate metal layer is formed on the insertion layer; the valence band top energy of the p-GaN cap layer is E. v1 The conduction band bottom energy of the p-GaN cap layer is E c1 The valence band top energy of the inserted layer is E v2 The conduction band bottom energy of the insertion layer is E c2 Among them, E c2 <E c1 E v2 <E v1 +0.5eV; A source layer and a drain layer are formed at a predetermined position of the barrier layer, and a passivation layer is formed on the barrier layer between the source layer, the p-GaN cap layer and the drain layer.

2. The method for fabricating the p-GaN HEMT device according to claim 1, characterized in that: A carbon-doped GaN layer is also formed between the buffer layer and the channel layer.

3. The method for fabricating a p-GaN HEMT device according to claim 1, characterized in that: The material of the barrier layer includes AlGaN.

4. The method for fabricating a p-GaN HEMT device according to claim 1, characterized in that: The thickness of the insertion layer is 0.5 nm to 10 nm.

5. The method for fabricating a p-GaN HEMT device according to claim 1, characterized in that: The process for forming the insertion layer on the p-GaN cap layer includes MOCVD, PECVD, LPCVD, or ALD processes.

6. The method for fabricating a p-GaN HEMT device according to claim 1, characterized in that: E v1 =7.5eV,E c1 =4.1eV,E c2 <4.1eV,E v2 <8eV。 7. The method for fabricating a p-GaN HEMT device according to claim 1, characterized in that: The material of the insertion layer includes SiN or h-BN.

8. A p-GaN HEMT device, characterized in that, The p-GaN HEMT device includes: A substrate and a buffer layer, a channel layer and a barrier layer sequentially formed on the substrate; A p-GaN cap layer is formed at a predetermined gate location of the barrier layer; An insertion layer is formed on the p-GaN cap layer, wherein the valence band top energy of the p-GaN cap layer is E. v1 The conduction band bottom energy of the p-GaN cap layer is E c1 The valence band top energy of the inserted layer is E v2 The conduction band bottom energy of the insertion layer is E c2 Among them, E c2 <E c1 E v2 <E v1 +0.5eV; A gate metal layer is formed on the insertion layer; The source layer and drain layer are formed at predetermined positions in the barrier layer; A passivation layer is formed on the barrier layer between the source layer, the p-GaN cap layer, and the drain layer.

9. The p-GaN HEMT device according to claim 8, characterized in that: The material of the insertion layer includes SiN or h-BN.

10. The p-GaN HEMT device according to claim 8, characterized in that: The thickness of the insertion layer is 0.5 nm to 10 nm.

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