Manufacturing method of trench gate device

Abstract

The invention discloses a manufacturing method of a trench gate device. The manufacturing method comprises the following steps: forming a trench gate; and forming a shielding oxide layer and controlling the thickness of the shielding oxide layer by adopting a dry etching process so that the thickness of the shielding oxide layer is uniform. And performing body injection to form a body region, wherein the thickness-uniform structure of the shielding oxide layer makes the bottom surface position of the body region flat. The shielding oxide layer is removed, and the vertex angle of the gate trench is recessed. And forming a vertex angle side wall at the vertex angle recess of the gate trench. Source injection is performed to form a source region, and the vertex angle side wall is used for reducing the depth of source injection downwards injected along the side surface of the gate trench, so that the channel length is accurately controlled, and source-drain punch-through caused by large channel length fluctuation when the channel length is shortened is prevented. According to the invention, the channel length can be accurately controlled, channel length fluctuation is reduced, the channel length can be shortened, source-drain punch-through is prevented when the channel length is shortened, and electric leakage is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device manufacturing method, in particular to a trench gate device manufacturing method. BACKGROUND

[0002] Power MOSFET devices play a core role in power electronic systems. The emergence of shield gate trench (SGT) MOS in the shield gate structure brings an opportunity for the improvement of the performance of medium and low voltage power MOSFET devices. The structure has the advantages of low on-resistance, fast switching speed, large safe working area, and small packaging, and has a broad market prospect in green home appliances and energy-saving systems. However, the traditional device has a large capacitance, and in the switching test, the loss is large and the switching frequency is low. It is necessary to reduce the switching loss of the power device. The key to reducing the loss is to reduce the capacitance of the power device, especially the Cgs and Cgd capacitances. Reducing the channel length of the power device is a frequently mentioned scheme to reduce the capacitance and improve the switching speed. However, in the actual manufacturing process, problems such as channel leakage often occur due to too short channel, and the uneven injection of the body region (Body) / source region such as N-type heavily doped (NP) source region in the process manufacturing process also causes leakage.

[0003] As shown in Figure 1 , it is a device structure schematic diagram after body injection and source injection in the manufacturing method of the existing SGT device; taking an N-type SGT MOSFET as an example, the formed SGT MOSFET device includes: An N-type substrate 101, i.e. a semiconductor substrate such as a silicon substrate, is used to provide mechanical support. According to the device characteristic parameters, an As or P doped substrate 101 can be selected. The higher the doping concentration of the substrate 101, the lower the Rsp of the device and the lower the power consumption.

[0004] An epitaxial layer 102 is formed on the substrate 101. The bottom of the body region 109 is the drift region, and the doping concentration and thickness of the epitaxial layer 102 depend on the breakdown voltage of the device; the higher the required breakdown voltage of the device, the lower the doping concentration of the drift region and the higher the thickness of the drift region.

[0005] A field oxide layer 103 is formed on the bottom surface and the bottom side of the gate trench, which is usually SiO2 and filled with N-type heavily doped shield polysilicon, i.e. source polysilicon 104, which is used to withstand voltage.

[0006] A gate-to-gate dielectric layer 105 is formed on the surface of the source polysilicon 104. The gate-to-gate dielectric layer 105 is usually an oxide layer and is usually deposited and etched by HDPCVD process, and is used to isolate the shield polysilicon and the polysilicon gate. The gate-to-gate dielectric layer 105 is also called interpoly oxide (IPO).

[0007] A polysilicon gate 107 is formed on the top region of the gate trench, and a gate oxide layer 106 is formed between the polysilicon gate 107 and the side surface of the gate trench.

[0008] Figure 1 As shown, the P-type doped body region 109 is formed by ion implantation on the surface region of the epitaxial layer 102. Generally, the ion implantation of the body region 109 will pass through a screen oxide 108, which is used to eliminate the tunneling effect during implantation. In the prior art, the screen oxide 108 is usually etched by a wet etching process, which will make the thickness of the screen oxide 108 uneven. The uneven thickness of the screen oxide 108 will also make the depth of the body implant uneven, Figure 1 As shown in FIG. 1C, the bottom surface of the body region 109 is uneven.

[0009] The N-type heavily doped source region 110 is also formed by ion implantation. The screen oxide 108 is removed before the source implantation, and then the implantation is performed so that the source region 110 is located on the surface region of the body region 109. However, generally, the side surface of the gate trench is a tilted structure with a top opening larger than a bottom opening. This tilted structure makes the depth of the source implantation at the side surface of the gate trench larger, Figure 1 As shown in FIG. 1D, the profile of the source region 110 is shown, and it can be seen that the depth of the bottom surface at the side surface of the gate trench is increased.

[0010] The surface of the body region 109 covered by the side surface of the polysilicon gate 107 of the trench gate at the bottom of the source region 110 is used to form a channel, and thus the channel length is the distance between the bottom surface of the source region 110 and the bottom surface of the body region 109. Since the bottom surface of the source region 110 is deeper at the side surface of the gate trench, the bottom surface of the body region 109 will fluctuate, and there is a high probability that the body region 109 at the bottom of the deeper source region 110 is shallower, which will make the channel length excessively reduced. Figure 1 As shown in FIG. 1E, L101 represents the channel length, and it can be seen that the value of L101 is smaller at the side surface of the gate trench, which will easily cause source-drain punchthrough and thus cause leakage.

[0011] After the source region 110 is formed, an interlayer dielectric (ILD) is formed, a contact hole (CT) and a front metal layer are formed, and the front metal layer is patterned to form a gate and a source. The top of the source region 110 and the body region 109 are connected to the source through the contact hole, and a P+ doped contact implant region (CT Implant) is usually formed at the bottom of the contact hole corresponding to the source region 110 to realize the ohmic contact between the body region 109 and the contact hole; the source polysilicon 104 is also connected to the source; and the polysilicon gate 107 is connected to the gate.

[0012] In the prior art, after the IPO layer is formed by HDPCVD, if a short-gate process is to be performed, the depth of wet etching of the active area (AA) has to be shallow, and the depth of the polysilicon gate will also be shallow, then the gate oxide layer is grown, and then the gate poly is deposited, the thickness of the deposited poly needs to be at least half of the width of the trench to ensure that the trench is completely filled, and then the gate poly is etched back.

[0013] The body implant depth is also reduced. Firstly, the gate trench etching has a certain inclination angle, and is inclined, the depth of the source implant, i.e. N+ implant, at the side of the gate trench is deep, and the thickness distribution of the body screen oxide is uneven, and the body implant, i.e. body implant, has a change in junction depth, which leads to a higher probability of punch-through at the side of the gate trench, resulting in channel leakage.

[0014] In the MOSFET, the channel region, i.e. the body region 109 and the drift region composed of the bottom epitaxial layer 102, will be depleted to withstand voltage. In the short-gate MOSFET, the channel region will be depleted prematurely due to insufficient channel length, which will cause the N-type drift region to connect to the N-type heavily doped source region 110, forming punch-through and increasing the leakage of the device. In addition, in the actual process, the control precision of the recess depth of the gate poly is poor, and the oxide distribution is uneven before the body implant and the N-type heavily doped (NP) ion implantation, i.e. source implant, which will cause the body implant junction depth to change. If the body junction depth is too shallow or the NP implantation depth is too deep, a considerable part of the channel will be inverted by the NP, resulting in a shorter channel length, and causing short-gate leakage. SUMMARY

[0015] The technical problem to be solved by the present application is to provide a trench gate device manufacturing method that can accurately control the flatness of the bottom surface of the body region and prevent the influence of the inclined side of the gate trench on the depth of the source region, thereby accurately controlling the channel length, reducing the fluctuation of the channel length, and facilitating the shortening of the channel length and preventing the occurrence of source-drain punch-through and reducing the leakage when the channel length is shortened.

[0016] To solve the above technical problems, the trench gate device manufacturing method provided by the present application controls the channel length to prevent the occurrence of source-drain punch-through when the channel length is shortened by the following steps: Forming a trench gate on a first epitaxial layer of a first conductivity type, the trench gate comprising a gate trench and a gate conductive material layer filled in the gate trench, the gate conductive material layer and the inner side surface of the corresponding gate trench being separated by a gate dielectric layer, the gate trench having a top opening larger than a bottom opening.

[0017] Forming a screen oxide on the surface of the first epitaxial layer where the trench gate is formed, and controlling the thickness of the screen oxide by a dry etching process to make the thickness of the screen oxide uniform.

[0018] Performing a body implant of a second conductivity type to form a body region in the surface region of the first epitaxial layer, the thickness uniformity of the screen oxide making the depth of the body implant uniform at different locations of the first epitaxial layer and making the bottom surface position of the body region flat.

[0019] Removing the screen oxide, the removal of the screen oxide causing a recess at the top corner of the gate trench.

[0020] Forming a top corner spacer at the recess of the top corner of the gate trench.

[0021] Performing a source implant of a first conductivity type heavy doping to form a source region in the surface region of the body region, the surface of the body region covered by the side surface of the trench gate being used to form a channel, the top corner spacer being used to reduce the depth of the source implant implanted downward along the side surface of the gate trench, thereby precisely controlling the distance between the bottom surface of the source region and the bottom surface of the body region at the side surface of the gate trench, i.e. the channel length, and preventing a large fluctuation of the channel length when the channel length is shortened, which causes source-drain punchthrough.

[0022] A further improvement is that the trench gate device comprises an SGT device, in which a source conductive material layer is further included in the gate trench, the source conductive material layer being located in the bottom region of the gate trench and being separated from the inner side surface of the gate trench by a source dielectric layer, and the source conductive material layer and the gate conductive material layer being separated by a gate-to-source dielectric layer.

[0023] A further improvement is that the top surface of the gate conductive material layer is further etched to be lower than the top surface of the first epitaxial layer outside the gate trench.

[0024] A further improvement is that after the dry etching of the screen oxide is completed, a wet cleaning is further performed to remove the damage to the surface of the first epitaxial layer caused by the dry etching of the screen oxide.

[0025] A further improvement is that the screen oxide is removed by wet soaking.

[0026] A further improvement is that the top corner side wall formation process includes: forming a top corner side wall material layer.

[0027] performing an anisotropic etch on the top corner side wall material layer to leave the top corner side wall material layer only at the top corner recesses and form the top corner side walls.

[0028] A further improvement is that the top corner side wall material layer includes an oxide layer.

[0029] A further improvement is that the top corner side wall material layer is formed to a thickness of 400 Angstroms.

[0030] A further improvement is that the process further includes the steps of: forming an interlayer dielectric film.

[0031] forming contact hole openings through the interlayer dielectric film and then filling the contact hole openings with a metal to form contact holes.

[0032] forming a front side metal layer and patterning the front side metal layer to form a source and a gate, the source region being connected to the source through a top corresponding contact hole and the gate electrode material layer being connected to the gate through a top corresponding contact hole.

[0033] A further improvement is that the process further includes the steps of: performing a second conductivity type heavily doped ion implant to form a contact implant region, the contact implant region and the contact hole forming an ohmic contact, the body region being connected to the contact hole through the contact implant region.

[0034] A further improvement is that the material of the gate dielectric layer includes an oxide.

[0035] The material of the gate electrode material layer includes polysilicon.

[0036] A further improvement is that the material of the source dielectric layer includes an oxide. The material of the source gate electrode material layer includes polysilicon.

[0037] The material of the gate inter-electrode dielectric layer includes an oxide.

[0038] A further improvement is that the trench gate device includes a trench gate MOSFET, the first epitaxial layer being formed on a semiconductor substrate.

[0039] A further improvement is that the process further includes the steps of: Thinning the semiconductor substrate, the semiconductor substrate is heavily doped with the first conductive type, the semiconductor substrate after thinning forms a drain region; or, the semiconductor substrate after thinning is formed with the drain region by backside ion implantation of the first conductive type heavy doping.

[0040] Forming a backside metal layer on the backside of the drain region and consisting of the backside metal layer to form a drain electrode.

[0041] Further improvement is that the material of the semiconductor substrate comprises silicon, and the material of the first epitaxial layer comprises silicon.

[0042] Further improvement is that the trench gate device is an N-type device, the first conductive type is N-type, and the second conductive type is P-type; or, the trench gate device is a P-type device, the first conductive type is P-type, and the second conductive type is N-type.

[0043] The present application makes comprehensive settings to the manufacturing process of the trench gate device according to the need of precisely controlling the channel length, mainly to the forming process of the body region and the source region closely related to the channel length, wherein the present application changes the etching of the shielding oxide layer formed before the body implantation from the existing conventional wet etching to dry etching process, and uses the dry etching process to make the thickness of the shielding oxide layer uniformly distributed, since the ions of the body implantation will pass through the shielding oxide layer into the first epitaxial layer, therefore, after the thickness of the shielding oxide layer is uniformly distributed, the depth of the body implantation is also uniform, thus the flatness of the bottom surface of the body region is also improved, preventing the bottom surface of the body region from fluctuating too much, thus preventing the bottom surface of the body region from being too shallow.

[0044] Meanwhile, the present application forms a top corner side wall at the top corner recess of the gate trench formed after the shielding oxide layer is removed before the source implantation, the top corner side wall can increase the implantation path at the side of the gate trench, preventing the source implantation from being too deep at the side of the gate trench combined with the top corner recess, i.e. the bottom surface of the source region is too deep. Since the bottom of the source region is used to form the channel with the body region surface of the trench gate side, therefore, the channel length is the distance between the bottom surface of the source region and the bottom surface of the body region, since the present application can prevent the bottom surface of the source region from being too deep and the bottom surface of the body region from being too shallow, therefore, it can prevent the channel length from being too short, under the condition of the designed shortened channel length, further shortened channel length caused by process fluctuation will make the channel length exceed the target value range, thus causing source-drain punchthrough, therefore, the present application can prevent source-drain punchthrough and reduce the leakage caused by source-drain punchthrough. BRIEF DESCRIPTION OF DRAWINGS

[0045] The present application will be further described in detail below in combination with the drawings and specific embodiments: Figure 1is a device structure diagram after body implantation and source implantation are completed in a manufacturing method of an existing SGT device; Figure 2 is a flow chart of a manufacturing method of a trench gate device in an embodiment of the present application; Figures 3A-3H is a device structure diagram in each step of the manufacturing method of the trench gate device in the embodiment of the present application. DETAILED DESCRIPTION

[0046] As Figure 2 shown, is a flow chart of a manufacturing method of a trench gate device in an embodiment of the present application; as Figures 3A to 3H shown, is a device structure diagram in each step of the manufacturing method of the trench gate device in the embodiment of the present application; the manufacturing method of the trench gate device in the embodiment of the present application adopts the following steps to control the channel length to prevent source-drain punchthrough when the channel length is shortened, comprising: Step S101, as Figure 3A shown, a semiconductor substrate 1 formed with a first epitaxial layer 2 doped with a first conductive type is provided.

[0047] In the embodiment of the present application, the material of the semiconductor substrate 1 includes silicon, and the material of the first epitaxial layer 2 includes silicon. In other embodiments, the semiconductor substrate 1 and the first epitaxial layer 2 can also adopt other semiconductor materials as needed.

[0048] As Figure 3C shown, a trench gate is formed on the first epitaxial layer 2 doped with the first conductive type. The trench gate includes a gate trench and a gate conductive material layer 7 filled in the gate trench, the gate conductive material layer 7 and the inner side surface of the corresponding gate trench are separated by a gate dielectric layer 6, and the gate trench has an inclined appearance with a top opening larger than a bottom opening.

[0049] In the embodiment of the present application, the trench gate device is an SGT device. In this application, the SGT device is taken as an example for description, and the embodiment of the present application is also applicable to other trench gate devices. In the SGT device, a source conductive material layer 4 is also included in the gate trench, the source conductive material layer 4 is located in the bottom region of the gate trench and is separated from the inner side surface of the gate trench by a source dielectric layer 3. A gate-to-gate dielectric layer 5 is separated between the source conductive material layer 4 and the gate conductive material layer 7.

[0050] Therefore, as Figure 3B shown, before the gate dielectric layer 6 and the gate conductive material layer 7 are formed, the source dielectric layer 3 and the source conductive material layer 4 need to be formed in the bottom region of the gate trench first.

[0051] As Figure 3C shown, then further comprising: forming a gate-to-gate dielectric layer 5.

[0052] Then, the gate dielectric layer 6 and the gate conductive material layer 7 are formed. In this embodiment of the invention, the top surface of the gate conductive material layer 7 is also etched back onto the top surface of the first epitaxial layer 2 below the gate trench.

[0053] In some embodiments, the material of the gate dielectric layer 6 includes oxides.

[0054] The material of the gate conductive material layer 7 includes polycrystalline silicon.

[0055] The material of the source dielectric layer 3 includes oxides.

[0056] The source and gate conductive material layer 7 is made of polysilicon.

[0057] The material of the inter-gate dielectric layer 5 includes oxides.

[0058] Step S102, as follows Figure 3D As shown, a shielding oxide layer 201 is formed on the surface of the first epitaxial layer 2 on which the trench gate is formed. The thickness of the shielding oxide layer 201 is controlled by a dry etching process to make the thickness of the shielding oxide layer 201 uniform.

[0059] In this embodiment of the invention, after the dry etching of the shielding oxide layer 201 is completed, a wet cleaning process is also performed to remove the damage to the surface of the first epitaxial layer 2 caused by the dry etching of the shielding oxide layer 201.

[0060] Step S103, as follows Figure 3D As shown, a second type of body implantation is performed to form a body region 11 in the surface region of the first epitaxial layer 2, which shields the oxide layer 201 to have a uniform thickness structure, so that the depth of body implantation at each position of the first epitaxial layer 2 is uniform and the bottom surface position of the body region 11 is flat. Figure 3D In this context, body injection is indicated by the arrow line marked 202, and is also commonly referred to as body implant.

[0061] Step S104, as follows Figure 3E As shown, removing the shielding oxide layer 201 will cause a depression at the top corner of the gate trench.

[0062] In this embodiment of the invention, the shielding oxide layer 201 is removed by wet immersion.

[0063] Step S105, as follows Figure 3E As shown, a corner sidewall 204 is formed at the corner recess of the gate trench.

[0064] In this embodiment of the invention, the process for forming the top corner sidewall 204 includes: A top corner spacer 204 material layer is formed. In some embodiments, the top corner spacer 204 material layer includes an oxide layer. The thickness of the formed top corner spacer 204 material layer is 400 Angstroms. In other embodiments, the material and thickness of the top corner spacer 204 material layer can also be changed as needed to ensure that the depth of the source implant along the side of the gate trench is prevented from being too deep in the subsequent source implant.

[0065] An anisotropic etch is performed on the top corner spacer 204 material layer to leave the top corner spacer 204 material layer only at the top corner recess and form the top corner spacer 204.

[0066] Step S106, as shown in Figure 3E A first conductivity type heavily doped source implant is performed to form a source region 9 in the surface region of the body region 11, the bottom of the source region 9 is the surface of the body region 11 covered by the trench gate side for forming a channel, and the top corner spacer 204 is used to reduce the depth of the source implant along the side of the gate trench, thereby precisely controlling the distance between the bottom surface of the source region 9 and the bottom surface of the body region 11 at the side of the gate trench, i.e., the channel length, and preventing the channel length from fluctuating greatly when the channel length is shortened and source-drain punchthrough occurs. Figure 3E In some embodiments, the source implant is also indicated by the arrow line marked 203, and is also commonly indicated by source implant. Figure 3E In some embodiments, the channel length is indicated by L1. And Figure 1 Compared with the channel length corresponding to L101, L1 is not reduced, so the defect of source-drain punchthrough caused by further shortening of the channel length on the basis of the design size is eliminated, and thus the leakage caused by source-drain punchthrough is eliminated.

[0067] In the embodiments of the present application, the following steps are further included: As shown in Figure 3F An interlayer film 8 is formed.

[0068] As shown in Figure 3G A second conductivity type heavily doped ion implantation is performed to form a contact implant region 10, the contact implant region 10 and the subsequent contact hole form an ohmic contact, and the body region 11 is connected to the contact hole through the contact implant region 10. In other embodiments, the contact implant region 10 can also be formed before the interlayer film 8 is formed; or, the contact implant layer 10 is formed after the subsequent contact hole opening is formed and before the metal is filled.

[0069] As shown in Figure 3H A contact hole opening is formed through the interlayer film 8, and then a metal is filled in the contact hole opening to form a contact hole.

[0070] As shown in Figure 3HAs shown, the front metal layer 12 is formed and patterned to form the source and the gate, the source region 9 is connected to the source through the top corresponding contact hole, and the gate conductive material layer 7 is connected to the gate through the top corresponding contact hole.

[0071] In the embodiment of the present application, the trench gate device includes a trench gate MOSFET, and after the front process is completed, the trench gate device further includes: The semiconductor substrate 1 is thinned, the semiconductor substrate 1 is heavily doped with the first conductive type, and the drain region is formed from the thinned semiconductor substrate 1. The thinned semiconductor substrate 1 is subjected to a back ion implantation of the first conductive type to form the drain region.

[0072] The back metal layer is formed on the back of the drain region and is composed of the drain electrode.

[0073] In the embodiment of the present application, the trench gate device is an N-type device, the first conductive type is N-type, and the second conductive type is P-type. In other embodiments, the trench gate device can also be a P-type device, the first conductive type is P-type, and the second conductive type is N-type.

[0074] In the embodiment of the present application, the manufacturing process of the trench gate device is comprehensively set according to the need for accurately controlling the channel length, mainly the forming process of the body region 11 and the source region 9 closely related to the channel length is improved. In the embodiment of the present application, the etching of the shielding oxide layer 201 formed before the body implantation is changed from the wet etching commonly used in the prior art to the dry etching process. The thickness of the shielding oxide layer 201 is uniformly distributed by using the dry etching process. Since the ions of the body implantation will pass through the shielding oxide layer 201 into the first epitaxial layer 2, after the thickness of the shielding oxide layer 201 is uniform, the depth of the body implantation is also uniform. In this way, the flatness of the bottom surface of the body region 11 is also improved, preventing the bottom surface of the body region 11 from fluctuating greatly, which prevents the bottom surface of the body region 11 from being too shallow.

[0075] Meanwhile, the embodiment of the present application also forms a top corner side wall 204 at the top corner recess of the gate trench formed after the removal of the screen oxide layer 201 before the source implantation, and the top corner side wall 204 can increase the implantation path at the side of the gate trench, and prevent the source implantation from being too deep at the side of the gate trench due to the top corner recess, i.e. the bottom surface of the source region 9 is too deep. Since the bottom surface of the source region 9 is used to form the channel with the surface of the body region 11 at the side of the trench gate, the channel length is the distance between the bottom surface of the source region 9 and the bottom surface of the body region 11. Since the embodiment of the present application can prevent the bottom surface of the source region 9 from being too deep and the bottom surface of the body region 11 from being too shallow, the channel length can be prevented from being too short. In the condition of the designed short channel length, the further shortening of the channel length due to the process fluctuation can make the channel length exceed the target value range, and thus cause the source-drain punch-through. Therefore, the embodiment of the present application can prevent the source-drain punch-through and reduce the leakage current caused by the source-drain punch-through.

[0076] In the embodiment of the present application, in order to control the body implantation junction depth distribution, the body implantation screen oxide etching is changed to dry etching, but the plasma of the dry etching is relatively serious, and the dry etching needs to be strengthened to reduce the damage of the plasma to the material surface such as the Si surface of the first epitaxial layer 2.

[0077] Generally, the NP implant, i.e. the N+ source implantation, is prone to form recesses at the top corners of the polysilicon gate, which can cause the source implantation to be deeper in the direction along the gate trench. In the embodiment of the present application, 400A oxide is deposited as a side wall before the source implantation, and then the oxide on the Si surface of the polysilicon (poly) and the epitaxial layer is etched by dry etching anisotropically, and the oxide on the side wall is reserved. In this way, the source implantation in the direction along the trench side wall will be shallower, and the channel leakage caused by the uneven source implantation can be effectively improved.

[0078] The above has described the present application in detail through specific embodiments, but these do not constitute the limitation of the present application. Those skilled in the art can also make many modifications and improvements without departing from the principle of the present application, and these should also be considered as the protection range of the present application.

Claims

1. A method for manufacturing a trench gate device, characterized in that, The following steps are used to control the channel length to prevent source-drain punch-through when the channel length is shortened: A trench gate is formed on a first epitaxial layer doped with a first conductivity type. The trench gate includes a gate trench and a gate conductive material layer filled in the gate trench. A gate dielectric layer is spaced between the gate conductive material layer and the inner surface of the corresponding gate trench. The gate trench has an inclined morphology with a top opening larger than a bottom opening. A shielding oxide layer is formed on the surface of the first epitaxial layer on which the trench gate is formed, and the thickness of the shielding oxide layer is controlled by a dry etching process to make the thickness of the shielding oxide layer uniform. A second conductivity type of volume implantation is performed to form a volume region in the surface region of the first epitaxial layer, the shielding oxide layer has a uniform thickness structure, the depth of the volume implantation at each location of the first epitaxial layer is uniform, and the bottom surface of the volume region is flat. Removing the shielding oxide layer will cause a depression at the apex of the gate trench. A corner sidewall is formed at the corner recess of the gate trench; A source implantation of a first conductivity type is performed to form a source region in the surface region of the body region. The bottom of the source region is covered by the sidewall of the trench gate to form a channel. The top corner sidewall is used to reduce the depth of the source implantation downward along the sidewall of the gate trench, thereby precisely controlling the channel length at the sidewall of the gate trench and preventing large fluctuations in the channel length when the channel length is shortened, which could lead to source-drain punch-through.

2. The method for manufacturing the trench gate device as described in claim 1, characterized in that: The trench gate device includes an SGT device, wherein the SGT device further includes a source conductive material layer in the gate trench, the source conductive material layer is located in the bottom region of the gate trench and is spaced apart from the inner surface of the gate trench by a source dielectric layer, and an inter-gate dielectric layer is spaced between the source conductive material layer and the gate conductive material layer.

3. The method for manufacturing the trench gate device as described in claim 2, characterized in that: The top surface of the gate conductive material layer is also etched back onto the top surface of the first epitaxial layer, which is below the gate trench.

4. The method for manufacturing the trench gate device as described in claim 1, characterized in that: After the dry etching of the shielding oxide layer is completed, a wet cleaning process is also performed to remove the damage caused to the surface of the first epitaxial layer by the dry etching of the shielding oxide layer.

5. The method for manufacturing the trench gate device as described in claim 1, characterized in that: The shielding oxide layer was removed by wet immersion.

6. The method for manufacturing the trench gate device as described in claim 1, characterized in that: The process for forming the top corner sidewall includes: Form a layer of material for the top corner sidewalls; The corner sidewall material layer is anisotropically etched so that the corner sidewall material layer is located only at the corner recess and forms the corner sidewall.

7. The method for manufacturing a trench gate device as described in claim 6, characterized in that: The corner sidewall material layer includes an oxide layer.

8. The method for manufacturing a trench gate device as described in claim 7, characterized in that: The thickness of the formed top corner sidewall material layer is 400 Å.

9. The method for manufacturing a trench gate device as described in claim 7, characterized in that, It also includes the following steps: Formation of interlayer membrane; A contact hole opening is formed through the interlayer membrane, and then metal is filled into the contact hole opening to form a contact hole; A front metal layer is formed and the front metal layer is patterned to form a source and a gate. The source region is connected to the source through the corresponding contact hole at the top, and the gate conductive material layer is connected to the gate through the corresponding contact hole at the top.

10. The method for manufacturing a trench gate device as described in claim 9, characterized in that, After the interlayer film is formed, the following is also included: Ion implantation of a second conductivity type is performed to form a contact implantation region, which forms an ohmic contact with the contact hole, and the body region is connected to the contact hole through the contact implantation region.

11. The method for manufacturing a trench gate device as described in claim 1, characterized in that: The material of the gate dielectric layer includes oxides; The material of the gate conductive material layer includes polycrystalline silicon.

12. The method for manufacturing a trench gate device as described in claim 2, characterized in that: The material of the source dielectric layer includes oxides; The material of the source and gate conductive material layer includes polycrystalline silicon; The material of the inter-gate dielectric layer includes oxides.

13. The method for manufacturing a trench gate device as described in claim 1, characterized in that: The trench gate device includes a trench gate MOSFET, wherein the first epitaxial layer is formed on a semiconductor substrate; After the front-side process is completed, it also includes: The semiconductor substrate is thinned, and the semiconductor substrate is heavily doped with a first conductivity type, and the drain region is formed from the thinned semiconductor substrate; or, the drain region is formed by back-side ion implantation of the thinned semiconductor substrate with a first conductivity type. A back metal layer is formed on the back side of the drain region, and the back metal layer forms the drain electrode.

14. The method for manufacturing a trench gate device as described in claim 13, characterized in that: The semiconductor substrate is made of silicon, and the first epitaxial layer is made of silicon.

15. A method for manufacturing a trench gate device as described in any one of claims 1 to 14, characterized in that: The trench gate device is an N-type device with an N-type first conductivity type and a P-type second conductivity type; or, the trench gate device is a P-type device with a P-type first conductivity type and an N-type second conductivity type.

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