Silicon carbide CMOS device and layout drawing method thereof

Abstract

The invention provides a silicon carbide CMOS device and a layout drawing method thereof, and relates to the technical field of microelectronic device design and manufacturing. The silicon carbide CMOS device comprises a substrate, an N-type buffer layer and a P-type epitaxial layer which are connected in sequence, the N-type well regions are respectively positioned on the surface of the P-type epitaxial layer; a plurality of N-type heavily doped isolation regions respectively located in the P-type epitaxial layer; a plurality of N-type heavily-doped ohmic contact regions and a plurality of P-type heavily-doped ohmic contact regions, wherein any N-type heavily-doped ohmic contact region and any P-type heavily-doped ohmic contact region are located on the surface of the P-type epitaxial layer; a gate oxide layer and a polysilicon gate layer are sequentially arranged above the P-type epitaxial layer; the gate oxide layer is used as a gate dielectric and a surface passivation layer; and the polysilicon gate layer is used as a gate electrode and an electrostatic shielding layer. According to the invention, the metal-substrate parasitic capacitance is effectively reduced, the current gain of the NPN-type and PNP-type transistors is improved, the latch-up effect caused by the conduction of the parasitic transistor is inhibited, and no extra new process step needs to be introduced.

Description

Technical Field

[0001] This application relates to the field of microelectronic device design and manufacturing technology, and in particular to a silicon carbide CMOS device and its layout drawing method. Background Technology

[0002] Silicon carbide (SiC) has become a core material for fabricating high-temperature, high-frequency, and high-power devices due to its excellent properties such as wide bandgap (3.26 eV), high critical electric field strength (2.5 MV / cm), and high thermal conductivity (4.9 W / m·K). With the increasing integration of power electronic systems, the performance optimization of SiC CMOS devices, as the fundamental unit for realizing SiC power integrated circuits, has become a research hotspot.

[0003] Existing SiC CMOS devices are mostly fabricated using mature SiC power device processes, which can reduce process complexity, but the following key issues exist:

[0004] (1) Parasitic capacitance affects frequency characteristics: SiC power device technology typically designs only a single metal electrode layer as the trace, and a large parasitic capacitance is directly formed between the metal trace and the substrate. In high-frequency operating scenarios, this parasitic capacitance will significantly increase signal transmission delay, limit the frequency response performance of the device, and make it difficult to meet the design requirements of high-frequency integrated circuits.

[0005] (2) Low current gain of BJT devices: The current gain of silicon carbide BJT devices is significantly affected by surface carrier recombination, and passivation with surface oxide layer (such as SiO2) is required to reduce recombination centers. However, in traditional layout design, the oxide layer in the BJT region is easily damaged in subsequent processes (such as electrode etching), resulting in poor passivation effect, increased carrier surface recombination rate, and decreased device current gain.

[0006] (3) Device isolation and latch-up problem: In SiC CMOS devices, the difference in substrate potential between PMOS and NMOS can easily lead to the conduction of parasitic transistors, causing latch-up. Traditional isolation methods (such as simple PN junction isolation) are difficult to achieve effective isolation between devices, resulting in large leakage current and obvious parasitic effects, which affect the stability of circuit operation.

[0007] Furthermore, traditional silicon-based CMOS layout design methods cannot be directly transferred to SiC devices due to differences in material properties (such as the high doping activation energy and anisotropic etching characteristics of SiC), which further exacerbates the above problems. Summary of the Invention

[0008] In view of the above problems, this application provides a silicon carbide CMOS device and a method for layout drawing the same, so as to solve the above problems.

[0009] According to a first aspect of this application, a silicon carbide CMOS device is provided, comprising: a substrate, an N-type buffer layer, and a P-type epitaxial layer connected in sequence; a plurality of N-type well regions located on the surface of the P-type epitaxial layer; a plurality of heavily doped N-type isolation regions located in the P-type epitaxial layer; a plurality of heavily doped N-type ohmic contact regions and a plurality of heavily doped P-type ohmic contact regions, wherein each of the heavily doped N-type ohmic contact regions and each of the heavily doped P-type ohmic contact regions is located on the surface of the P-type epitaxial layer; a gate oxide layer and a polysilicon gate layer are sequentially disposed above the P-type epitaxial layer; the gate oxide layer is used as a gate dielectric and a surface passivation layer; and the polysilicon gate layer is used as a gate electrode and an electrostatic shielding layer.

[0010] According to an embodiment of this application, an N-type heavily doped isolation region is deeply implanted in a P-type epitaxial layer, the implantation depth of the N-type heavily doped isolation region exceeds the thickness of the P-type epitaxial layer, and the N-type heavily doped isolation region forms an electrical contact with the N-type buffer layer.

[0011] According to embodiments of this application, the silicon carbide CMOS device further includes a field oxide layer and an electrode layer sequentially disposed above the polysilicon gate layer, an active region contact hole penetrating the field oxide layer and the gate oxide layer, and a gate contact hole penetrating the field oxide layer; the bottom of the active region contact hole contacts one of an N-type heavily doped ohmic contact region or a P-type heavily doped ohmic contact region; and the bottom of the gate contact hole contacts the polysilicon gate layer.

[0012] According to an embodiment of this application, an N-type heavily doped ohmic contact region is shallowly implanted in a P-type epitaxial layer, and the distance between the bottom of the N-type heavily doped ohmic contact region and the upper surface of the P-type epitaxial layer is less than the thickness of the P-type epitaxial layer.

[0013] According to an embodiment of this application, an N-type heavily doped ohmic contact region, a P-type epitaxial layer, and an N-type buffer layer constitute a vertical NPN transistor. The N-type heavily doped ohmic contact region is the emitter of the NPN transistor, the P-type epitaxial layer is the base of the NPN transistor, and the N-type heavily doped isolation region adjacent to the N-type buffer layer is the collector of the NPN transistor.

[0014] According to an embodiment of this application, any P-type heavily doped ohmic contact region, N-type well region, and P-type heavily doped ohmic contact region located in the P-type epitaxial layer constitute a lateral PNP transistor. Any P-type heavily doped ohmic contact region located in the P-type epitaxial layer is the collector of the PNP transistor, the P-type heavily doped ohmic contact region located in the N-type well region is the emitter of the PNP transistor, and the N-type heavily doped ohmic contact region located in the N-type well region is the base of the PNP transistor. A polysilicon gate layer covers the surfaces of the NPN transistor and the PNP transistor.

[0015] According to embodiments of this application, two adjacent heavily doped N-type ohmic contact regions on a P-type epitaxial layer, a field oxide layer above them, and a gate oxide layer above them constitute an NMOS device; two adjacent heavily doped P-type ohmic contact regions on an N-type well region, a field oxide layer above them, and a gate oxide layer above them constitute a PMOS device; the NMOS device is surrounded by a ring-shaped heavily doped N-type isolation region, and a gate oxide layer covers the surface of the NMOS device; the PMOS device is surrounded by a ring-shaped P-type epitaxial layer, and a gate oxide layer covers the surface of the NMOS device.

[0016] According to embodiments of this application, a portion of the polysilicon gate layer is patterned into a gate electrode, and a portion covers the upper surface of the NMOS and PMOS devices.

[0017] According to an embodiment of this application, a plurality of first holes are formed in the polysilicon gate layer for active region contact holes to pass through, allowing the collector, emitter, and base electrical signals to be led out. The size of the first holes is larger than the size of the active region contact holes. The sidewalls and surfaces of the polysilicon gate layer are in contact with the field oxide layer and are connected to the electrodes formed by the gate contact holes and the electrode layer. A plurality of second holes are formed in the polysilicon gate layer for active region contact holes disposed in the source-drain contact region to pass through. The size of the second holes is larger than the size of the active region contact holes. The sidewalls and surfaces of the polysilicon gate layer are in contact with the field oxide layer and are connected to the electrodes formed by the gate contact holes and the electrode layer.

[0018] The second aspect of this application provides a layout drawing method for a silicon carbide CMOS device, comprising: selecting a substrate and epitaxial layer: based on the substrate, an N-type buffer layer is epitaxially grown, and a P-type epitaxial layer is epitaxially grown on the N-type buffer layer, wherein the substrate material is N+ SiC; drawing N-type heavily doped isolation regions and N-type well regions: using a deep implantation process, an N-type heavily doped isolation region is drawn in the P-type epitaxial layer, wherein the N-type heavily doped isolation region divides the P-type epitaxial layer into multiple independent islands; drawing N-type well regions on the surfaces of the multiple islands as required; drawing ohmic contact regions: implanting into the N-type heavily doped ohmic contact regions... Implantation in the heavily doped p-type ohmic contact region Drawing the dielectric layer and gate structure: A gate oxide layer is grown above the P-type epitaxial layer and passivated by oxynitride annealing; a polysilicon gate layer is deposited above the gate oxide layer, covering all device surfaces during patterning, and openings are reserved at the positions of active region contact holes in the polysilicon gate layer; a field oxide layer is grown to cover the sidewalls and surface of the polysilicon gate layer; drawing the contact holes and electrodes: multiple active region contact holes are set in the field oxide layer and the gate oxide layer, and multiple gate contact holes are set in the gate oxide layer; an electrode layer is deposited above the field oxide layer, and the polysilicon gate layer is connected to a fixed ground potential through the gate contact holes.

[0019] The silicon carbide CMOS device and its layout design method provided in this application have at least the following technical advantages:

[0020] 1. By connecting the polysilicon gate layer to a fixed potential, an electrostatic shielding layer is formed between the metal trace (electrode layer) and the substrate, which effectively reduces the metal-substrate parasitic capacitance, significantly improves the high-frequency response performance of the device, and broadens the application frequency range of silicon carbide CMOS circuits.

[0021] 2. By fully covering the surface of the BJT (Bipolar Junction Transistor) device with a gate oxide layer and using a patterned design of the polysilicon gate layer (with openings only at the electrode leads), the gate oxide layer, which has been passivated by NO, is ensured not to be damaged during the process. This significantly reduces surface recombination of charge carriers, improves the current gain of NPN and PNP transistors, and enhances the DC characteristics of the device.

[0022] 3. By deeply implanting heavily doped N-type isolation regions, the P-type epitaxial layer is divided into independent "islands," equivalent to a double-well CMOS process, achieving physical and electrical isolation between devices. This structure can reduce leakage current between devices by 1 to 2 orders of magnitude, effectively suppress the latch-up effect caused by parasitic transistor conduction, and improve the stability of circuit operation.

[0023] 4. Silicon carbide CMOS devices are based entirely on existing SiC power device processes (such as ion implantation, oxidation, polysilicon deposition, etc.), without the need to introduce additional new process steps, which reduces the manufacturing cost and facilitates industrial application. Attached Figure Description

[0024] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0025] Figure 1 A schematic cross-sectional view of an NMOS device structure in a silicon carbide CMOS device according to an embodiment of this application is shown.

[0026] Figure 2 A schematic cross-sectional view of a PMOS device structure in a silicon carbide CMOS device according to an embodiment of this application is shown.

[0027] Figure 3 A schematic cross-sectional view of an NPN transistor structure in a silicon carbide CMOS device according to an embodiment of this application is shown.

[0028] Figure 4 A schematic cross-sectional view of a PNP transistor structure in a silicon carbide CMOS device according to an embodiment of this application is shown.

[0029] Figure 5 A flowchart illustrating a layout drawing method for a silicon carbide CMOS device according to an embodiment of this application is shown schematically.

[0030] Figure reference numerals: 1-N-type buffer layer; 2-P-type epitaxial layer; 3-N-type well region; 4-N-type heavily doped isolation region; 5-N-type heavily doped ohmic contact region; 6-P-type heavily doped ohmic contact region; 7-gate oxide layer; 8-polysilicon gate layer; 9-field oxide layer; 10-electrode layer; 11-active region contact hole; 12-gate contact hole. Detailed Implementation

[0031] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0033] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0034] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0035] Figure 1 A schematic cross-sectional view of an NMOS device structure in a silicon carbide CMOS device according to an embodiment of this application is shown. Figure 2 A schematic cross-sectional view of a PMOS device structure in a silicon carbide CMOS device according to an embodiment of this application is shown.

[0036] like Figure 1 , Figure 2As shown, one embodiment of this application discloses a silicon carbide CMOS device, comprising: a substrate, an N-type buffer layer 1, and a P-type epitaxial layer 2 connected in sequence; a plurality of N-type well regions 3 located on the surface of the P-type epitaxial layer 2; a plurality of heavily doped N-type isolation regions 4 located in the P-type epitaxial layer 2; a plurality of heavily doped N-type ohmic contact regions 5 and a plurality of heavily doped P-type ohmic contact regions 6, wherein any one of the heavily doped N-type ohmic contact regions 5 and any one of the heavily doped P-type ohmic contact regions 6 is located on the surface of the P-type epitaxial layer 2; a gate oxide layer 7 and a polysilicon gate layer 8 are sequentially disposed above the P-type epitaxial layer 2; the gate oxide layer 7 is used as a gate dielectric and a surface passivation layer; the polysilicon gate layer 8 is used as a gate electrode and an electrostatic shielding layer.

[0037] In the embodiments of this disclosure, by connecting the polysilicon layer to a fixed potential, an electrostatic shielding layer is formed between the metal trace (electrode layer 10) and the substrate, effectively reducing the metal-substrate parasitic capacitance. The gate oxide layer 7 completely covers the surface of the BJT (bipolar junction transistor) device, and through the patterned design of the polysilicon gate layer 8 (with openings only at the electrode leads), it is ensured that the NO passivation (oxygen nitride passivation) gate oxide layer 7 is not damaged during the process, significantly reducing the surface recombination of charge carriers. By deeply injecting N+ isolation regions to divide the P epitaxial layer into independent "islands," equivalent to a dual-well CMOS process, physical and electrical isolation between devices is achieved. This structure effectively suppresses the latch-up effect caused by parasitic transistor conduction and improves the stability of circuit operation.

[0038] In this process, after growing the gate oxide layer 7 and performing NO passivation, the BJT device surface achieves a near-ideal passivation effect, with extremely low interface state density and minimal carrier surface recombination rate. Immediately after forming the high-quality gate oxide layer 7, a polysilicon gate layer 8 is deposited on top. The polysilicon gate layer 8 has openings only at the electrode lead-out locations, meaning that during polysilicon etching, only the tiny areas where metal electrodes need to be led out are etched through the polysilicon and gate oxide layer 7. The gate oxide layer 7 over most of the BJT active region remains tightly covered and protected by the polysilicon. Subsequent process steps (such as dielectric deposition, contact hole etching, and metallization) first fall on the polysilicon protective cap, without directly damaging the underlying fragile, high-quality gate oxide layer 7. Experiments show that the polysilicon gate layer 8 structure can reduce parasitic capacitance by 30%–50%, significantly improve the high-frequency response performance of the device, and broaden the application frequency range of silicon carbide CMOS circuits.

[0039] like Figure 1 As shown, the N-type heavily doped isolation region 4 is deeply implanted in the P-type epitaxial layer 2. The implantation depth of the N-type heavily doped isolation region 4 exceeds the thickness of the P-type epitaxial layer 2, and the N-type heavily doped isolation region 4 forms an electrical contact with the N-type buffer layer 1.

[0040] The P-type epitaxial layer 2 is divided into multiple independent "islands" by the N-type heavily doped isolation region 4. Each island can be individually implanted with an N-well and fabricated into a device, achieving the isolation effect of an equivalent double-well CMOS process.

[0041] It is understood that because the implantation depth of the heavily doped N-type isolation region 4 exceeds the thickness of the P-type epitaxial layer 2 and forms an electrical contact with the underlying N-type buffer layer 1, the P-type body region of each "island" is completely enclosed by an "N-type enclosure" consisting of an N+ isolation region and an N-type buffer layer. At any time, as long as the N-type enclosure (heavily doped N-type isolation region 4 and N-type buffer layer 1) is connected to the highest power supply potential and the P-type island is connected to the lowest potential, the PN junction enclosing the P-type island is always in a reverse bias state. The resistance of the reverse PN junction is extremely high, thus achieving near-perfect longitudinal and lateral electrical isolation.

[0042] It is understood that the latch-up effect is caused by the PNPN structure formed by parasitic NPN and PNP transistors. The deeply N-type heavily doped isolation region 4 acts like a "wall," physically cutting off the path for the formation of parasitic SCRs (Silicon Controlled Rectifiers) between adjacent devices. While an SCR is itself a powerful controllable power switching device, in CMOS integrated circuits, it appears in a harmful parasitic form, and its uncontrolled conduction (i.e., latch-up) is one of the main causes of chip failure. The N-type heavily doped isolation region 4 prevents the collector current of the parasitic PNP transistor (which is also the base current of the parasitic NPN transistor) from flowing laterally between devices, thereby disrupting the positive feedback condition for latch-up and greatly improving the circuit's anti-latch-up capability and reliability.

[0043] like Figure 1 As shown, the silicon carbide CMOS device also includes a field oxide layer 9 and an electrode layer 10 sequentially disposed above the polysilicon gate layer 8, an active region contact hole 11 penetrating the field oxide layer 9 and the gate oxide layer 7, and a gate contact hole 12 penetrating the field oxide layer 9; the bottom of the active region contact hole 11 contacts one of the N-type heavily doped ohmic contact region 5 or the P-type heavily doped ohmic contact region 6; the bottom of the gate contact hole 12 contacts the polysilicon gate layer 8.

[0044] The field oxide layer 9 is used to achieve electrical isolation. On a chip, there are large areas between active devices (transistors) that do not need to be conductive. If these areas are bare silicon, the metal traces above may accidentally induce conductive channels on the silicon surface, causing short circuits or leakage between adjacent devices. As a thick insulator, the field oxide layer 9 fundamentally prevents the formation of such parasitic channels, ensuring that different devices are electrically independent of each other and that no unexpected current paths are generated.

[0045] The active region contact hole 11 is a hole etched on the field oxide layer 9 and the gate oxide layer 7, exposing the underlying N-type heavily doped ohmic contact region 5 or P-type heavily doped ohmic contact region 6, so that the metal electrode layer 10 can be electrically connected to the source and drain of the transistor, allowing current to flow in and out.

[0046] The gate contact hole 12 is a hole etched into the field oxide layer 9, exposing the underlying polysilicon gate layer 8, and transmitting the external control voltage (logic "0" and "1" for digital circuits, and input signal for analog circuits) to the transistor gate. Through the direct connection between the metal and the polysilicon, it significantly reduces the series resistance of the gate. Lower gate resistance means faster charging and discharging of the gate capacitor, thereby directly improving the transistor's switching speed and the circuit's maximum operating frequency.

[0047] The electrode layer 10 connects the source, drain and gate of multiple transistors according to the circuit design diagram through the active region contact hole 11 and the gate contact hole 12, so as to connect the power supply voltage and ground line to the corresponding transistors.

[0048] Figure 3 A schematic cross-sectional view of an NPN transistor structure in a silicon carbide CMOS device according to an embodiment of this application is shown. Figure 4 A schematic cross-sectional view of a PNP transistor structure in a silicon carbide CMOS device according to an embodiment of this application is shown.

[0049] like Figure 3 , Figure 4 As shown, an N-type heavily doped ohmic contact region 5 is shallowly implanted in a P-type epitaxial layer 2. The distance between the bottom of the N-type heavily doped ohmic contact region 5 and the upper surface of the P-type epitaxial layer 2 is less than the thickness of the P-type epitaxial layer 2. The N-type heavily doped ohmic contact region 5, the P-type epitaxial layer 2, and the N-type buffer layer 1 constitute a vertical NPN transistor. The N-type heavily doped ohmic contact region 5 is the emitter of the NPN transistor, the P-type epitaxial layer 2 is the base of the NPN transistor, and the N-type heavily doped isolation region 4 adjacent to the N-type buffer layer 1 is the collector of the NPN transistor. Any region located in the P-type buffer layer 1... The P-type heavily doped ohmic contact region 6, the N-type well region 3, and the P-type heavily doped ohmic contact region 6 located in the N-type well region 3 constitute a lateral PNP transistor. Any P-type heavily doped ohmic contact region 6 located in the P-type epitaxial layer 2 is the collector of the PNP transistor, the P-type heavily doped ohmic contact region 6 located in the N-type well region 3 is the emitter of the PNP transistor, and the N-type heavily doped ohmic contact region 5 located in the N-type well region 3 is the base of the PNP transistor. The polysilicon gate layer 8 covers the surfaces of the NPN transistor and the PNP transistor.

[0050] Among them, the N-type heavily doped ohmic contact region 5 is drawn in the P-type epitaxial layer 2 using a shallow implantation method, and its implantation concentration is greater than 5e18cm. -3 The implantation depth is 10nm to 400nm smaller than that of the P-type epitaxial layer 2. Specifically, the distance between the bottom (i.e., the location of the PN junction) of the heavily doped N-type ohmic contact region 5 (emitter) formed by ion implantation and the upper surface of the P-type epitaxial layer 2 is 10nm to 400nm smaller than the total thickness of the entire P-type epitaxial layer 2. Through precise ion implantation, the emitter junction depth of the NPN transistor is controlled within an extremely shallow and precise range. This forms a highly efficient heavily doped emitter and, in conjunction with the thickness of the P-type epitaxial layer 2, defines and compresses the base region width to the nanoscale. Ultimately, by reducing the transit time and recombination probability of charge carriers in the base region, the current gain of the parasitic NPN transistor is significantly improved.

[0051] In this design, the P-type heavily doped ohmic contact region 6 within the N-type well region 3 is located 10 nm to 400 nm from the boundary between the N-type well region 3 and the P-type epitaxial layer 2. This distance defines the effective base region width of the PNP transistor. This distance represents the path length that holes must traverse to diffuse laterally from the emitter to the collector. By controlling the base region width at the nanoscale, the transport path of charge carriers (holes) is significantly shortened, thereby significantly improving the current gain of the PNP transistor. This PNP transistor, combined with a similarly optimized vertical NPN transistor, constitutes a complete complementary bipolar technology platform on SiC material.

[0052] It is important to understand that gate oxide layer 7 completely covers the surface of the NPN transistor, while polysilicon gate layer 8 covers gate oxide layer 7 and only has openings at the electrode leads; gate oxide layer 7 and polysilicon gate layer 8 cover the surface of the PNP transistor, with openings only at the electrode leads. The globally covered polysilicon gate layer 8 provides crucial shielding and protection for all active devices, reducing parasitic capacitance and noise crosstalk caused by metal interconnects.

[0053] like Figure 1 , Figure 2 As shown, two adjacent heavily doped N-type ohmic contact regions 5 on the P-type epitaxial layer 2, the field oxide layer 9 above them, and the gate oxide layer 7 above them constitute an NMOS device; two adjacent heavily doped P-type ohmic contact regions 6 on the N-type well region 3, the field oxide layer 9 above them, and the gate oxide layer 7 above them constitute a PMOS device; the NMOS device is surrounded by a ring-shaped heavily doped N-type isolation region 4, and the gate oxide layer 7 covers the surface of the NMOS device; the PMOS device is surrounded by a ring-shaped P-type epitaxial layer 2, and the gate oxide layer 7 covers the surface of the NMOS device.

[0054] In this configuration, the NMOS device is surrounded by a ring-shaped heavily doped N-type isolation region 4, which forms a PN junction with the P-type epitaxial layer 2. When the heavily doped N-type isolation region 4 is connected to a high potential (such as VDD) and the P-type epitaxial layer 2 is connected to a low potential (such as GND), this PN junction is reverse biased, forming a high-resistance isolation ring that isolates the NMOS device. Similarly, the PMOS device is surrounded by a ring-shaped P-type epitaxial layer 2, and the PMOS device itself is fabricated in an N-type well region 3. This N-type well region 3 is also surrounded by a common P-type epitaxial layer 2, and a reverse-biased PN junction is formed between the N-type well region 3 and the P-type epitaxial layer, thus isolating the PMOS device. This layout physically blocks the PNPN latch-up path formed by the N+ source region of the NMOS device (the emitter of the parasitic NPN transistor), the P epitaxial layer (the base of the parasitic NPN transistor), the N well (the base of the parasitic PNP transistor), and the P+ source region of the PMOS device (the emitter of the parasitic PNP transistor). Even with a trigger current, a positive feedback loop cannot be formed.

[0055] Meanwhile, the full coverage of gate oxide layer 7 provides excellent surface passivation for the device, stabilizes its electrical parameters, and creates conditions for the subsequent introduction of a multifunctional polysilicon layer (electrostatic shielding), ultimately building a robust, reliable, and high-performance silicon carbide CMOS process platform.

[0056] Based on embodiments of this application, a portion of the polysilicon gate layer 8 is patterned as a gate electrode, and a portion covers the upper surface of the NMOS and PMOS devices.

[0057] The polysilicon layer covering the MOS device is connected to a fixed potential (such as GND or VDD). It forms an electrostatic shield between the metal traces above and the active region and gate below. This shield effectively cuts off the electric field lines between the metal traces and the underlying circuitry, thereby minimizing parasitic capacitance.

[0058] By reusing the polysilicon gate layer 8, the shielding function and the gate function are completed simultaneously in the same polysilicon gate layer 8 deposition and patterning step, so that it can serve as both the gate electrode of the MOSFET and the electrostatic shielding layer covering the device.

[0059] Based on the embodiments of this application, a plurality of first holes are formed in the polysilicon gate layer 8 for active region contact holes 11 to pass through, through which collector, emitter and base electrical signals are led out. The size of the first holes is larger than the size of the active region contact holes 11. The sidewalls and surfaces of the polysilicon gate layer 8 are in contact with the field oxide layer 9 and are connected to the electrodes formed by the electrode layer 10 through the gate contact holes 12. A plurality of second holes are formed in the polysilicon gate layer 8 for active region contact holes 11 disposed in the source and drain contact regions to pass through. The size of the second holes is larger than the size of the active region contact holes 11. The sidewalls and surfaces of the polysilicon gate layer 8 are in contact with the field oxide layer 9 and are connected to the electrodes formed by the electrode layer 10 through the gate contact holes 12.

[0060] The first and second holes are larger than the active region contact hole 11. This means that a larger opening is first etched into the polysilicon gate layer 8, and then a precisely sized small contact hole leading to the semiconductor active region is etched at the bottom of this large opening. During the etching of the small contact hole, the plasma and chemicals in the etching process (such as reactive ion etching) only attack a small portion of the gate oxide layer 7 exposed at the bottom of the first or second hole, while the vast majority of the gate oxide layer 7 remains tightly covered by the overlying polysilicon layer. This maximizes the protection of the gate oxide layer 7 / SiC interface, which has undergone optimization treatments such as NO passivation, preventing physical or chemical damage in subsequent processes and significantly reducing carrier surface recombination. Test results show that the current gain of NPN and PNP transistors can be increased by 20% to 40%, respectively, improving the DC characteristics of the device.

[0061] Figure 5 This schematically illustrates a flowchart of a layout drawing method for a silicon carbide CMOS device according to an embodiment of this application. The silicon carbide CMOS device drawn by this method steps is shown below. Figures 1-4 As shown.

[0062] like Figure 5 As shown, this application provides a layout drawing method for a silicon carbide CMOS device, including:

[0063] Step 501, Selecting the substrate and epitaxial layer: Based on the substrate, an N-type buffer layer 1 is epitaxially grown, and a P-type epitaxial layer 2 is epitaxially grown on the N-type buffer layer 1. The substrate material is N+ SiC.

[0064] Step 502, draw N-type heavily doped isolation region 4 and N-type well region 3: Draw N-type heavily doped isolation region 4 in P-type epitaxial layer 2 using deep implantation process. N-type heavily doped isolation region 4 divides P-type epitaxial layer 2 into multiple independent islands; draw N-type well region 3 on the surface of multiple islands as required.

[0065] Step 503, Draw the ohmic contact region: Implant N into the heavily doped N-type ohmic contact region 5 +Al was implanted in the p-type heavily doped ohmic contact region 6. + ;

[0066] Step 504, drawing the dielectric layer and gate structure: a gate oxide layer 7 is grown above the P-type epitaxial layer 2 and passivated by oxynitride annealing; a polysilicon gate layer 8 is deposited above the gate oxide layer 7, and the polysilicon gate layer 8 covers all device surfaces when patterned, and an opening is reserved at the position of the active region contact hole 11 in the polysilicon gate layer 8; a field oxide layer 9 is grown to cover the sidewalls and surface of the polysilicon gate layer 8;

[0067] Step 505, draw contact holes and electrodes: multiple active region contact holes 11 are set in the field oxide layer 9 and the gate oxide layer 7, and multiple gate contact holes 12 are set in the gate oxide layer 7; an electrode layer 10 is deposited above the field oxide layer 9, and the polysilicon gate layer 8 is connected to a fixed ground potential through the gate contact holes 12.

[0068] The entire process is based on existing mature SiC power device technologies (such as epitaxy, deep implantation, NO annealing, and polysilicon deposition) without introducing any additional, expensive proprietary process steps. All performance improvements (isolation, shielding, and gain enhancement) are achieved through ingenious design and hierarchical reuse, without the need for additional new process steps, thus reducing fabrication costs and facilitating industrial applications.

[0069] According to one embodiment of this application, the N-type buffer layer 1 has a thickness of 0.5 μm, the P-type epitaxial layer 2 has a thickness of 1 μm, and the depth of the N-type heavily doped isolation region 4 is 1.5 μm; the implanted ions in the N-type well region 3 are N... + The depth is 0.8 μm; the implanted ions in N-type heavily doped ohmic contact region 5 are N + The energy is 0.3 μm, and the implanted ions in the P-type heavily doped ohmic contact region 6 are Al. + The depth is 0.6 μm; the thickness of the gate oxide layer 7 is 20 nm to 80 nm, the thickness of the polysilicon gate layer 8 is 100 nm to 1.5 μm, the thickness of the field oxide layer 9 is 500 nm to 2 μm, and the thickness of the electrode layer 10 is 2 μm.

[0070] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

[0071] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this application is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this application, and all such substitutions and modifications should fall within the scope of this application.

Claims

1. A silicon carbide CMOS device, characterized in that, include: A substrate, an N-type buffer layer (1), and a P-type epitaxial layer (2) are connected in sequence. Multiple N-type well regions (3) are located on the surface of the P-type epitaxial layer (2); Multiple N-type heavily doped isolation regions (4) are located in the P-type epitaxial layer (2); Multiple N-type heavily doped ohmic contact regions (5) and multiple P-type heavily doped ohmic contact regions (6), wherein any N-type heavily doped ohmic contact region (5) and any P-type heavily doped ohmic contact region (6) are located on the surface of the P-type epitaxial layer (2); A gate oxide layer (7) and a polysilicon gate layer (8) are sequentially disposed above the P-type epitaxial layer (2). The gate oxide layer (7) is used as a gate dielectric and a surface passivation layer; The polysilicon gate layer (8) is used as a gate electrode and an electrostatic shielding layer.

2. The silicon carbide CMOS device according to claim 1, characterized in that, The N-type heavily doped isolation region (4) is deeply implanted into the P-type epitaxial layer (2), and the implantation depth of the N-type heavily doped isolation region (4) exceeds the thickness of the P-type epitaxial layer (2). The N-type heavily doped isolation region (4) forms an electrical contact with the N-type buffer layer (1).

3. The silicon carbide CMOS device according to claim 1, characterized in that, The silicon carbide CMOS device further includes a field oxide layer (9) and an electrode layer (10) disposed sequentially above the polysilicon gate layer (8), an active region contact hole (11) penetrating the field oxide layer (9) and the gate oxide layer (7), and a gate contact hole (12) penetrating the field oxide layer (9). The bottom of the active region contact hole (11) contacts one of the N-type heavily doped ohmic contact region (5) or the P-type heavily doped ohmic contact region (6); The bottom of the gate contact hole (12) is in contact with the polysilicon gate layer (8).

4. The silicon carbide CMOS device according to claim 1, characterized in that, The N-type heavily doped ohmic contact region (5) is shallowly implanted into the P-type epitaxial layer (2), and the distance between the bottom of the N-type heavily doped ohmic contact region (5) and the upper surface of the P-type epitaxial layer (2) is less than the thickness of the P-type epitaxial layer (2).

5. The silicon carbide CMOS device according to claim 4, characterized in that, The N-type heavily doped ohmic contact region (5), the P-type epitaxial layer (2), and the N-type buffer layer (1) constitute a vertical NPN transistor. The N-type heavily doped ohmic contact region (5) is the emitter of the NPN transistor, the P-type epitaxial layer (2) is the base of the NPN transistor, and the N-type heavily doped isolation region (4) adjacent to the N-type buffer layer (1) is the collector of the NPN transistor.

6. The silicon carbide CMOS device according to claim 5, characterized in that, Any of the P-type heavily doped ohmic contact regions (6) located in the P-type epitaxial layer (2), the N-type well region (3), and the P-type heavily doped ohmic contact regions (6) located in the N-type well region (3) constitute a lateral PNP transistor. Any of the P-type heavily doped ohmic contact regions (6) located in the P-type epitaxial layer (2) is the collector of the PNP transistor, the P-type heavily doped ohmic contact regions (6) located in the N-type well region (3) is the emitter of the PNP transistor, and the N-type heavily doped ohmic contact regions (5) located in the N-type well region (3) are the base of the PNP transistor. The polysilicon gate layer (8) covers the surfaces of the NPN transistor and the PNP transistor.

7. The silicon carbide CMOS device according to claim 3, characterized in that, Two adjacent heavily doped N-type ohmic contact regions (5) located on the P-type epitaxial layer (2), the field oxide layer (9) above them and the gate oxide layer (7) above them constitute an NMOS device; Two adjacent P-type heavily doped ohmic contact regions (6) located on the N-type well region (3), together with the field oxide layer (9) above them and the gate oxide layer (7) above them, constitute a PMOS device. The NMOS device is surrounded by the annular N-type heavily doped isolation region (4), and the gate oxide layer (7) covers the surface of the NMOS device; The PMOS device is surrounded by the annular P-type epitaxial layer (2), and the gate oxide layer (7) covers the surface of the NMOS device.

8. The silicon carbide CMOS device according to claim 7, characterized in that, A portion of the polysilicon gate layer (8) is patterned into a gate electrode, and a portion covers the upper surfaces of the NMOS device and the PMOS device.

9. The silicon carbide CMOS device according to claim 8, characterized in that, The polysilicon gate layer (8) has a plurality of first holes through which the active region contact holes (11) for drawing out the collector, emitter and base electrical signals are passed. The size of the first holes is larger than the size of the active region contact holes (11). The sidewalls and surfaces of the polysilicon gate layer (8) are in contact with the field oxide layer (9) and are connected to the electrodes formed by the electrode layer (10) through the gate contact holes (12). The polysilicon gate layer (8) has multiple second holes through which the active region contact holes (11) located in the source-drain contact area pass. The size of the second holes is larger than the size of the active region contact holes (11). The sidewalls and surfaces of the polysilicon gate layer (8) are in contact with the field oxide layer (9) and are connected to the electrodes formed by the gate contact holes (12) and the electrode layer (10).

10. A layout design method for a silicon carbide CMOS device as described in any one of claims 1-9, characterized in that, include: Selecting the substrate and epitaxial layer: Based on the substrate, an N-type buffer layer (1) is epitaxially grown, and a P-type epitaxial layer (2) is epitaxially grown on the N-type buffer layer (1). The substrate is made of N+ SiC. Draw N-type heavily doped isolation region (4) and N-type well region (3): Draw N-type heavily doped isolation region (4) in the P-type epitaxial layer (2) using deep implantation process. The N-type heavily doped isolation region (4) divides the P-type epitaxial layer (2) into multiple independent islands. Draw N-type well region (3) on the surface of multiple islands as required. Drawing the ohmic contact region: implantation in the N-type heavily doped ohmic contact region (5) Implantation in the heavily doped p-type ohmic contact region (6) ; Drawing the dielectric layer and gate structure: A gate oxide layer (7) is grown above the P-type epitaxial layer (2) and passivated by oxynitride annealing; a polysilicon gate layer (8) is deposited above the gate oxide layer (7), and the polysilicon gate layer (8) covers all device surfaces when patterned, and an opening is reserved at the position of the active region contact hole (11) in the polysilicon gate layer (8); a field oxide layer (9) is grown to cover the sidewalls and surface of the polysilicon gate layer (8); Drawing contact holes and electrodes: Multiple active region contact holes (11) are provided in the field oxide layer (9) and the gate oxide layer (7), and multiple gate contact holes (12) are provided in the gate oxide layer (7); an electrode layer (10) is deposited above the field oxide layer (9), and the polysilicon gate layer (8) is connected to a fixed ground potential through the gate contact holes (12).

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