Package structure

Abstract

The invention provides a packaging structure. The package structure includes a substrate, a first electronic component, a second electronic component, an encapsulant, and a third electronic component. The first electronic component and the second electronic component are disposed over the substrate. The encapsulant encapsulates the first electronic component and the second electronic component. The third electronic component is exposed by the encapsulant. A wafer node of the third electronic component is smaller than a wafer node of the first electronic component.

Description

Technical Field

[0001] This disclosure generally relates to a packaging structure. Background Technology

[0002] Typically, in high-density semiconductor packaging, multiple dies or modules can be arranged side-by-side or stacked vertically within the package to form a system-in-package (SiP). However, electromagnetic interference occurs between the dies or modules within the package, and external electromagnetic signals also interfere with their operation, potentially leading to damage to the dies or modules and failure of the package containing them. Therefore, improved package structures with shielding features are needed to provide more effective electromagnetic shielding.

[0003] However, when encapsulating multiple modules individually, it may be necessary to form shielding structures separately for each module. Alternatively, shielding material may be formed on selected areas, each corresponding to one of the modules in which the keep-out zone (KOZ) is omitted. This may result in problems with incomplete shielding structure formation or even low yield. Summary of the Invention

[0004] In one or more arrangements, a package structure includes a substrate, a first electronic component, a second electronic component, an encapsulant, and a third electronic component. The first and second electronic components are disposed above the substrate. The encapsulant encapsulates the first and second electronic components. The third electronic component is exposed by the encapsulant. The wafer node of the third electronic component is smaller than that of the first electronic component.

[0005] In one or more arrangements, a package structure includes a substrate, an encapsulation, an electronic component, a connection element, and a dielectric layer. The substrate includes a ground element on its upper surface. The encapsulation is disposed on the upper surface of the substrate and exposes the ground element. The electronic component is disposed on the upper surface of the substrate exposed by the encapsulation. The ground element is positioned between the encapsulation and the electronic component. The connection element is disposed in a gap between the electronic component and the substrate and configured to electrically connect the electronic component to the substrate. The dielectric layer encapsulates the connection element and is spaced apart from the ground element. The gap is not completely filled by the dielectric layer.

[0006] In one or more arrangements, a packaging structure includes a substrate, a plurality of first electronic components, a first encapsulator, a plurality of second electronic components, and a first shielding layer. The substrate supports the first electronic components. The first encapsulator encapsulates the first electronic components. The second electronic components are located above the substrate and exposed by the first encapsulator. The first shielding layer is adhered to the outer surface of the first encapsulator and configured to accommodate the second electronic components. Attached Figure Description

[0007] The aspects of this disclosure are better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale, and the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A This is a cross-section of a packaging structure according to some arrangements of this disclosure.

[0009] Figure 1B This is a top view of an encapsulation structure arranged according to some of the present disclosure.

[0010] Figure 2A This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure.

[0011] Figure 2B This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure.

[0012] Figure 2C This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure.

[0013] Figure 2D This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure.

[0014] Figure 2E This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure.

[0015] Figure 3A This is a cross-section of a packaging structure according to some arrangements of this disclosure.

[0016] Figure 3B This is a cross-section of a packaging structure according to some arrangements of this disclosure.

[0017] Figure 4 This is a top view of an encapsulation structure arranged according to some of the present disclosure.

[0018] Figures 5A to 5I The various stages of an exemplary method for forming an encapsulation structure according to some arrangements of this disclosure are shown.

[0019] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements. This disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0020] Figure 1A This is a cross-section of the encapsulation structure 1 according to some arrangements of the present disclosure. Figure 1BThis is a top view of an encapsulation structure 1 according to some arrangements of the present disclosure. In some arrangements, Figure 1A For along Figure 1B The cross-section of line 1A-1A' in the diagram. Package structure 1 may include a substrate 10, electronic components 20A, 20B, 30 and 70, an encapsulant 40, a shielding element 50, a barrier 60, connectors 60A and 60B, and electrical contacts 81. Package structure 1 may be or include a multiple system shielding module (MSSM).

[0021] Substrate 10 may comprise, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. Substrate 10 may comprise interconnect structures, such as multiple conductive traces and / or multiple conductive vias. In some arrangements, substrate 10 comprises a ceramic material, a metal plate, an organic substrate, or a lead frame. In some arrangements, substrate 10 may comprise two substrate layers, each comprising a core layer and conductive material and / or structures disposed on an upper and bottom surface of substrate 10. The conductive material and / or structure may comprise multiple conductive traces. Substrate 10 may comprise a surface 101, a surface 102 opposite to surface 101, and side surfaces 103 and 104 extending between surface 101 and surface 102. In some arrangements, substrate 10 includes conductive pads 120A, 120B, and 130 exposed from surface 101. In some arrangements, substrate 10 includes conductive pads 160A, 160B, 170, and 180 exposed from surface 102. Substrate 10 includes a grounding element 100g exposed from surface 101.

[0022] Electronic components 20A and 20B may be disposed above substrate 10. In some arrangements, electronic components 20A and 20B include surface mount devices (SMDs). Each of electronic components 20A and 20B may be a chip or die containing a semiconductor substrate, one or more integrated circuit devices, and one or more overlay interconnect structures. The integrated circuit devices may include active devices such as transistors, and / or passive devices such as resistors, capacitors, inductors, or combinations thereof. In some arrangements, electronic component 20A includes active devices (e.g., PMICs, ASICs, or the like), and electronic component 20B includes passive devices (e.g., capacitors or the like).

[0023] Electronic component 30 may be disposed above substrate 10. In some arrangements, the wafer node of electronic component 30 is smaller than that of electronic component 20A. In some arrangements, the wafer node of electronic component 30 is smaller than that of electronic component 20B. In some arrangements, the gate length of the transistor in electronic component 30 is smaller than that of the transistor in electronic component 20A. In some arrangements, the gate length of the transistor in electronic component 30 is smaller than that of the transistor in electronic component 20B. In some arrangements, the manufacturing cost of electronic component 30 is higher than that of electronic components 20A and 20B. In some arrangements, electronic component 30 has a top surface 30a (also referred to as the upper surface) and a bottom surface 30b (also referred to as the lower surface) facing substrate 10. In some arrangements, the bottom surface 30b is spaced apart from the surface 101 of substrate 10 by a gap G1 (or space). Gap G1 may be an air gap. Gap G1 (or space) may be defined by a barrier 60.

[0024] In some arrangements, electronic component 30 includes electronic devices 301 and 302, a redistribution layer (RDL) 30r, and an encapsulation layer 305 encapsulating electronic devices 301 and 302. In some embodiments, the wafer node of at least one of electronic devices 301 and 302 is smaller than the wafer node of electronic component 20A. In some embodiments, the gate length of at least one of electronic devices 301 and 302 is smaller than the gate length of one of electronic components 20A and 20B. RDL 30r may be located between electronic device 301 and substrate 10. In some arrangements, RDL 30r includes a conductive layer 30r1 and a dielectric layer 30d. Conductive layer 30r1 may include conductive traces and conductive vias. In some arrangements, RDL 30r further includes a ground element 30g exposed on the side of RDL 30r. In some arrangements, electronic device 301 is electrically connected to RDL 30r via conductive pad 320, connection element 301c, and conductive pad 301a. In some arrangements, electronic device 302 is electrically connected to electronic device 301 via conductive pad 301b, connection element 302c, and conductive pad 302a. Connection elements 301c and 302c may include solder elements. Electronic devices 301 and 302 may independently be or comprise system-on-a-chip (SoC), stacked package (PoP), MEMS, or the like. Electronic assembly 30 may be or comprise system-in-package (SiP).

[0025] In some arrangements, the connecting element 20c is between the substrate 10 and electronic components 20A and 20B. In some arrangements, electronic component 20A is electrically connected to conductive pad 120A of the substrate 10 via connecting element 20c and conductive pad 210. In some arrangements, electronic component 20B is electrically connected to conductive pad 120B of the substrate 10 via connecting element 20c. In some arrangements, the connecting element 30c is between the substrate 10 and electronic component 30. In some arrangements, electronic component 30 is electrically connected to conductive pad 130 of the substrate 10 via connecting element 30c and conductive pad 310. Connecting elements 20c and 30c may include solder elements.

[0026] A barrier 60 (also referred to as a “barrier structure” or “barrier element”) may be disposed above the substrate 10 and adjacent to the electronic assembly 30. In some arrangements, the barrier 60 is configured to prevent the shielding element 50 from extending toward the gap G1 between the electronic assembly 30 and the substrate 10 for electrical connection to the connection element 30c during sputtering operations. In some arrangements, the barrier 60 may act as a spacer or elevation element configured to reduce the extent or size of the portion 520 of the shielding element 50 that tapers toward the substrate 10, thereby preventing cracking or breakage of the shielding element 50. In some arrangements, the barrier 60 has a surface 601 facing upward (or away from the substrate 10) and configured to provide a deposition surface for the shielding element 50. In some arrangements, the barrier 60 includes at least a portion that overlaps with the electronic assembly 30 in a direction generally parallel to the surface 101 of the substrate 10, and said portion is configured to support the shielding element 50. Surface 601 may not be parallel to surface 101 of substrate 10 or may be inclined relative to said surface. Barrier 60 may be or comprise a dielectric layer. In some arrangements, grounding element 100g is exposed by encapsulation 40 and barrier 60. In some arrangements, the top tip 60t of barrier 60 is closer to the bottom surface 30b of electronic assembly 30 than to the top surface 30a. In some arrangements, the lateral edges 60e of barrier 60 are closer to electronic assembly 30 than to encapsulation 40. In some arrangements, barrier 60 contacts a portion of RDL 30r. In some arrangements, barrier 60 is configured to increase the bonding strength between electronic assembly 30 and substrate 10. Barrier 60 may be or comprise an insulating or dielectric material. In some arrangements, barrier 60 is or comprises a bottom filler. The bottom filler may comprise an epoxy resin with fillers dispersed therein, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide (PI), a phenolic compound or material, a polymeric material in which silicone is dispersed, or a combination thereof.

[0027] In some arrangements, a barrier 60 is located between the connecting element 30c and the shielding element 50. In some arrangements, the barrier 60 contacts at least one of the connecting elements 30c. In some arrangements, the barrier 60 does not contact at least one of the connecting elements 30c in the gap G1. In some cases, the connecting element 30c is exposed without a barrier around it, and the shielding element 50 is formed by a selective sputtering operation, i.e., sputtering the shielding element on a selected area above the encapsulation 40. In this case, the shielding element 50 can extend to contact the connecting element 30c when no barrier is placed between the connecting element 30c and the shielding element 50. In contrast, according to some arrangements of this disclosure, by designing the barrier 60 surrounding the connecting element 30c, the barrier 60 can prevent the shielding element 50 from contacting the connecting element 30c, and thus prevent the electronic assembly 30 from being undesirably connected to ground via the connecting element 30c contacting the shielding element 50. Therefore, yield can be improved.

[0028] In some arrangements, the barrier 60 is spaced apart from the grounding element 100g. In some arrangements, the barrier 60 protrudes a relatively small distance beyond the side of the electronic component 30. In some cases where shielding material is sputtered over the entire area covering the substrate 10, a mask may be positioned to cover the electronic component 30 to prevent sputtering of the shielding material. The sidewalls of the mask may be relatively thick and thus cover the grounding element 100g, and the shielding material may leak through the gap between the mask and the substrate 10 into the space between the electronic component 30 and the substrate 10, and the mask may shift and potentially collide with the electronic component 30, causing damage. In contrast, according to some arrangements of this disclosure, by designing the barrier 60 positioned around the connecting element 30c, the area covered by the barrier 60 above the surface 101 of the substrate 10 is relatively small, and therefore the grounding element 100g can be fully exposed to contact the shielding element 50. Therefore, yield can be improved. In some arrangements, the barrier 60 is configured such that the shielding element 50 is spaced apart from, rather than covering, the connecting element 30c, so that a gap G1 can be formed within the barrier 60 and the connecting element 30c is exposed. With the above design, the amount of barrier 60 can be relatively small, and therefore the KOZ can be reduced accordingly.

[0029] Encapsulation 40 may be disposed above surface 101 of substrate 10. In some arrangements, encapsulation 40 encapsulates electronic components 20A and 20B. In some arrangements, electronic component 30 is exposed by encapsulation 40. In some arrangements, encapsulation 40 includes trenches 40T penetrating encapsulation 40. In some arrangements, portions of surface 101 are exposed to trenches 40T. In some arrangements, conductive material may be filled in trenches 40T to form shielding element 40C. Shielding element 40C may be referred to as segmented shielding. Shielding element 40C provides electromagnetic interference (EMI) shielding between some of electronic components 20A and 20B. Shielding element 40C prevents EMI emissions from electronic components 20A and / or 20B on one side of shielding element 40C to electronic components 20A and / or 20B on the opposite side of shielding element 40C. Encapsulation 40 may comprise an epoxy resin having fillers dispersed therein, a molding compound (e.g., epoxy molding compound or other molding compound), PI, a phenolic compound or material, a polymeric material in which silicone is dispersed, or a combination thereof. Shielding element 40C may be or comprise conductive paste, conductive adhesive, or conductive film, for example, aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), mixtures, alloys, or other combinations thereof.

[0030] Encapsulation 40 can be referred to as a selective mold. Electronic components 20A and 20B encapsulated by encapsulation 40 can be referred to as system-in-package (SiP).

[0031] Shielding element 50 may be located above electronic components 20A, 20B, and 30. In some arrangements, shielding element 50 covers electronic components 20A, 20B, and 30. In some arrangements, shielding element 50 contacts electronic component 30, encapsulation 40, grounding element 100g, surface 101 of substrate 10, and sides 103 and 104 of substrate 10. In some arrangements, shielding element 50 is positioned along the outer side of encapsulation 40 and the outer side of electronic component 30. In some arrangements, shielding element 50 is adhered to the outer side of encapsulation 40 and configured to accommodate electronic devices 301 and 302 of electronic component 30. In some arrangements, shielding element 50 does not contact connecting element 30c. In some arrangements, shielding element 50 does not extend into the gap G1 between electronic component 30 and substrate 10 in a direction substantially perpendicular to surface 101 of substrate 10. In some arrangements, grounding element 100g is exposed by barrier 60 and contacts shielding element 50. In some arrangements, barrier 60 is located between connecting element 30c and shielding element 50. In some arrangements, barrier 60 is configured to space shielding element 50 from connecting element 30c. In some arrangements, grounding element 30g is exposed by barrier 60 and contacts shielding element 50. In some arrangements, barrier 60 is configured to reduce the extension of shielding element 50 toward the gap G1 between electronic assembly 30 and substrate 10. Shielding element 50 may be or comprise a conductive film, such as, for example, Al, Cu, Cr, Sn, Au, Ag, Ni, stainless steel, mixtures, alloys, or other combinations thereof. Shielding element 50 may comprise multiple conductive layers.

[0032] In some arrangements, the shielding element 50 includes portions 510, 520, 530, and 540. In some arrangements, portions 510, 520, 530, and 540 are integrally and conformally formed over the substrate 10, the electronic component 30, and the encapsulation 40. In some arrangements, portion 510 extends between the encapsulation 40 and the electronic component 30. In some arrangements, portion 510 has a thickness 510t that decreases towards the electronic component 30. In some arrangements, portion 510 has a thickness 510t that decreases from the encapsulation 40 towards the barrier 60. In some arrangements, portion 510 contacts the grounding element 100g.

[0033] In some arrangements, portion 520 extends along the sidewall of electronic component 30. In some arrangements, portion 520 contacts encapsulation layer 305. In some arrangements, portion 520 extends along the sidewall and ramp of encapsulation 40. In some arrangements, portion 520 contacts encapsulation 40. In some arrangements, portion 520 gradually narrows toward substrate 10. In some arrangements, portion 520 has a width 520w that decreases toward substrate 10. In some arrangements, portion 520 further extends above the sides 103 and 104 of substrate 10. In some arrangements, in addition to vertical walls, encapsulation 40 also provides ramps for portion 520 to be formed thereon, thereby improving the stepped coverage of shielding element 50 and also improving the uniformity of shielding element 50 above the entire package structure 1.

[0034] In some arrangements, portion 530 extends between substrate 10 and portion 520. In some arrangements, portion 530 gradually narrows toward portion 520. In some arrangements, portion 530 connects portion 510 to portion 520.

[0035] In some arrangements, portion 540 extends between portions 520 and above electronic component 30 and encapsulation 40. In some arrangements, portion 540 has a generally uniform thickness.

[0036] Connectors 60A and 60B can be connected to surface 102 of substrate 10. In some arrangements, connectors 60A and 60B may include an interposer layer. In some arrangements, connector 60A includes a base layer 60s (or core layer), RDLs 610r and 620r on opposite surfaces of the base layer 60s, and a conductive via 60v electrically connecting RDL 610r to RDL 620r. The base layer 60s may include a dielectric core layer. In some arrangements, RDL 610r includes a dielectric structure 610d and a conductive layer 610r1 within the dielectric structure 610d. The conductive layer 610r1 may include conductive traces and conductive vias. The dielectric structure 610d may include multiple dielectric layers. Connector 60A can be electrically connected to the conductive pad 160A of substrate 10 via a connecting element 60c1. A connecting element 60c2 can be disposed on and electrically connected to RDL 620r. In some arrangements, connector 60B includes a base layer 60s and a conductive via 60v penetrating the base layer 60s. Connector 60B can be electrically connected to a conductive pad 160B of the substrate via a connecting element 60c1. Connecting element 60c2 can be disposed on and electrically connected to the conductive via 60v of connector 60B. The base layer 60s may be or include a silicon layer, and the conductive via 60v may be or include a through-silicon via.

[0037] Electronic component 70 may be connected to surface 102 of substrate 10. In some arrangements, electronic component 70 is electrically connected to conductive pad 170 of the substrate via connection element 70c. Electronic component 70 may be or include a sensor, such as an IMU.

[0038] Electrical contact 81 may be connected to surface 102 of substrate 10. In some arrangements, electrical contact 81 is electrically connected to conductive pad 180 of substrate 10. In some arrangements, electrical contact 15 includes controlled collapse chip interconnect (C4) bumps, ball grid array (BGA), or connection disk grid array (LGA).

[0039] See Figure 1B In some arrangements, from a top view, the barrier 60 has a non-uniform width 60w. In some arrangements, the barrier 60 surrounds the connecting element 30c. In some arrangements, the gap G1 is surrounded and closed by the barrier 60. In some arrangements, the gap G1 (or space) is not completely filled by the barrier 60. In some arrangements, the grounding element 100g extends on the opposite side of the barrier 60. In some arrangements, from a top view, the encapsulation structure 1 has an outer edge 1e with an irregular shape.

[0040] Figure 2A This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure. Figure 2B This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure. In some arrangements, Figure 2A for Figure 1A The cross-section of part 2A, and Figure 2B for Figure 1A The cross-section of part 2B in the middle.

[0041] In some arrangements, an intermetallic compound (IMC) layer 20m1 is formed between an electronic component 20A (e.g., a conductive pad 210) and a connecting element 20c, and an IMC layer 20m2 is formed between the connecting element 20c and a substrate 10 (e.g., a conductive pad 120A). In some arrangements, the IMC layer 20m1 is formed of metal from the conductive pad 210 and the connecting element 20c. In some arrangements, the IMC layer 20m2 is formed of metal from the conductive pad 120A and the connecting element 20c. In some arrangements, the IMC layer 20m1 has a thickness T1, and the IMC layer 20m2 has a thickness T1' that is substantially the same as the thickness T1.

[0042] In some arrangements, an IMC layer 30m1 is formed between an electronic component 30 (e.g., a conductive pad 310) and a connecting element 30c, and an IMC layer 30m2 is formed between the connecting element 30c and a substrate 10 (e.g., a conductive pad 130). In some arrangements, the IMC layer 30m1 is formed of metal from the conductive pad 310 and the connecting element 30c. In some arrangements, the IMC layer 30m2 is formed of metal from the conductive pad 130 and the connecting element 30c. In some arrangements, the IMC layer 30m1 has a thickness T2, and the IMC layer 30m2 has a thickness T2' that is substantially the same as the thickness T2. In some arrangements, the thickness T1 is substantially the same as the thickness T2.

[0043] Figure 2C This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure. Figure 2D This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure. In some arrangements, Figure 2C for Figure 1A The cross-section of part 2C, and Figure 2D for Figure 1A A portion of the 2D cross-section.

[0044] In some arrangements, an IMC layer 81m is formed between an electrical contact 81 and a substrate 10 (e.g., a conductive pad 180). In some arrangements, the IMC layer 81m is formed of metal from the conductive pad 180 and the electrical contact 81. In some arrangements, the IMC layer 81m has a thickness T3 that is less than the thicknesses T1 and T2.

[0045] In some arrangements, an IMC layer 60m1 is formed between a substrate 10 (e.g., conductive pad 160A) and a connector 60c1, and an IMC layer 60m2 is formed between the connector 60c1 and a connector 60A (e.g., conductive pad 120A). In some arrangements, the IMC layer 60m1 is formed of metal from the conductive pad 160A and the connector 60c1. In some arrangements, the IMC layer 60m2 is formed of metal from the conductive layer 610r1 and the connector 60c1. In some arrangements, the IMC layer 60m1 has a thickness T4, and the IMC layer 60m2 has a thickness T4' that is substantially the same as the thickness T4. In some arrangements, the thickness T3 is substantially the same as the thickness T4.

[0046] Figure 2E This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure. In some arrangements, Figure 2E for Figure 1A The cross-section of part 2E.

[0047] In some arrangements, IMC layer 301m1 is formed between conductive pad 301a and connecting element 301c, and IMC layer 301m2 is formed between connecting element 301c and conductive pad 320. In some arrangements, IMC layer 301m1 is formed of metal from conductive pad 310a and connecting element 301c. In some arrangements, IMC layer 301m2 is formed of metal from conductive pad 320 and connecting element 60c1. In some arrangements, IMC layer 301m1 has a thickness T5, and IMC layer 301m2 has a thickness T5' that is substantially the same as the thickness T5. In some arrangements, thickness T5 is greater than thicknesses T1, T2, T3, and T4.

[0048] In some arrangements, during the formation of package structure 1, electronic device 301 is connected to RDL 30r via connecting element 301c through a reflow operation. IMC layers 301m1 and 301m2 can be formed through the reflow operation. In some arrangements, electronic components 20A, 20B, and 30 are connected to the substrate via connecting elements 20c and 30c through another reflow operation. IMC layers 20m1, 20m2, 30m1, and 30m2 can be formed through a reflow operation, which also thickens the already formed IMC layers 301m1 and 301m2. Next, in some arrangements, connector 60A is connected to substrate 10 via connecting element 60c1 through an additional reflow operation, and electrical contact 81 is connected to substrate 10 through the same additional reflow operation. This additional reflow operation thickens IMC layers 20m1, 20m2, 30m1, and 30m2, and further thickens IMC layers 301m1 and 301m2.

[0049] Figure 3A This is a cross-section of a package structure 3A according to some arrangements of the present disclosure. Package structure 3A is similar to... Figure 1A and Figure 1B The encapsulation structure 1 in the text is described below, and the differences between them are described below.

[0050] In some arrangements, electronic component 30 further includes a shielding element 90 covering an encapsulation layer 305. In some arrangements, shielding element 90 is located between electronic component 30 and shielding element 50. In some arrangements, shielding element 50 and shielding element 90 overlap vertically and horizontally. In some arrangements, shielding element 50 covers and contacts shielding element 90. In some arrangements, shielding element 50 includes shielding layers 51, 52, and 53, and shielding element 90 includes shielding layers 91, 92, and 93. In some arrangements, shielding layers 52 and 92 include Cu layers, and shielding layers 51, 53, 91, and 93 include stainless steel layers. In some arrangements, the interface 90s between shielding elements 50 and 90 may be unobservable.

[0051] In some arrangements, electronic component 30 includes electronic devices 301, 302, and 303, a redistribution layer (RDL) 30r, and an encapsulation layer 305 encapsulating electronic devices 301, 302, and 303. In some arrangements, electronic device 301 is electrically connected to RDL 30r via conductive pads 320, connection elements 301c, and conductive pads 301a. In some arrangements, electronic device 302 is electrically connected to electronic device 301 via conductive pads 301b, connection elements 302c, and conductive pads 302a. In some arrangements, electronic device 303 is electrically connected to electronic device 302 via conductive pads 302b, connection elements 303c, and conductive pads 303a. Connection elements 301c, 302c, and 303c may include solder elements. Electronic devices 301, 302, and 303 may be independently or comprise a system-on-a-chip (SoC), a multi-package (PoP), a MEMS, or the like.

[0052] Shielding element 90 covers a portion of RDL 30r. In some arrangements, barrier 60 is partially between shielding element 50 and shielding element 90. In some arrangements, a portion of encapsulation 40 extends between shielding element 50 and shielding element 90. In some arrangements, RDL 30r, shielding element 50, and shielding element 90 overlap in a direction generally parallel to the surface 101 of substrate 10. In some arrangements, RDL 30r, shielding element 50, barrier 60, and shielding element 90 overlap in a direction generally parallel to the surface 101 of substrate 10. In some arrangements, barrier 60 may be or comprise a non-conductive film (NCF). In some arrangements, the NCF acting as barrier 60 may have a convex curved surface 601.

[0053] Figure 3B This is a cross-section of the packaging structure 3B according to some arrangements of the present disclosure. The packaging structure 3B is similar to... Figure 3A The packaging structure 3A is described below, and the differences between them are described below.

[0054] In some arrangements, the package structure 3B further includes one or more metal plates 40P and one or more connecting elements 40c connecting the metal plates 40P to the substrate 10. In some arrangements, the metal plates 40P may act as shielding elements providing shielding functions similar to those provided by the shielding elements 40C. The metal plates 40P may be referred to as segmented shielding. The shielding element 50 may include a portion extending into the encapsulation 40 and contacting the metal plates 40P.

[0055] Figure 4 This is a top view of a package structure 4 according to some arrangements of the present disclosure. Package structure 4 is similar to... Figure 1A and Figure 1B The encapsulation structure 1 in the text is described below, and the differences between them are described below.

[0056] In some arrangements, from a top view, barrier 60 has a non-uniform width 60w. In some arrangements, barrier 60 surrounds connecting element 30c. In some arrangements, gap G1 is surrounded and closed by barrier 60. In some arrangements, grounding element 100g extends on the opposite side of barrier 60. In some arrangements, from a top view, encapsulation structure 4 has an irregularly shaped peripheral shape 4e.

[0057] Figures 5A to 5I The various stages of an exemplary method for forming an encapsulation structure 1 according to some arrangements of the present disclosure are shown.

[0058] See Figure 5A A substrate 10A may be provided, and electronic components 20A, 20B, and 30 may be disposed on or connected to the substrate 10A. In some arrangements, the substrate 10A is or comprises a wafer-level substrate structure. Electronic components 20A, 20B, and 30 may be bonded to the substrate 10A via connection elements 20c and 30c (e.g., solder elements). In some arrangements, electronic component 30 includes electronic devices 301 and 302 bonded to RDL 30r via connection elements 301c and 302c (e.g., solder elements) through a reflow operation (e.g., a first reflow operation). In some arrangements, electronic components 20A, 20B, and 30 are bonded to the substrate 10A via connection elements 20c and 30c (e.g., solder elements) through the same reflow operation (e.g., a second reflow operation). In some arrangements, the substrate 10A has a surface 101 and a surface 102 opposite to surface 101. In some arrangements, substrate 10A includes conductive pads 120A, 120B, and 130 and a grounding element 100g exposed from surface 101. In some arrangements, substrate 10 includes conductive pads 160A, 160B, 170, and 180 exposed from surface 102.

[0059] See Figure 5B Encapsulation 40 may be disposed over a portion of the surface 101 of substrate 10A to encapsulate electronic components 20A and 20B and expose electronic component 30. In some arrangements, encapsulation 40 may be referred to as selective mold.

[0060] See Figure 5C The trench 40T may be formed in the encapsulation 40. In some arrangements, the trench 40T penetrates the encapsulation 40. In some arrangements, a portion of the encapsulation 40 is removed by applying thermal energy via a laser using a laser device L1. In some arrangements, a portion of the surface 101 is exposed to the trench 40T.

[0061] See Figure 5DConductive material may be formed or filled in the trench 40T to form a shielding element 40C. In some arrangements, conductive paste or conductive adhesive is dispensed into the trench 40T to form the shielding element 40C. In some arrangements, metallic material may be placed or deposited in the trench 40T to form the shielding element 40C.

[0062] See Figure 5E A barrier 60 may be disposed around the connecting element 30c. In some arrangements, barrier material may be disposed or distributed around the connecting element 30c. The barrier material may be or contain an insulating material, such as an underfill material. In some arrangements, the amount of barrier material is sufficient to cover the outermost connecting element 30c to provide barrier function, but the amount of barrier material may not be excessive enough to extend above the grounding element 100g or even the encapsulation 40. Therefore, due to the fine control of the amount of barrier material distributed, the formed barrier 60 is formed to partially cover the sides of the encapsulation layer 305 and partially cover the connecting element 30c, and a gap G1 is formed between the electronic component 30 and the substrate 10. In some arrangements, some of the connecting elements 30c are exposed to or disposed within the gap G1.

[0063] See Figure 5F and Figure 5G , Figure 5G Show Figure 5F The diagram shows a top view of the stage. A splitting operation can be performed to form multiple package structures 1. In some arrangements, the splitting operation includes separating a substrate layer 10A into multiple substrates 10, each substrate having electronic components 20A, 20B, and 30 connected thereto. In some arrangements, a laser device L2 can be used to separate the package structure 1 by scanning a laser beam along at least one or more separation lines (e.g., lines S1 and S2). Separation lines may be referred to as scribing lines or cutting lines. Gap may be formed along lines S1 and S2. In some arrangements, the laser device L2 allows a laser beam to scan along irregularly shaped separation lines S1 and S2 to form a package structure 1 with an irregularly shaped peripheral edge 1e, which, from a top view, has an irregular shape.

[0064] See Figure 5H A shielding material may be formed over the exposed surfaces 101 of the electronic component 30, the encapsulation 40, and the substrate 10 to form a shielding element 50. In some arrangements, the shielding element 50 is conformally formed over the substrate 10, the electronic component 30, and the encapsulation 40. In some arrangements, the shielding material may be formed by sputtering. In some arrangements, the shielding material may be formed by physical vapor deposition (PVD). In some arrangements, the shielding material may be supplied from above the exposed surfaces 101 of the electronic component 30, the encapsulation 40, and the substrate 10, and reach the surfaces of the exposed surfaces 101 of the electronic component 30, the encapsulation 40, and the substrate 10 in a direction from the encapsulation 40 toward the substrate 10.

[0065] See Figure 5I Connectors 60A and 60B, electronic component 70, and electrical contact 81 can be connected to the surface 102 of substrate 10. Connectors 60A and 60B, along with electronic component 70, can be bonded to substrate 10 via connecting element 60c1 (e.g., solder element) in the same reflow operation (e.g., a third reflow operation). Thus, a [structure / structure] can be formed. Figure 1A and Figure 1B The packaging structure 1 is shown in the figure.

[0066] Unless otherwise specified, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” and “below” are relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not compromised by such arrangement.

[0067] As used herein, the terms “approximately,” “generally,” “roughly,” “about,” and “approximately” are used to describe and explain minor variations. When used in conjunction with an event or situation, these terms may refer to examples where the event or situation occurred precisely or very approximately. For example, when used in conjunction with a numerical value, these terms may refer to a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first value is within a range of variation less than or equal to ±10% of a second value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first value may be considered “generally” the same as or equal to the second value. For example, "roughly" vertical can refer to an angle variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0068] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered substantially flat.

[0069] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” may contain a plural or multiple indicators.

[0070] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials are those that offer little or no resistance to the flow of electric current. A unit of measurement for conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m, for example, at least 10 5 S / m or at least 10 6 A material with conductivity of S / m. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0071] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be flexibly interpreted as including not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0072] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and alternative equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, the process reproduction in this disclosure may differ from actual equipment. Other embodiments may exist that are not specifically described in this disclosure. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are considered to be included within the scope of the appended claims. Although the disclosed methods have been described herein with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A packaging structure comprising: Substrate; A first electronic component and a second electronic component, wherein the first electronic component and the second electronic component are disposed above the substrate; An encapsulation material that encapsulates the first electronic component and the second electronic component; as well as A third electronic component is exposed by the encapsulation, wherein the wafer node of the third electronic component is smaller than that of the first electronic component.

2. The packaging structure according to claim 1, wherein the first electronic component includes an active device, and the second electronic component includes a passive device.

3. The packaging structure according to claim 2, wherein the third electronic component includes a first electronic device, a second electronic device, and an encapsulation layer encapsulating the first electronic device and the second electronic device, the encapsulation layer being spaced apart from the substrate, and the wafer node of at least one of the first electronic device and the second electronic device being smaller than the wafer node of the first electronic component.

4. The packaging structure according to claim 3, further comprising: A connecting element that electrically connects the third electronic component to the substrate; as well as A shielding layer is disposed along the outer side of the encapsulation and the outer side of the third electronic component, wherein the shielding layer does not contact the connecting element.

5. The packaging structure according to claim 4, wherein the shielding layer does not extend into the gap between the third electronic component and the substrate in a direction substantially perpendicular to the surface of the substrate.

6. The packaging structure of claim 4, further comprising a barrier disposed above the substrate and configured to space the shielding layer from the connecting element.

7. The packaging structure of claim 6, wherein the barrier includes at least a portion that overlaps with the third electronic component in a direction substantially parallel to the surface of the substrate, and the portion is configured to support the shielding layer.

8. The packaging structure of claim 7, wherein the shielding layer includes a portion adhered to the side of the third electronic component and gradually narrowing toward the substrate.

9. The packaging structure of claim 6, wherein the barrier defines a space that exposes a portion of the bottom surface of the third electronic component.

10. A packaging structure comprising: A substrate, which includes a grounding element at the upper surface of the substrate; An encapsulation material disposed on the upper surface of the substrate and exposing the grounding element; An electronic component disposed on the upper surface of the substrate exposed by the encapsulation, wherein the grounding element is between the encapsulation and the electronic component; A connecting element disposed in the gap between the electronic component and the substrate and configured to electrically connect the electronic component to the substrate; as well as A dielectric layer that encapsulates the connection element and is spaced apart from the grounding element, wherein the gap is not completely filled by the dielectric layer.

11. The packaging structure of claim 10, wherein the lateral edge of the dielectric layer is closer to the electronic component than to the encapsulation.

12. The packaging structure according to claim 11, further comprising a shielding element between the grounding element and the dielectric layer.

13. The packaging structure of claim 12, wherein the dielectric layer has a surface that is not parallel to the upper surface of the substrate and is configured to support the shielding element.

14. The packaging structure of claim 11, wherein the dielectric layer has a non-uniform width when viewed from a top view.

15. A packaging structure comprising: Substrate; Multiple first electronic components are located above the substrate; The first package encapsulates the first electronic component; Multiple second electronic components are located above the substrate and exposed by the first encapsulation. as well as A first shielding layer is adhered to the outer side of the first encapsulation and configured to accommodate the second electronic component.

16. The packaging structure of claim 15, wherein the gate length of one of the plurality of second electronic components is less than the gate length of one of the plurality of first electronic components.

17. The packaging structure of claim 15, further comprising a second encapsulation material encapsulating the plurality of second electronic components, wherein the first shielding layer is located between the first encapsulation material and the second encapsulation material.

18. The packaging structure of claim 17, further comprising a second shielding layer between the plurality of first electronic components and the plurality of second electronic components.

19. The packaging structure of claim 18, wherein a portion of the first encapsulant extends between the first shielding layer and the second shielding layer.

20. The packaging structure of claim 15, further comprising a first connection element electrically connected to one of the plurality of first electronic components and a second connection element electrically connected to one of the plurality of second electronic components, wherein a first intermetallic compound (IMC) layer between the first connection element and the one of the first electronic components has a first thickness, and a second IMC layer between the second connection element and the one of the plurality of second electronic components has a second thickness substantially the same as the first thickness.

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